Changeset 64414 in vbox

Timestamp:

Oct 25, 2016 2:12:19 PM (8 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

111529

Message:

DevPCI: Moved ICH9PCIBUS to a common header (DevPciInternal.h) and use that for both PCI bus implementations.

Location:

trunk

Files:

• include/VBox/vmm/pdmpcidevint.h (modified) (6 diffs)
• src/VBox/Devices/Bus/DevPCI.cpp (modified) (35 diffs)
• src/VBox/Devices/Bus/DevPciIch9.cpp (modified) (32 diffs)
• src/VBox/Devices/Bus/DevPciInternal.h (added)
• src/VBox/Devices/Bus/DevPciMerge1.cpp.h (modified) (4 diffs)
• src/VBox/Devices/testcase/tstDeviceStructSize.cpp (modified) (1 diff)
• src/VBox/Devices/testcase/tstDeviceStructSizeRC.cpp (modified) (5 diffs)

trunk/include/VBox/vmm/pdmpcidevint.h

@@ -82 +82 @@
 
 /* Forward declaration */
-struct PCIBus;
+struct DEVPCIBUS;
 
 enum {
@@ -119 +119 @@
     PPDMDEVINSR3                    pDevInsR3;
     /** Pointer to the next PDM device associate with the PDM device. (R3 ptr) */
-    R3PTRTYPE(PPDMPCIDEV)        pNextR3;
+    R3PTRTYPE(PPDMPCIDEV)           pNextR3;
     /** Pointer to the internal PDM PCI bus for the device. (R3 ptr) */
     R3PTRTYPE(struct PDMPCIBUS *)   pPdmBusR3;
@@ -126 +126 @@
     PPDMDEVINSR0                    pDevInsR0;
     /** Pointer to the next PDM device associate with the PDM device. (R0 ptr) */
-    R0PTRTYPE(PPDMPCIDEV)        pNextR0;
+    R0PTRTYPE(PPDMPCIDEV)           pNextR0;
     /** Pointer to the internal PDM PCI bus for the device. (R0 ptr) */
     R0PTRTYPE(struct PDMPCIBUS *)   pPdmBusR0;
@@ -133 +133 @@
     PPDMDEVINSRC                    pDevInsRC;
     /** Pointer to the next PDM device associate with the PDM device. (RC ptr) */
-    RCPTRTYPE(PPDMPCIDEV)        pNextRC;
+    RCPTRTYPE(PPDMPCIDEV)           pNextRC;
     /** Pointer to the internal PDM PCI bus for the device. (RC ptr) */
     RCPTRTYPE(struct PDMPCIBUS *)   pPdmBusRC;
@@ -153 +153 @@
      */
     /** Pointer to the PCI bus of the device. (R3 ptr) */
-    R3PTRTYPE(struct PCIBus *)      pBusR3;
+    R3PTRTYPE(struct DEVPCIBUS *)   pBusR3;
     /** Page used for MSI-X state.             (R3 ptr) */
     R3PTRTYPE(void *)               pMsixPageR3;
@@ -168 +168 @@
 
     /** Pointer to the PCI bus of the device. (R0 ptr) */
-    R0PTRTYPE(struct PCIBus *)      pBusR0;
+    R0PTRTYPE(struct DEVPCIBUS *)   pBusR0;
     /** Page used for MSI-X state.             (R0 ptr) */
     R0PTRTYPE(void *)               pMsixPageR0;
 
     /** Pointer to the PCI bus of the device. (RC ptr) */
-    RCPTRTYPE(struct PCIBus *)      pBusRC;
+    RCPTRTYPE(struct DEVPCIBUS *)   pBusRC;
     /** Page used for MSI-X state.             (RC ptr) */
     RCPTRTYPE(void *)               pMsixPageRC;

trunk/src/VBox/Devices/Bus/DevPCI.cpp

@@ -2 +2 @@
 /** @file
  * DevPCI - PCI BUS Device.
+ *
+ * @remarks New code is currently added to DevPciMerge1.cpp.h, the goal is
+ *          to end up with a large common code base for the two PCI bus
+ *          implementations.  The merge file will soon be compiled separately
+ *          and not included, so it shall not be used as a template with
+ *          \#ifdefs for different PCI bus configs, but rather use config
+ *          flags in the structures to select paths & feature sets.
+ *
+ *          When moving code, always prefer the ICH9 version, not this!
  */
 
@@ -56 +65 @@
 #include "PciInline.h"
 #include "VBoxDD.h"
+#include "DevPciInternal.h"
 
 
@@ -61 +71 @@
 *   Structures and Typedefs                                                                                                      *
 *********************************************************************************************************************************/
+typedef DEVPCIBUS  PCIBUS;
+typedef PDEVPCIBUS PPCIBUS;
+
+
 /**
  * PIIX3 ISA Bridge state.
@@ -70 +84 @@
 } PIIX3State, PIIX3, *PPIIX3;
 
-/**
- * PCI Bus instance.
- */
-typedef struct PCIBus
-{
-    /** Bus number. */
-    int32_t             iBus;
-    /** Start device number. */
-    uint32_t            iDevSearch;
-    /** Number of bridges attached to the bus. */
-    uint32_t            cBridges;
-
-    uint32_t            Alignment0;
-
-    union
-    {
-        /** Array of PCI devices. */
-        R3PTRTYPE(PPDMPCIDEV) apDevices[256];
-        /** @deprecated   */
-        R3PTRTYPE(PPDMPCIDEV) devices[256];
-    };
-    /** Array of bridges attached to the bus. */
-    R3PTRTYPE(PPDMPCIDEV *) papBridgesR3;
-
-    /** R3 pointer to the device instance. */
-    PPDMDEVINSR3        pDevInsR3;
-    /** Pointer to the PCI R3  helpers. */
-    PCPDMPCIHLPR3       pPciHlpR3;
-
-    /** R0 pointer to the device instance. */
-    PPDMDEVINSR0        pDevInsR0;
-    /** Pointer to the PCI R0 helpers. */
-    PCPDMPCIHLPR0       pPciHlpR0;
-
-    /** RC pointer to the device instance. */
-    PPDMDEVINSRC        pDevInsRC;
-    /** Pointer to the PCI RC helpers. */
-    PCPDMPCIHLPRC       pPciHlpRC;
-
-    /** The PCI device for the PCI bridge. */
-    PDMPCIDEV           PciDev;
-
-} PCIBUS;
-/** Pointer to a PCIBUS instance. */
-typedef PCIBUS *PPCIBUS;
-typedef PCIBUS PCIBus;
-
 /** @def PCI_IRQ_PINS
  * Number of pins for interrupts (PIRQ#0...PIRQ#3)
@@ -133 +100 @@
 {
     /** Irq levels for the four PCI Irqs.
-     *  These count how many devices asserted
-     *  the IRQ line. If greater 0 an IRQ is sent to the guest.
-     *  If it drops to 0 the IRQ is deasserted.
+     * These count how many devices asserted the IRQ line. If greater 0 an IRQ is
+     * sent to the guest.  If it drops to 0 the IRQ is deasserted.
      */
     volatile uint32_t   pci_irq_levels[PCI_IRQ_PINS];
 
-#if 1 /* Will be moved into the BIOS soon. */
+#if 1 /* Will be moved into the BIOS "soon". */
     /** The next I/O port address which the PCI BIOS will use. */
-    uint32_t            pci_bios_io_addr;
+    uint32_t            uPciBiosIo;
     /** The next MMIO address which the PCI BIOS will use. */
-    uint32_t            pci_bios_mem_addr;
+    uint32_t            uPciBiosMmio;
     /** Actual bus number. */
     uint8_t             uBus;
+    uint8_t             uAlignment0[2];
 #endif
 
@@ -151 +118 @@
     bool                fUseIoApic;
     /** I/O APIC irq levels */
-    volatile uint32_t   pci_apic_irq_levels[PCI_APIC_IRQ_PINS];
+    volatile uint32_t   uaPciApicIrqLevels[PCI_APIC_IRQ_PINS];
     /** ACPI IRQ level */
     uint32_t            acpi_irq_level;
     /** ACPI PIC IRQ */
     int                 acpi_irq;
-    /** Config register. */
+    /** Value latched in Configuration Address Port (0CF8h) */
     uint32_t            uConfigReg;
 
@@ -173 +140 @@
     PIIX3               PIIX3State;
     /** PCI bus which is attached to the host-to-PCI bridge. */
-    PCIBUS              PciBus;
+    DEVPCIBUS           PciBus;
 
 } PCIGLOBALS;
@@ -188 +155 @@
 /** Converts a PCI bus device instance pointer to a PCIGLOBALS pointer. */
 #define DEVINS_2_PCIGLOBALS(pDevIns)    ((PPCIGLOBALS)(PDMINS_2_DATA(pDevIns, PPCIGLOBALS)))
-/** Converts a PCI bus device instance pointer to a PCIBUS pointer. */
+/** Converts a PCI bus device instance pointer to a DEVPCIBUS pointer. */
 #define DEVINS_2_PCIBUS(pDevIns)        ((PPCIBUS)(&PDMINS_2_DATA(pDevIns, PPCIGLOBALS)->PciBus))
 
@@ -529 +496 @@
     else
     {
-        R3PTRTYPE(PDMPCIDEV *) pci_dev = pGlobals->PciBus.devices[iDevice];
+        R3PTRTYPE(PDMPCIDEV *) pci_dev = pGlobals->PciBus.apDevices[iDevice];
         if (pci_dev)
         {
@@ -576 +543 @@
     else
     {
-        R3PTRTYPE(PDMPCIDEV *) pci_dev = pGlobals->PciBus.devices[iDevice];
+        R3PTRTYPE(PDMPCIDEV *) pci_dev = pGlobals->PciBus.apDevices[iDevice];
         if (pci_dev)
         {
@@ -612 +579 @@
 static inline int get_pci_irq_apic_level(PPCIGLOBALS pGlobals, int irq_num)
 {
-    return (pGlobals->pci_apic_irq_levels[irq_num] != 0);
+    return (pGlobals->uaPciApicIrqLevels[irq_num] != 0);
 }
 
@@ -626 +593 @@
 
         if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
-            ASMAtomicIncU32(&pGlobals->pci_apic_irq_levels[irq_num]);
+            ASMAtomicIncU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
         else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
-            ASMAtomicDecU32(&pGlobals->pci_apic_irq_levels[irq_num]);
+            ASMAtomicDecU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
 
         apic_irq = irq_num + 0x10;
@@ -637 +604 @@
 
         if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
-            ASMAtomicDecU32(&pGlobals->pci_apic_irq_levels[irq_num]);
+            ASMAtomicDecU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
             pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
             apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
@@ -998 +965 @@
                  * through the bridge but we want to be compliant to the spec.
                  */
-                if ((pGlobals->pci_bios_io_addr % 4096) != 0)
-                    pGlobals->pci_bios_io_addr = RT_ALIGN_32(pGlobals->pci_bios_io_addr, 4*1024);
-                Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->pci_bios_io_addr));
-                pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->pci_bios_io_addr >> 8) & 0xf0);
+                if ((pGlobals->uPciBiosIo % 4096) != 0)
+                    pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
+                Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosIo));
+                pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0);
 
                 /* The MMIO range for the bridge must be aligned to a 1MB boundary. */
-                if ((pGlobals->pci_bios_mem_addr % (1024 * 1024)) != 0)
-                    pGlobals->pci_bios_mem_addr = RT_ALIGN_32(pGlobals->pci_bios_mem_addr, 1024*1024);
-                Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->pci_bios_mem_addr));
-                pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->pci_bios_mem_addr >> 16) & UINT32_C(0xffff0));
+                if ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0)
+                    pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
+                Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosMmio));
+                pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0));
 
                 /* Save values to compare later to. */
-                uint32_t u32IoAddressBase = pGlobals->pci_bios_io_addr;
-                uint32_t u32MMIOAddressBase = pGlobals->pci_bios_mem_addr;
+                uint32_t u32IoAddressBase = pGlobals->uPciBiosIo;
+                uint32_t u32MMIOAddressBase = pGlobals->uPciBiosMmio;
 
                 /* Init devices behind the bridge and possibly other bridges as well. */
@@ -1026 +993 @@
                  * interface. Again this doesn't really matter here but we want to be compliant to the spec.
                  */
-                if ((u32IoAddressBase != pGlobals->pci_bios_io_addr) && ((pGlobals->pci_bios_io_addr % 4096) != 0))
+                if ((u32IoAddressBase != pGlobals->uPciBiosIo) && ((pGlobals->uPciBiosIo % 4096) != 0))
                 {
                     /* The upper boundary must be one byte less than a 4KB boundary. */
-                    pGlobals->pci_bios_io_addr = RT_ALIGN_32(pGlobals->pci_bios_io_addr, 4*1024);
+                    pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
                 }
-                pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->pci_bios_io_addr >> 8) & 0xf0) - 1);
+                pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1);
 
                 /* Same with the MMIO limit register but with 1MB boundary here. */
-                if ((u32MMIOAddressBase != pGlobals->pci_bios_mem_addr) && ((pGlobals->pci_bios_mem_addr % (1024 * 1024)) != 0))
+                if ((u32MMIOAddressBase != pGlobals->uPciBiosMmio) && ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0))
                 {
                     /* The upper boundary must be one byte less than a 1MB boundary. */
-                    pGlobals->pci_bios_mem_addr = RT_ALIGN_32(pGlobals->pci_bios_mem_addr, 1024*1024);
+                    pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
                 }
-                pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->pci_bios_mem_addr >> 16) & UINT32_C(0xfff0)) - 1);
+                pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1);
 
                 /*
@@ -1093 +1060 @@
                     {
                         if (fIsPio)
-                            paddr = &pGlobals->pci_bios_io_addr;
+                            paddr = &pGlobals->uPciBiosIo;
                         else
-                            paddr = &pGlobals->pci_bios_mem_addr;
+                            paddr = &pGlobals->uPciBiosMmio;
                         uint32_t uNew = *paddr;
                         uNew = (uNew + u32Size - 1) & ~(u32Size - 1);
@@ -1249 +1216 @@
  *       as a possible file #2 contains external code if there's any left.
  */
-typedef PPCIBUS PPCIMERGEDBUS;
 # define pciR3UnmergedConfigReadDev  pci_default_read_config
 # define pciR3UnmergedConfigWriteDev pci_default_write_config
@@ -1269 +1235 @@
      * Iterate thru all the devices.
      */
-    for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
-    {
-        PPDMPCIDEV pDev = pBus->devices[i];
+    for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
+    {
+        PPDMPCIDEV pDev = pBus->apDevices[i];
         if (pDev)
         {
@@ -1306 +1272 @@
         SSMR3PutU32(pSSM, pThis->pci_irq_levels[i]);
     for (i = 0; i < PCI_APIC_IRQ_PINS; i++)
-        SSMR3PutU32(pSSM, pThis->pci_apic_irq_levels[i]);
+        SSMR3PutU32(pSSM, pThis->uaPciApicIrqLevels[i]);
 
     SSMR3PutU32(pSSM, pThis->acpi_irq_level);
@@ -1511 +1477 @@
      * LogRels in pciR3CommonRestoreConfig.
      */
-    for (i = 0; i < RT_ELEMENTS(pBus->devices); i++)
-    {
-        PPDMPCIDEV pDev = pBus->devices[i];
+    for (i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
+    {
+        PPDMPCIDEV pDev = pBus->apDevices[i];
         if (pDev)
         {
@@ -1537 +1503 @@
         if (u32 == (uint32_t)~0)
             break;
-        if (    u32 >= RT_ELEMENTS(pBus->devices)
+        if (    u32 >= RT_ELEMENTS(pBus->apDevices)
             ||  u32 < i)
         {
@@ -1547 +1513 @@
         for (; i < u32; i++)
         {
-            if (pBus->devices[i])
+            if (pBus->apDevices[i])
             {
-                LogRel(("PCI: New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pBus->devices[i]->pszNameR3,
-                        PCIDevGetVendorId(pBus->devices[i]), PCIDevGetDeviceId(pBus->devices[i])));
+                LogRel(("PCI: New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pBus->apDevices[i]->pszNameR3,
+                        PCIDevGetVendorId(pBus->apDevices[i]), PCIDevGetDeviceId(pBus->apDevices[i])));
                 if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
                     return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
-                                            i, pBus->devices[i]->pszNameR3, PCIDevGetVendorId(pBus->devices[i]), PCIDevGetDeviceId(pBus->devices[i]));
+                                            i, pBus->apDevices[i]->pszNameR3, PCIDevGetVendorId(pBus->apDevices[i]), PCIDevGetDeviceId(pBus->apDevices[i]));
             }
         }
@@ -1576 +1542 @@
 
         /* check that it's still around. */
-        pDev = pBus->devices[i];
+        pDev = pBus->apDevices[i];
         if (!pDev)
         {
@@ -1633 +1599 @@
             SSMR3GetU32(pSSM, (uint32_t *)&pThis->pci_irq_levels[i]);
         for (uint8_t i = 0; i < PCI_APIC_IRQ_PINS; i++)
-            SSMR3GetU32(pSSM, (uint32_t *)&pThis->pci_apic_irq_levels[i]);
+            SSMR3GetU32(pSSM, (uint32_t *)&pThis->uaPciApicIrqLevels[i]);
 
         SSMR3GetU32(pSSM, &pThis->acpi_irq_level);
@@ -1736 +1702 @@
      * Set the start addresses.
      */
-    pGlobals->pci_bios_io_addr  = 0xd000;
-    pGlobals->pci_bios_mem_addr = UINT32_C(0xf0000000);
+    pGlobals->uPciBiosIo  = 0xd000;
+    pGlobals->uPciBiosMmio = UINT32_C(0xf0000000);
     pGlobals->uBus = 0;
 
@@ -1814 +1780 @@
     for (int i = 0; i < PCI_APIC_IRQ_PINS; ++i)
     {
-        pHlp->pfnPrintf(pHlp, "  IRQ%02d: %u\n", 0x10 + i, pGlobals->pci_apic_irq_levels[i]);
+        pHlp->pfnPrintf(pHlp, "  IRQ%02d: %u\n", 0x10 + i, pGlobals->uaPciApicIrqLevels[i]);
     }
 }
@@ -1841 +1807 @@
 static void pciR3BusInfo(PPCIBUS pBus, PCDBGFINFOHLP pHlp, int iIndent, bool fRegisters)
 {
-    for (uint32_t iDev = 0; iDev < RT_ELEMENTS(pBus->devices); iDev++)
-    {
-        PPDMPCIDEV pPciDev = pBus->devices[iDev];
+    for (uint32_t iDev = 0; iDev < RT_ELEMENTS(pBus->apDevices); iDev++)
+    {
+        PPDMPCIDEV pPciDev = pBus->apDevices[iDev];
         if (pPciDev != NULL)
         {
@@ -1978 +1944 @@
 
     /* Relocate RC pointers for the attached pci devices. */
-    for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
-    {
-        if (pBus->devices[i])
-            pBus->devices[i]->Int.s.pBusRC += offDelta;
+    for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
+    {
+        if (pBus->apDevices[i])
+            pBus->apDevices[i]->Int.s.pBusRC += offDelta;
     }
 }
@@ -2036 +2002 @@
      */
     PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
-    pGlobals->pci_bios_io_addr    = 0xc000;
-    pGlobals->pci_bios_mem_addr   = 0xf0000000;
+    pGlobals->uPciBiosIo    = 0xc000;
+    pGlobals->uPciBiosMmio   = 0xf0000000;
     memset((void *)&pGlobals->pci_irq_levels, 0, sizeof(pGlobals->pci_irq_levels));
     pGlobals->fUseIoApic          = fUseIoApic;
-    memset((void *)&pGlobals->pci_apic_irq_levels, 0, sizeof(pGlobals->pci_apic_irq_levels));
+    memset((void *)&pGlobals->uaPciApicIrqLevels, 0, sizeof(pGlobals->uaPciApicIrqLevels));
 
     pGlobals->pDevInsR3 = pDevIns;
@@ -2050 +2016 @@
     pGlobals->PciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
     pGlobals->PciBus.papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns,   sizeof(PPDMPCIDEV)
-                                                                                 * RT_ELEMENTS(pGlobals->PciBus.devices));
+                                                                                 * RT_ELEMENTS(pGlobals->PciBus.apDevices));
 
     PDMPCIBUSREG PciBusReg;
@@ -2268 +2234 @@
     {
         /* This is the target bus, pass the write to the device. */
-        PPDMPCIDEV pPciDev = pBus->devices[iDevice];
+        PPDMPCIDEV pPciDev = pBus->apDevices[iDevice];
         if (pPciDev)
         {
@@ -2301 +2267 @@
     {
         /* This is the target bus, pass the read to the device. */
-        PPDMPCIDEV pPciDev = pBus->devices[iDevice];
+        PPDMPCIDEV pPciDev = pBus->apDevices[iDevice];
         if (pPciDev)
         {
@@ -2358 +2324 @@
 
     /* Relocate RC pointers for the attached pci devices. */
-    for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
-    {
-        if (pBus->devices[i])
-            pBus->devices[i]->Int.s.pBusRC += offDelta;
+    for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
+    {
+        if (pBus->apDevices[i])
+            pBus->apDevices[i]->Int.s.pBusRC += offDelta;
     }
 }
@@ -2401 +2367 @@
     pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
     pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
-    pBus->papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) * RT_ELEMENTS(pBus->devices));
+    pBus->papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) * RT_ELEMENTS(pBus->apDevices));
 
     PDMPCIBUSREG PciBusReg;
@@ -2504 +2470 @@
     ~0U,
     /* cbInstance */
-    sizeof(PCIBUS),
+    sizeof(DEVPCIBUS),
     /* pfnConstruct */
     pcibridgeR3Construct,

trunk/src/VBox/Devices/Bus/DevPciIch9.cpp

@@ -3 +3 @@
  * DevPCI - ICH9 southbridge PCI bus emulation device.
  *
- * @note    bird: I've cleaned up DevPCI.cpp to some extent, this file has not
- *                be cleaned up and because of pending code merge.
+ * @remarks New code is currently added to DevPciMerge1.cpp.h, the goal is
+ *          to end up with a large common code base for the two PCI bus
+ *          implementations.  The merge file will soon be compiled separately
+ *          and not included, so it shall not be used as a template with
+ *          \#ifdefs for different PCI bus configs, but rather use config
+ *          flags in the structures to select paths & feature sets.
+ *
+ *          When moving code, always prefer the ICH9 version (this file)!
  */
 
@@ -24 +30 @@
 *********************************************************************************************************************************/
 #define LOG_GROUP LOG_GROUP_DEV_PCI
-#define PCIBus    ICH9PCIBus        /**< HACK ALERT! Real ugly type hack! */
 #define PDMPCIDEV_INCLUDE_PRIVATE  /* Hack to get pdmpcidevint.h included at the right point. */
 #include <VBox/vmm/pdmpcidev.h>
@@ -41 +46 @@
 #include "VBoxDD.h"
 #include "MsiCommon.h"
+#include "DevPciInternal.h"
 
 
@@ -46 +52 @@
 *   Structures and Typedefs                                                                                                      *
 *********************************************************************************************************************************/
-/**
- * PCI Bus instance.
- */
-typedef struct ICH9PCIBus
-{
-    /** Bus number. */
-    int32_t             iBus;
-    /** Number of bridges attached to the bus. */
-    uint32_t            cBridges;
-
-    /** Array of PCI devices. We assume 32 slots, each with 8 functions. */
-    R3PTRTYPE(PPDMPCIDEV)   apDevices[256];
-    /** Array of bridges attached to the bus. */
-    R3PTRTYPE(PPDMPCIDEV *) papBridgesR3;
-
-    /** R3 pointer to the device instance. */
-    PPDMDEVINSR3        pDevInsR3;
-    /** Pointer to the PCI R3  helpers. */
-    PCPDMPCIHLPR3       pPciHlpR3;
-
-    /** R0 pointer to the device instance. */
-    PPDMDEVINSR0        pDevInsR0;
-    /** Pointer to the PCI R0 helpers. */
-    PCPDMPCIHLPR0       pPciHlpR0;
-
-    /** RC pointer to the device instance. */
-    PPDMDEVINSRC        pDevInsRC;
-    /** Pointer to the PCI RC helpers. */
-    PCPDMPCIHLPRC       pPciHlpRC;
-
-    /** The PCI device for the PCI bridge. */
-    PDMPCIDEV           aPciDev;
-
-    /** Start device number - always zero (only for DevPCI source compat). */
-    uint32_t            iDevSearch;
-    /** Size alignemnt padding. */
-    uint32_t            u32Alignment;
-} ICH9PCIBUS, *PICH9PCIBUS;
+typedef DEVPCIBUS  ICH9PCIBUS;
+typedef PDEVPCIBUS PICH9PCIBUS;
 
 
@@ -109 +79 @@
     volatile uint32_t   uaPciApicIrqLevels[PCI_APIC_IRQ_PINS];
 
-#if 1 /* Will be moved into the BIOS soon. */
+#if 1 /* Will be moved into the BIOS "soon". */
     /** The next I/O port address which the PCI BIOS will use. */
     uint32_t            uPciBiosIo;
@@ -126 +96 @@
 
     /** PCI bus which is attached to the host-to-PCI bridge. */
-    ICH9PCIBUS          aPciBus;
+    DEVPCIBUS           PciBus;
 } ICH9PCIGLOBALS, *PICH9PCIGLOBALS;
 
@@ -159 +129 @@
 #define DEVINS_2_PCIGLOBALS(pDevIns)    ((PICH9PCIGLOBALS)(PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS)))
 /** Converts a device instance pointer to a PCIBUS pointer. */
-#define DEVINS_2_PCIBUS(pDevIns)        ((PICH9PCIBUS)(&PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS)->aPciBus))
+#define DEVINS_2_PCIBUS(pDevIns)        ((PICH9PCIBUS)(&PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS)->PciBus))
 /** Converts a pointer to a PCI root bus instance to a PCIGLOBALS pointer. */
-#define PCIROOTBUS_2_PCIGLOBALS(pPciBus)    ( (PICH9PCIGLOBALS)((uintptr_t)(pPciBus) - RT_OFFSETOF(ICH9PCIGLOBALS, aPciBus)) )
+#define PCIROOTBUS_2_PCIGLOBALS(pPciBus)    ( (PICH9PCIGLOBALS)((uintptr_t)(pPciBus) - RT_OFFSETOF(ICH9PCIGLOBALS, PciBus)) )
 
 /** @def PCI_LOCK
@@ -228 +198 @@
     do
     {
-        uDevFnBridge  = pBus->aPciDev.uDevFn;
+        uDevFnBridge  = pBus->PciDev.uDevFn;
         iIrqPinBridge = ((pPciDevBus->uDevFn >> 3) + iIrqPinBridge) & 3;
 
         /* Get the parent. */
-        pBus = pBus->aPciDev.Int.s.CTX_SUFF(pBus);
-        pPciDevBus = &pBus->aPciDev;
+        pBus = pBus->PciDev.Int.s.CTX_SUFF(pBus);
+        pPciDevBus = &pBus->PciDev;
     } while (pBus->iBus != 0);
 
@@ -327 +297 @@
     if (pAddr->iBus != 0)       /* forward to subordinate bus */
     {
-        if (pGlobals->aPciBus.cBridges)
+        if (pGlobals->PciBus.cBridges)
         {
 #ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
-            PPDMPCIDEV pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pAddr->iBus);
+            PPDMPCIDEV pBridgeDevice = ich9pciFindBridge(&pGlobals->PciBus, pAddr->iBus);
             if (pBridgeDevice)
             {
@@ -344 +314 @@
     else                    /* forward to directly connected device */
     {
-        R3PTRTYPE(PDMPCIDEV *) pPciDev = pGlobals->aPciBus.apDevices[pAddr->iDeviceFunc];
+        R3PTRTYPE(PDMPCIDEV *) pPciDev = pGlobals->PciBus.apDevices[pAddr->iDeviceFunc];
         if (pPciDev)
         {
@@ -440 +410 @@
     if (pPciAddr->iBus != 0)    /* forward to subordinate bus */
     {
-        if (pGlobals->aPciBus.cBridges)
+        if (pGlobals->PciBus.cBridges)
         {
 #ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
-            PPDMPCIDEV pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pPciAddr->iBus);
+            PPDMPCIDEV pBridgeDevice = ich9pciFindBridge(&pGlobals->PciBus, pPciAddr->iBus);
             if (pBridgeDevice)
             {
@@ -461 +431 @@
     else                    /* forward to directly connected device */
     {
-        R3PTRTYPE(PDMPCIDEV *) pPciDev = pGlobals->aPciBus.apDevices[pPciAddr->iDeviceFunc];
+        R3PTRTYPE(PDMPCIDEV *) pPciDev = pGlobals->PciBus.apDevices[pPciAddr->iDeviceFunc];
         if (pPciDev)
         {
@@ -631 +601 @@
         Assert(!MsixIsEnabled(pPciDev));    /* Not allowed -- see note above. */
         LogFlowFunc(("PCI Dev %p : MSI\n", pPciDev));
-        PPDMDEVINS pDevIns = pGlobals->aPciBus.CTX_SUFF(pDevIns);
-        MsiNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
+        PPDMDEVINS pDevIns = pGlobals->PciBus.CTX_SUFF(pDevIns);
+        MsiNotify(pDevIns, pGlobals->PciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
         return;
     }
@@ -639 +609 @@
     {
         LogFlowFunc(("PCI Dev %p : MSI-X\n", pPciDev));
-        PPDMDEVINS pDevIns = pGlobals->aPciBus.CTX_SUFF(pDevIns);
-        MsixNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
+        PPDMDEVINS pDevIns = pGlobals->PciBus.CTX_SUFF(pDevIns);
+        MsixNotify(pDevIns, pGlobals->PciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
         return;
     }
 
-    PICH9PCIBUS     pBus      =     &pGlobals->aPciBus;
+    PICH9PCIBUS     pBus      =     &pGlobals->PciBus;
     const bool  fIsAcpiDevice = PCIDevGetDeviceId(pPciDev) == 0x7113;
 
@@ -784 +754 @@
  *       as a possible file #2 contains external code if there's any left.
  */
-typedef PICH9PCIBUS PPCIMERGEDBUS;
 # define pciR3UnmergedConfigReadDev  ich9pciConfigReadDev
 # define pciR3UnmergedConfigWriteDev ich9pciConfigWriteDev
@@ -1121 +1090 @@
     SSMR3PutU32(pSSM, UINT32_MAX);  /* separator */
 
-    return ich9pciR3CommonSaveExec(&pThis->aPciBus, pSSM);
+    return ich9pciR3CommonSaveExec(&pThis->PciBus, pSSM);
 }
 
@@ -1139 +1108 @@
 
     /* If the current bus is not the target bus search for the bus which contains the device. */
-    if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
+    if (iBus != PCIDevGetByte(&pBus->PciDev, VBOX_PCI_SECONDARY_BUS))
     {
         PPDMPCIDEV pBridgeDevice = ich9pciFindBridge(pBus, iBus);
@@ -1169 +1138 @@
 
     /* If the current bus is not the target bus search for the bus which contains the device. */
-    if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
+    if (iBus != PCIDevGetByte(&pBus->PciDev, VBOX_PCI_SECONDARY_BUS))
     {
         PPDMPCIDEV pBridgeDevice = ich9pciFindBridge(pBus, iBus);
@@ -1516 +1485 @@
 {
     PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
-    PICH9PCIBUS     pBus  = &pThis->aPciBus;
+    PICH9PCIBUS     pBus  = &pThis->PciBus;
     uint32_t        u32;
     int             rc;
@@ -1855 +1824 @@
         {
             /* Find bus this device attached to. */
-            PICH9PCIBUS pBus = &pGlobals->aPciBus;
+            PICH9PCIBUS pBus = &pGlobals->PciBus;
             while (1)
             {
@@ -1878 +1847 @@
             {
                 /* Get the pin the device would assert on the bridge. */
-                iPin = ((pBus->aPciDev.uDevFn >> 3) + iPin) & 3;
-                pBus = pBus->aPciDev.Int.s.pBusR3;
+                iPin = ((pBus->PciDev.uDevFn >> 3) + iPin) & 3;
+                pBus = pBus->PciDev.Int.s.pBusR3;
             };
         }
@@ -1902 +1871 @@
                                       unsigned uBusSecondary)
 {
-    PPDMPCIDEV pBridgeDev = &pBus->aPciDev;
+    PPDMPCIDEV pBridgeDev = &pBus->PciDev;
 
     /* Set only if we are not on the root bus, it has no primary bus attached. */
@@ -1956 +1925 @@
      * Assign bridge topology, for further routing to work.
      */
-    PICH9PCIBUS pBus = &pGlobals->aPciBus;
+    PICH9PCIBUS pBus = &pGlobals->PciBus;
     ich9pciInitBridgeTopology(pGlobals, pBus, 0, 0);
 
@@ -2431 +2400 @@
      */
     PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
-    PICH9PCIBUS     pBus     = &pGlobals->aPciBus;
+    PICH9PCIBUS     pBus     = &pGlobals->PciBus;
     /* Zero out everything */
     memset(pGlobals, 0, sizeof(*pGlobals));
@@ -2451 +2420 @@
     pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
 
-    pGlobals->aPciBus.pDevInsR3 = pDevIns;
-    pGlobals->aPciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
-    pGlobals->aPciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
-    pGlobals->aPciBus.papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) * RT_ELEMENTS(pGlobals->aPciBus.apDevices));
+    pGlobals->PciBus.pDevInsR3 = pDevIns;
+    pGlobals->PciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
+    pGlobals->PciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
+    pGlobals->PciBus.papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) * RT_ELEMENTS(pGlobals->PciBus.apDevices));
 
     /*
@@ -2491 +2460 @@
 #if 0
     /* Host bridge device */
-    PCIDevSetVendorId(  &pBus->aPciDev, 0x8086); /* Intel */
-    PCIDevSetDeviceId(  &pBus->aPciDev, 0x29e0); /* Desktop */
-    PCIDevSetRevisionId(&pBus->aPciDev,   0x01); /* rev. 01 */
-    PCIDevSetClassBase( &pBus->aPciDev,   0x06); /* bridge */
-    PCIDevSetClassSub(  &pBus->aPciDev,   0x00); /* Host/PCI bridge */
-    PCIDevSetClassProg( &pBus->aPciDev,   0x00); /* Host/PCI bridge */
-    PCIDevSetHeaderType(&pBus->aPciDev,   0x00); /* bridge */
-    PCIDevSetWord(&pBus->aPciDev,  VBOX_PCI_SEC_STATUS, 0x0280);  /* secondary status */
-
-    pBus->aPciDev.pDevIns               = pDevIns;
+    PCIDevSetVendorId(  &pBus->PciDev, 0x8086); /* Intel */
+    PCIDevSetDeviceId(  &pBus->PciDev, 0x29e0); /* Desktop */
+    PCIDevSetRevisionId(&pBus->PciDev,   0x01); /* rev. 01 */
+    PCIDevSetClassBase( &pBus->PciDev,   0x06); /* bridge */
+    PCIDevSetClassSub(  &pBus->PciDev,   0x00); /* Host/PCI bridge */
+    PCIDevSetClassProg( &pBus->PciDev,   0x00); /* Host/PCI bridge */
+    PCIDevSetHeaderType(&pBus->PciDev,   0x00); /* bridge */
+    PCIDevSetWord(&pBus->PciDev,  VBOX_PCI_SEC_STATUS, 0x0280);  /* secondary status */
+
+    pBus->PciDev.pDevIns               = pDevIns;
     /* We register Host<->PCI controller on the bus */
-    ich9pciRegisterInternal(pBus, 0, &pBus->aPciDev, "dram");
+    ich9pciRegisterInternal(pBus, 0, &pBus->PciDev, "dram");
 #endif
 
@@ -2630 +2599 @@
 {
     PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
-    PICH9PCIBUS     pBus     = &pGlobals->aPciBus;
+    PICH9PCIBUS     pBus     = &pGlobals->PciBus;
 
     /* PCI-specific reset for each device. */
@@ -2664 +2633 @@
 {
     PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
-    PICH9PCIBUS     pBus     = &pGlobals->aPciBus;
+    PICH9PCIBUS     pBus     = &pGlobals->PciBus;
     pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
 
@@ -2744 +2713 @@
      * Fill in PCI configs and add them to the bus.
      */
-    PCIDevSetVendorId(  &pBus->aPciDev, 0x8086); /* Intel */
-    PCIDevSetDeviceId(  &pBus->aPciDev, 0x2448); /* 82801 Mobile PCI bridge. */
-    PCIDevSetRevisionId(&pBus->aPciDev,   0xf2);
-    PCIDevSetClassSub(  &pBus->aPciDev,   0x04); /* pci2pci */
-    PCIDevSetClassBase( &pBus->aPciDev,   0x06); /* PCI_bridge */
-    PCIDevSetClassProg( &pBus->aPciDev,   0x01); /* Supports subtractive decoding. */
-    PCIDevSetHeaderType(&pBus->aPciDev,   0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
-    PCIDevSetCommand(   &pBus->aPciDev,   0x00);
-    PCIDevSetStatus(    &pBus->aPciDev,   0x20); /* 66MHz Capable. */
-    PCIDevSetInterruptLine(&pBus->aPciDev, 0x00); /* This device does not assert interrupts. */
+    PCIDevSetVendorId(  &pBus->PciDev, 0x8086); /* Intel */
+    PCIDevSetDeviceId(  &pBus->PciDev, 0x2448); /* 82801 Mobile PCI bridge. */
+    PCIDevSetRevisionId(&pBus->PciDev,   0xf2);
+    PCIDevSetClassSub(  &pBus->PciDev,   0x04); /* pci2pci */
+    PCIDevSetClassBase( &pBus->PciDev,   0x06); /* PCI_bridge */
+    PCIDevSetClassProg( &pBus->PciDev,   0x01); /* Supports subtractive decoding. */
+    PCIDevSetHeaderType(&pBus->PciDev,   0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
+    PCIDevSetCommand(   &pBus->PciDev,   0x00);
+    PCIDevSetStatus(    &pBus->PciDev,   0x20); /* 66MHz Capable. */
+    PCIDevSetInterruptLine(&pBus->PciDev, 0x00); /* This device does not assert interrupts. */
 
     /*
@@ -2759 +2728 @@
      * devices attached to the bus is unaffected.
      */
-    PCIDevSetInterruptPin (&pBus->aPciDev, 0x00);
+    PCIDevSetInterruptPin (&pBus->PciDev, 0x00);
 
     /*
      * Register this PCI bridge. The called function will take care on which bus we will get registered.
      */
-    rc = PDMDevHlpPCIRegisterEx(pDevIns, &pBus->aPciDev, PDMPCIDEVREG_CFG_PRIMARY, PDMPCIDEVREG_F_PCI_BRIDGE,
+    rc = PDMDevHlpPCIRegisterEx(pDevIns, &pBus->PciDev, PDMPCIDEVREG_CFG_PRIMARY, PDMPCIDEVREG_F_PCI_BRIDGE,
                                 PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, "ich9pcibridge");
     if (RT_FAILURE(rc))
         return rc;
-    pBus->aPciDev.Int.s.pfnBridgeConfigRead  = ich9pcibridgeConfigRead;
-    pBus->aPciDev.Int.s.pfnBridgeConfigWrite = ich9pcibridgeConfigWrite;
+    pBus->PciDev.Int.s.pfnBridgeConfigRead  = ich9pcibridgeConfigRead;
+    pBus->PciDev.Int.s.pfnBridgeConfigWrite = ich9pcibridgeConfigWrite;
 
     /*
@@ -2806 +2775 @@
 
     /* Reset config space to default values. */
-    PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_PRIMARY_BUS, 0);
-    PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS, 0);
-    PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SUBORDINATE_BUS, 0);
+    PCIDevSetByte(&pBus->PciDev, VBOX_PCI_PRIMARY_BUS, 0);
+    PCIDevSetByte(&pBus->PciDev, VBOX_PCI_SECONDARY_BUS, 0);
+    PCIDevSetByte(&pBus->PciDev, VBOX_PCI_SUBORDINATE_BUS, 0);
 
     /* PCI-specific reset for each device. */
@@ -2910 +2879 @@
     ~0U,
     /* cbInstance */
-    sizeof(ICH9PCIBUS),
+    sizeof(DEVPCIBUS),
     /* pfnConstruct */
     ich9pcibridgeConstruct,

trunk/src/VBox/Devices/Bus/DevPciMerge1.cpp.h

@@ -28 +28 @@
  * @remarks Caller enters the PDM critical section.
  */
-static uint8_t pciR3MergedFindUnusedDeviceNo(PPCIMERGEDBUS pBus)
+static uint8_t pciR3MergedFindUnusedDeviceNo(PDEVPCIBUS pBus)
 {
     for (uint8_t uPciDevNo = pBus->iDevSearch >> VBOX_PCI_DEVFN_DEV_SHIFT; uPciDevNo < VBOX_PCI_MAX_DEVICES; uPciDevNo++)
@@ -64 +64 @@
  * @remarks Caller enters the PDM critical section.
  */
-static int pciR3MergedRegisterDeviceOnBus(PPCIMERGEDBUS pBus, PPDMPCIDEV pPciDev, uint32_t fFlags,
+static int pciR3MergedRegisterDeviceOnBus(PDEVPCIBUS pBus, PPDMPCIDEV pPciDev, uint32_t fFlags,
                                           uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName,
                                           PFNPCICONFIGREAD pfnConfigRead, PFNPCICONFIGWRITE pfnConfigWrite)
@@ -221 +221 @@
                                              uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName)
 {
-    PPCIMERGEDBUS pBus = DEVINS_2_PCIBUS(pDevIns);
+    PDEVPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
     return pciR3MergedRegisterDeviceOnBus(pBus, pPciDev, fFlags, uPciDevNo, uPciFunNo, pszName,
                                           pciR3UnmergedConfigReadDev, pciR3UnmergedConfigWriteDev);
@@ -233 +233 @@
                                                          uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName)
 {
-    PPCIMERGEDBUS pBus = PDMINS_2_DATA(pDevIns, PPCIMERGEDBUS);
+    PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
     return pciR3MergedRegisterDeviceOnBus(pBus, pPciDev, fFlags, uPciDevNo, uPciFunNo, pszName,
                                           pciR3UnmergedConfigReadDev, pciR3UnmergedConfigWriteDev);

trunk/src/VBox/Devices/testcase/tstDeviceStructSize.cpp

@@ -361 +361 @@
 # endif
 #endif
-    CHECK_MEMBER_ALIGNMENT(PCIBUS, devices, 16);
-    CHECK_MEMBER_ALIGNMENT(PCIBUS, devices, 16);
+    CHECK_MEMBER_ALIGNMENT(DEVPCIBUS, apDevices, 64);
     CHECK_MEMBER_ALIGNMENT(PCIGLOBALS, pci_irq_levels, 16);
     CHECK_MEMBER_ALIGNMENT(PCNETSTATE, u64LastPoll, 8);

trunk/src/VBox/Devices/testcase/tstDeviceStructSizeRC.cpp

@@ -36 +36 @@
 #define VBOX_DEVICE_STRUCT_TESTCASE
 #define VBOX_WITH_HGCM                  /* grumble */
+#undef LOG_GROUP
+#include "../Bus/DevPciInternal.h"
 #undef LOG_GROUP
 #include "../Bus/DevPCI.cpp" /* must be first! */
@@ -147 +149 @@
     GEN_CHECK_OFF(PDMDEVINS, achInstanceData);
 
-    /* DevPCI.cpp */
+    /* PDMPCIDEV */
     GEN_CHECK_SIZE(PDMPCIDEV);
     GEN_CHECK_SIZE(PDMPCIDEVINT);
-    GEN_CHECK_SIZE(PCIIOREGION);
+    GEN_CHECK_SIZE(PCIIOREGION); /** @todo fix name of PCIIOREGION */
     GEN_CHECK_OFF(PDMPCIDEV, abConfig);
     GEN_CHECK_OFF(PDMPCIDEV, uDevFn);
@@ -173 +175 @@
     GEN_CHECK_OFF(PDMPCIDEV, Int.s.pfnBridgeConfigWrite);
     GEN_CHECK_PADDING(PDMPCIDEV, Int, 8);
+
+    /* DevPciInternal.h */
+    GEN_CHECK_SIZE(DEVPCIBUS);
+    GEN_CHECK_OFF(DEVPCIBUS, iBus);
+    GEN_CHECK_OFF(DEVPCIBUS, iDevSearch);
+    GEN_CHECK_OFF(DEVPCIBUS, cBridges);
+    GEN_CHECK_OFF(DEVPCIBUS, apDevices);
+    GEN_CHECK_OFF(DEVPCIBUS, apDevices[1]);
+    GEN_CHECK_OFF(DEVPCIBUS, pDevInsR3);
+    GEN_CHECK_OFF(DEVPCIBUS, pPciHlpR3);
+    GEN_CHECK_OFF(DEVPCIBUS, papBridgesR3);
+    GEN_CHECK_OFF(DEVPCIBUS, pDevInsR0);
+    GEN_CHECK_OFF(DEVPCIBUS, pPciHlpR0);
+    GEN_CHECK_OFF(DEVPCIBUS, pDevInsRC);
+    GEN_CHECK_OFF(DEVPCIBUS, pPciHlpRC);
+    GEN_CHECK_OFF(DEVPCIBUS, PciDev);
+
+    /* DevPCI.cpp */
     GEN_CHECK_SIZE(PIIX3State);
-    GEN_CHECK_SIZE(PCIBUS);
-    GEN_CHECK_OFF(PCIBUS, iBus);
-    GEN_CHECK_OFF(PCIBUS, iDevSearch);
-    GEN_CHECK_OFF(PCIBUS, cBridges);
-    GEN_CHECK_OFF(PCIBUS, devices);
-    GEN_CHECK_OFF(PCIBUS, devices[1]);
-    GEN_CHECK_OFF(PCIBUS, pDevInsR3);
-    GEN_CHECK_OFF(PCIBUS, pPciHlpR3);
-    GEN_CHECK_OFF(PCIBUS, papBridgesR3);
-    GEN_CHECK_OFF(PCIBUS, pDevInsR0);
-    GEN_CHECK_OFF(PCIBUS, pPciHlpR0);
-    GEN_CHECK_OFF(PCIBUS, pDevInsRC);
-    GEN_CHECK_OFF(PCIBUS, pPciHlpRC);
-    GEN_CHECK_OFF(PCIBUS, PciDev);
     GEN_CHECK_SIZE(PCIGLOBALS);
-    GEN_CHECK_OFF(PCIGLOBALS, pci_bios_io_addr);
-    GEN_CHECK_OFF(PCIGLOBALS, pci_bios_mem_addr);
+    GEN_CHECK_OFF(PCIGLOBALS, uPciBiosIo);
+    GEN_CHECK_OFF(PCIGLOBALS, uPciBiosMmio);
     GEN_CHECK_OFF(PCIGLOBALS, pci_irq_levels);
     GEN_CHECK_OFF(PCIGLOBALS, pci_irq_levels[1]);
     GEN_CHECK_OFF(PCIGLOBALS, fUseIoApic);
-    GEN_CHECK_OFF(PCIGLOBALS, pci_apic_irq_levels);
-    GEN_CHECK_OFF(PCIGLOBALS, pci_apic_irq_levels[1]);
+    GEN_CHECK_OFF(PCIGLOBALS, uaPciApicIrqLevels);
+    GEN_CHECK_OFF(PCIGLOBALS, uaPciApicIrqLevels[1]);
     GEN_CHECK_OFF(PCIGLOBALS, acpi_irq_level);
     GEN_CHECK_OFF(PCIGLOBALS, acpi_irq);
@@ -206 +212 @@
 
     /* DevPciIch9.cpp */
-    GEN_CHECK_SIZE(ICH9PCIBUS);
-    GEN_CHECK_OFF(ICH9PCIBUS, iBus);
-    GEN_CHECK_OFF(ICH9PCIBUS, cBridges);
-    GEN_CHECK_OFF(ICH9PCIBUS, apDevices);
-    GEN_CHECK_OFF(ICH9PCIBUS, apDevices[1]);
-    GEN_CHECK_OFF(ICH9PCIBUS, pDevInsR3);
-    GEN_CHECK_OFF(ICH9PCIBUS, pPciHlpR3);
-    GEN_CHECK_OFF(ICH9PCIBUS, papBridgesR3);
-    GEN_CHECK_OFF(ICH9PCIBUS, pDevInsR0);
-    GEN_CHECK_OFF(ICH9PCIBUS, pPciHlpR0);
-    GEN_CHECK_OFF(ICH9PCIBUS, pDevInsRC);
-    GEN_CHECK_OFF(ICH9PCIBUS, pPciHlpRC);
-    GEN_CHECK_OFF(ICH9PCIBUS, aPciDev);
     GEN_CHECK_SIZE(ICH9PCIGLOBALS);
     GEN_CHECK_OFF(ICH9PCIGLOBALS, pDevInsR3);
@@ -232 +225 @@
     GEN_CHECK_OFF(ICH9PCIGLOBALS, u64PciConfigMMioAddress);
     GEN_CHECK_OFF(ICH9PCIGLOBALS, u64PciConfigMMioLength);
-    GEN_CHECK_OFF(ICH9PCIGLOBALS, aPciBus);
+    GEN_CHECK_OFF(ICH9PCIGLOBALS, PciBus);
 
     /* EFI/DevSMC.cpp */