Changeset 64415 in vbox for trunk

Timestamp:

Oct 25, 2016 3:01:40 PM (8 years ago)

Author:

vboxsync

Message:

DevPci: Working on merging ICH9PCIGLOBALS and PCIGLOBALS.

Location:

trunk/src/VBox/Devices

Files:

• Bus/DevPCI.cpp (modified) (5 diffs)
• Bus/DevPciIch9.cpp (modified) (8 diffs)
• Bus/DevPciInternal.h (modified) (1 diff)
• testcase/tstDeviceStructSizeRC.cpp (modified) (1 diff)

trunk/src/VBox/Devices/Bus/DevPCI.cpp

@@ -99 +99 @@
 typedef struct PCIGLOBALS
 {
+    /** PCI bus which is attached to the host-to-PCI bridge.
+     * This must come first!  */
+    DEVPCIBUS           PciBus;
+
+    /** R3 pointer to the device instance. */
+    PPDMDEVINSR3        pDevInsR3;
+    /** R0 pointer to the device instance. */
+    PPDMDEVINSR0        pDevInsR0;
+    /** RC pointer to the device instance. */
+    PPDMDEVINSRC        pDevInsRC;
+
+    /** I/O APIC usage flag */
+    bool                fUseIoApic;
+    /** Reserved for future config flags. */
+    bool                afFutureFlags[3];
+
+    /** Value latched in Configuration Address Port (0CF8h) */
+    uint32_t            uConfigReg;
+    /** ACPI IRQ level */
+    uint32_t            acpi_irq_level;
+    /** ACPI PIC IRQ */
+    int                 acpi_irq;
+    uint32_t            u32Alignment;
+
+    /** I/O APIC irq levels */
+    volatile uint32_t   uaPciApicIrqLevels[PCI_APIC_IRQ_PINS];
+
     /** Irq levels for the four PCI Irqs.
-     * These count how many devices asserted the IRQ line. If greater 0 an IRQ is
-     * sent to the guest.  If it drops to 0 the IRQ is deasserted.
+     * These count how many devices asserted the IRQ line.  If greater 0 an IRQ
+     * is sent to the guest.  If it drops to 0 the IRQ is deasserted.
      */
     volatile uint32_t   pci_irq_levels[PCI_IRQ_PINS];
+
+    /** ISA bridge state. */
+    PIIX3               PIIX3State;
 
 #if 1 /* Will be moved into the BIOS "soon". */
@@ -112 +142 @@
     /** Actual bus number. */
     uint8_t             uBus;
-    uint8_t             uAlignment0[2];
+    uint8_t             uAlignment0[7];
 #endif
-
-    /** I/O APIC usage flag */
-    bool                fUseIoApic;
-    /** I/O APIC irq levels */
-    volatile uint32_t   uaPciApicIrqLevels[PCI_APIC_IRQ_PINS];
-    /** ACPI IRQ level */
-    uint32_t            acpi_irq_level;
-    /** ACPI PIC IRQ */
-    int                 acpi_irq;
-    /** Value latched in Configuration Address Port (0CF8h) */
-    uint32_t            uConfigReg;
-
-    /** R3 pointer to the device instance. */
-    PPDMDEVINSR3        pDevInsR3;
-    /** R0 pointer to the device instance. */
-    PPDMDEVINSR0        pDevInsR0;
-    /** RC pointer to the device instance. */
-    PPDMDEVINSRC        pDevInsRC;
-
-#if HC_ARCH_BITS == 64
-    uint32_t            Alignment0;
-#endif
-
-    /** ISA bridge state. */
-    PIIX3               PIIX3State;
-    /** PCI bus which is attached to the host-to-PCI bridge. */
-    DEVPCIBUS           PciBus;
 
 } PCIGLOBALS;
 /** Pointer to per VM data. */
 typedef PCIGLOBALS *PPCIGLOBALS;
+
 
 
@@ -2002 +2006 @@
      */
     PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
-    pGlobals->uPciBiosIo    = 0xc000;
-    pGlobals->uPciBiosMmio   = 0xf0000000;
+    pGlobals->uPciBiosIo   = 0xc000;
+    pGlobals->uPciBiosMmio = 0xf0000000;
     memset((void *)&pGlobals->pci_irq_levels, 0, sizeof(pGlobals->pci_irq_levels));
-    pGlobals->fUseIoApic          = fUseIoApic;
+    pGlobals->fUseIoApic   = fUseIoApic;
     memset((void *)&pGlobals->uaPciApicIrqLevels, 0, sizeof(pGlobals->uaPciApicIrqLevels));
 
@@ -2012 +2016 @@
     pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
 
+    pGlobals->PciBus.fTypePiix3  = true;
+    pGlobals->PciBus.fTypeIch9   = false;
+    pGlobals->PciBus.fPureBridge = false;
     pGlobals->PciBus.pDevInsR3 = pDevIns;
     pGlobals->PciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
     pGlobals->PciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
-    pGlobals->PciBus.papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns,   sizeof(PPDMPCIDEV)
-                                                                                 * RT_ELEMENTS(pGlobals->PciBus.apDevices));
+    pGlobals->PciBus.papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns,
+                                                                        sizeof(PPDMPCIDEV)
+                                                                        * RT_ELEMENTS(pGlobals->PciBus.apDevices));
+    AssertLogRelReturn(pGlobals->PciBus.papBridgesR3, VERR_NO_MEMORY);
+
 
     PDMPCIBUSREG PciBusReg;
@@ -2364 +2374 @@
      */
     PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
+    pBus->fTypePiix3  = true;
+    pBus->fTypeIch9   = false;
+    pBus->fPureBridge = true;
     pBus->pDevInsR3 = pDevIns;
     pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
     pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
     pBus->papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) * RT_ELEMENTS(pBus->apDevices));
+    AssertLogRelReturn(pBus->papBridgesR3, VERR_NO_MEMORY);
 
     PDMPCIBUSREG PciBusReg;

trunk/src/VBox/Devices/Bus/DevPciIch9.cpp

@@ -66 +66 @@
 typedef struct
 {
+    /** PCI bus which is attached to the host-to-PCI bridge.
+     * This must come first so we can share more code with the bridges!  */
+    DEVPCIBUS           PciBus;
+
     /** R3 pointer to the device instance. */
     PPDMDEVINSR3        pDevInsR3;
@@ -73 +77 @@
     PPDMDEVINSRC        pDevInsRC;
 
+    /** I/O APIC usage flag (always true of ICH9, see constructor). */
+    bool                fUseIoApic;
+    /** Reserved for future config flags. */
+    bool                afFutureFlags[3];
+    /** Physical address of PCI config space MMIO region. */
+    uint64_t            u64PciConfigMMioAddress;
+    /** Length of PCI config space MMIO region. */
+    uint64_t            u64PciConfigMMioLength;
+
+    /** I/O APIC irq levels */
+    volatile uint32_t   uaPciApicIrqLevels[PCI_APIC_IRQ_PINS];
     /** Value latched in Configuration Address Port (0CF8h) */
     uint32_t            uConfigReg;
 
-    /** I/O APIC irq levels */
-    volatile uint32_t   uaPciApicIrqLevels[PCI_APIC_IRQ_PINS];
-
 #if 1 /* Will be moved into the BIOS "soon". */
+    /** Current bus number (?). */
+    uint8_t             uPciBiosBus;
+    uint8_t             Alignment0[3];
     /** The next I/O port address which the PCI BIOS will use. */
     uint32_t            uPciBiosIo;
@@ -86 +101 @@
     /** The next 64-bit MMIO address which the PCI BIOS will use. */
     uint64_t            uPciBiosMmio64;
-    /** Actual bus number. */
-    uint8_t             uBus;
-    uint8_t             Alignment0[7];
 #endif
-    /** Physical address of PCI config space MMIO region. */
-    uint64_t            u64PciConfigMMioAddress;
-    /** Length of PCI config space MMIO region. */
-    uint64_t            u64PciConfigMMioLength;
-
-    /** PCI bus which is attached to the host-to-PCI bridge. */
-    DEVPCIBUS           PciBus;
+
 } ICH9PCIGLOBALS, *PICH9PCIGLOBALS;
 
@@ -1688 +1694 @@
         case 0x0604:
             /* PCI-to-PCI bridge. */
-            AssertMsg(pGlobals->uBus < 255, ("Too many bridges on the bus\n"));
+            AssertMsg(pGlobals->uPciBiosBus < 255, ("Too many bridges on the bus\n"));
             ich9pciBiosInitBridge(pGlobals, uBus, uDevFn);
             break;
@@ -1886 +1892 @@
                   ("Device is not a PCI bridge but on the list of PCI bridges\n"));
         PICH9PCIBUS pChildBus = PDMINS_2_DATA(pBridge->Int.s.CTX_SUFF(pDevIns), PICH9PCIBUS);
-        pGlobals->uBus++;
-        ich9pciInitBridgeTopology(pGlobals, pChildBus, uBusSecondary, pGlobals->uBus);
-    }
-    PCIDevSetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus);
+        pGlobals->uPciBiosBus++;
+        ich9pciInitBridgeTopology(pGlobals, pChildBus, uBusSecondary, pGlobals->uPciBiosBus);
+    }
+    PCIDevSetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uPciBiosBus);
     Log2(("ich9pciInitBridgeTopology: for bus %p: primary=%d secondary=%d subordinate=%d\n",
           pBus,
@@ -1909 +1915 @@
      * Set the start addresses.
      */
+    pGlobals->uPciBiosBus    = 0;
     pGlobals->uPciBiosIo     = 0xd000;
     pGlobals->uPciBiosMmio   = cbBelow4GB;
     pGlobals->uPciBiosMmio64 = cbAbove4GB + _4G;
-    pGlobals->uBus = 0;
 
     /* NB: Assume that if MMIO range is enabled, it is at the bottom of the memory hole. */
@@ -2416 +2422 @@
                                 N_("Configuration error: Failed to read \"McfgLength\""));
 
+    pGlobals->fUseIoApic = fUseIoApic;
     pGlobals->pDevInsR3 = pDevIns;
     pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
     pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
 
+    pGlobals->PciBus.fTypePiix3  = false;
+    pGlobals->PciBus.fTypeIch9   = true;
+    pGlobals->PciBus.fPureBridge = false;
     pGlobals->PciBus.pDevInsR3 = pDevIns;
     pGlobals->PciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
     pGlobals->PciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
     pGlobals->PciBus.papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) * RT_ELEMENTS(pGlobals->PciBus.apDevices));
+    AssertLogRelReturn(pGlobals->PciBus.papBridgesR3, VERR_NO_MEMORY);
 
     /*
@@ -2679 +2690 @@
      */
     PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
+    pBus->fTypePiix3  = false;
+    pBus->fTypeIch9   = true;
+    pBus->fPureBridge = true;
     pBus->pDevInsR3 = pDevIns;
     pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
     pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
     pBus->papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) * RT_ELEMENTS(pBus->apDevices));
+    AssertLogRelReturn(pBus->papBridgesR3, VERR_NO_MEMORY);
 
     PDMPCIBUSREG PciBusReg;

trunk/src/VBox/Devices/Bus/DevPciInternal.h

@@ -36 +36 @@
     /** Start device number - always zero (only for DevPCI source compat). */
     uint32_t                iDevSearch;
-    /** Size alignemnt padding. */
-    uint32_t                u32Alignment0;
+    /** Set if PIIX3 type. */
+    uint32_t                fTypePiix3 : 1;
+    /** Set if ICH9 type. */
+    uint32_t                fTypeIch9: 1;
+    /** Set if this is a pure bridge, i.e. not part of DEVPCIGLOBALS struct. */
+    uint32_t                fPureBridge : 1;
+    uint32_t                uUnused : 29;
 
     /** R3 pointer to the device instance. */

trunk/src/VBox/Devices/testcase/tstDeviceStructSizeRC.cpp

@@ -219 +219 @@
     GEN_CHECK_OFF(ICH9PCIGLOBALS, uaPciApicIrqLevels);
     GEN_CHECK_OFF(ICH9PCIGLOBALS, uaPciApicIrqLevels[1]);
+    GEN_CHECK_OFF(ICH9PCIGLOBALS, uPciBiosBus);
     GEN_CHECK_OFF(ICH9PCIGLOBALS, uPciBiosIo);
     GEN_CHECK_OFF(ICH9PCIGLOBALS, uPciBiosMmio);
     GEN_CHECK_OFF(ICH9PCIGLOBALS, uPciBiosMmio64);
-    GEN_CHECK_OFF(ICH9PCIGLOBALS, uBus);
     GEN_CHECK_OFF(ICH9PCIGLOBALS, u64PciConfigMMioAddress);
     GEN_CHECK_OFF(ICH9PCIGLOBALS, u64PciConfigMMioLength);