VirtualBox

Changeset 64419 in vbox


Ignore:
Timestamp:
Oct 25, 2016 3:35:56 PM (9 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
111536
Message:

DevPci: Mmerged ICH9PCIGLOBALS and PCIGLOBALS.

Location:
trunk/src/VBox/Devices
Files:
5 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/Devices/Bus/DevPCI.cpp

    r64418 r64419  
    7171*   Structures and Typedefs                                                                                                      *
    7272*********************************************************************************************************************************/
    73 typedef DEVPCIBUS  PCIBUS;
    74 typedef PDEVPCIBUS PPCIBUS;
    75 
    76 
    77 /**
    78  * PIIX3 ISA Bridge state.
    79  */
    80 typedef struct PIIX3State
    81 {
    82     /** The PCI device of the bridge. */
    83     PDMPCIDEV dev;
    84 } PIIX3State, PIIX3, *PPIIX3;
    85 
    86 
    87 /**
    88  * PCI Globals - This is the host-to-pci bridge and the root bus.
    89  */
    90 typedef struct PCIGLOBALS
    91 {
    92     /** PCI bus which is attached to the host-to-PCI bridge.
    93      * This must come first!  */
    94     DEVPCIBUS           PciBus;
    95 
    96     /** R3 pointer to the device instance. */
    97     PPDMDEVINSR3        pDevInsR3;
    98     /** R0 pointer to the device instance. */
    99     PPDMDEVINSR0        pDevInsR0;
    100     /** RC pointer to the device instance. */
    101     PPDMDEVINSRC        pDevInsRC;
    102 
    103     /** I/O APIC usage flag */
    104     bool                fUseIoApic;
    105     /** Reserved for future config flags. */
    106     bool                afFutureFlags[3];
    107 
    108     /** Value latched in Configuration Address Port (0CF8h) */
    109     uint32_t            uConfigReg;
    110     uint32_t            u32Alignment;
    111 
    112     /** I/O APIC irq levels */
    113     volatile uint32_t   auPciApicIrqLevels[DEVPCI_APIC_IRQ_PINS];
    114     /** Members only used by the PIIX3 code variant. */
    115     struct
    116     {
    117         /** Irq levels for the four PCI Irqs.
    118          * These count how many devices asserted the IRQ line.  If greater 0 an IRQ
    119          * is sent to the guest.  If it drops to 0 the IRQ is deasserted.
    120          * @remarks Labling this "legacy" might be a bit off...
    121          */
    122         volatile uint32_t   auPciLegacyIrqLevels[DEVPCI_LEGACY_IRQ_PINS];
    123 
    124         /** ACPI IRQ level */
    125         uint32_t            iAcpiIrqLevel;
    126         /** ACPI PIC IRQ */
    127         int32_t             iAcpiIrq;
    128 
    129         /** ISA bridge state. */
    130         PIIX3               PIIX3State;
    131     } Piix3;
    132 
    133 #if 1 /* Will be moved into the BIOS "soon". */
    134     /** The next I/O port address which the PCI BIOS will use. */
    135     uint32_t            uPciBiosIo;
    136     /** The next MMIO address which the PCI BIOS will use. */
    137     uint32_t            uPciBiosMmio;
    138     /** Actual bus number. */
    139     uint8_t             uBus;
    140     uint8_t             uAlignment0[7];
    141 #endif
    142 
    143 } PCIGLOBALS;
    144 /** Pointer to per VM data. */
    145 typedef PCIGLOBALS *PPCIGLOBALS;
    146 
     73typedef DEVPCIBUS       PCIBUS;
     74typedef PDEVPCIBUS      PPCIBUS;
     75typedef DEVPCIROOT      PCIGLOBALS;
     76typedef PDEVPCIROOT     PPCIGLOBALS;
    14777
    14878
    … …  
    765695}
    766696
    767 static void pciR3Piix3Reset(PIIX3State *d)
     697static void pciR3Piix3Reset(PIIX3ISABRIDGE *d)
    768698{
    769699    uint8_t *pci_conf = d->dev.abConfig;
    … …  
    952882                pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_PRIMARY_BUS, uBus);
    953883
    954                 AssertMsg(pGlobals->uBus < 255, ("Too many bridges on the bus\n"));
    955                 pGlobals->uBus++;
    956                 pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, pGlobals->uBus);
     884                AssertMsg(pGlobals->uPciBiosBus < 255, ("Too many bridges on the bus\n"));
     885                pGlobals->uPciBiosBus++;
     886                pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, pGlobals->uPciBiosBus);
    957887                pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, 0xff); /* Temporary until we know how many other bridges are behind this one. */
    958888
    … …  
    985915
    986916                /* The number of bridges behind the this one is now available. */
    987                 pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus);
     917                pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uPciBiosBus);
    988918
    989919                /*
    … …  
    17021632     * Set the start addresses.
    17031633     */
    1704     pGlobals->uPciBiosIo  = 0xd000;
     1634    pGlobals->uPciBiosBus  = 0;
     1635    pGlobals->uPciBiosIo   = 0xd000;
    17051636    pGlobals->uPciBiosMmio = UINT32_C(0xf0000000);
    1706     pGlobals->uBus = 0;
    17071637
    17081638    /*

  • trunk/src/VBox/Devices/Bus/DevPciIch9.cpp

    r64418 r64419  
    5252*   Structures and Typedefs                                                                                                      *
    5353*********************************************************************************************************************************/
    54 typedef DEVPCIBUS  ICH9PCIBUS;
    55 typedef PDEVPCIBUS PICH9PCIBUS;
    56 
    57 
    58 /**
    59  * PCI Globals - This is the host-to-pci bridge and the root bus.
    60  */
    61 typedef struct
    62 {
    63     /** PCI bus which is attached to the host-to-PCI bridge.
    64      * This must come first so we can share more code with the bridges!  */
    65     DEVPCIBUS           PciBus;
    66 
    67     /** R3 pointer to the device instance. */
    68     PPDMDEVINSR3        pDevInsR3;
    69     /** R0 pointer to the device instance. */
    70     PPDMDEVINSR0        pDevInsR0;
    71     /** RC pointer to the device instance. */
    72     PPDMDEVINSRC        pDevInsRC;
    73 
    74     /** I/O APIC usage flag (always true of ICH9, see constructor). */
    75     bool                fUseIoApic;
    76     /** Reserved for future config flags. */
    77     bool                afFutureFlags[3];
    78     /** Physical address of PCI config space MMIO region. */
    79     uint64_t            u64PciConfigMMioAddress;
    80     /** Length of PCI config space MMIO region. */
    81     uint64_t            u64PciConfigMMioLength;
    82 
    83     /** I/O APIC irq levels */
    84     volatile uint32_t   auPciApicIrqLevels[DEVPCI_APIC_IRQ_PINS];
    85     /** Value latched in Configuration Address Port (0CF8h) */
    86     uint32_t            uConfigReg;
    87 
    88 #if 1 /* Will be moved into the BIOS "soon". */
    89     /** Current bus number (?). */
    90     uint8_t             uPciBiosBus;
    91     uint8_t             Alignment0[3];
    92     /** The next I/O port address which the PCI BIOS will use. */
    93     uint32_t            uPciBiosIo;
    94     /** The next MMIO address which the PCI BIOS will use. */
    95     uint32_t            uPciBiosMmio;
    96     /** The next 64-bit MMIO address which the PCI BIOS will use. */
    97     uint64_t            uPciBiosMmio64;
    98 #endif
    99 
    100 } ICH9PCIGLOBALS, *PICH9PCIGLOBALS;
     54typedef DEVPCIBUS     ICH9PCIBUS;
     55typedef PDEVPCIBUS    PICH9PCIBUS;
     56typedef DEVPCIROOT    ICH9PCIGLOBALS;
     57typedef PDEVPCIROOT   PICH9PCIGLOBALS;
     58
     59
    10160
    10261

  • trunk/src/VBox/Devices/Bus/DevPciInternal.h

    r64417 r64419  
    8585#define DEVPCI_LEGACY_IRQ_PINS  4
    8686
     87/**
     88 * PIIX3 ISA bridge state.
     89 */
     90typedef struct PIIX3ISABRIDGE
     91{
     92    /** The PCI device of the bridge. */
     93    PDMPCIDEV dev;
     94} PIIX3ISABRIDGE;
     95
     96
     97/**
     98 * PCI Globals - This is the host-to-pci bridge and the root bus.
     99 *
     100 * @note Only used by the root bus, not the bridges.
     101 */
     102typedef struct DEVPCIROOT
     103{
     104    /** PCI bus which is attached to the host-to-PCI bridge.
     105     * @note This must come first so we can share more code with the bridges!  */
     106    DEVPCIBUS           PciBus;
     107
     108    /** R3 pointer to the device instance. */
     109    PPDMDEVINSR3        pDevInsR3;
     110    /** R0 pointer to the device instance. */
     111    PPDMDEVINSR0        pDevInsR0;
     112    /** RC pointer to the device instance. */
     113    PPDMDEVINSRC        pDevInsRC;
     114
     115    /** I/O APIC usage flag (always true of ICH9, see constructor). */
     116    bool                fUseIoApic;
     117    /** Reserved for future config flags. */
     118    bool                afFutureFlags[3];
     119    /** Physical address of PCI config space MMIO region. */
     120    uint64_t            u64PciConfigMMioAddress;
     121    /** Length of PCI config space MMIO region. */
     122    uint64_t            u64PciConfigMMioLength;
     123
     124    /** I/O APIC irq levels */
     125    volatile uint32_t   auPciApicIrqLevels[DEVPCI_APIC_IRQ_PINS];
     126    /** Value latched in Configuration Address Port (0CF8h) */
     127    uint32_t            uConfigReg;
     128    /** Alignment padding.   */
     129    uint32_t            u32Alignment1;
     130    /** Members only used by the PIIX3 code variant. */
     131    struct
     132    {
     133        /** ACPI IRQ level */
     134        uint32_t            iAcpiIrqLevel;
     135        /** ACPI PIC IRQ */
     136        int32_t             iAcpiIrq;
     137        /** Irq levels for the four PCI Irqs.
     138         * These count how many devices asserted the IRQ line.  If greater 0 an IRQ
     139         * is sent to the guest.  If it drops to 0 the IRQ is deasserted.
     140         * @remarks Labling this "legacy" might be a bit off...
     141         */
     142        volatile uint32_t   auPciLegacyIrqLevels[DEVPCI_LEGACY_IRQ_PINS];
     143        /** ISA bridge state. */
     144        PIIX3ISABRIDGE      PIIX3State;
     145    } Piix3;
     146
     147#if 1 /* Will be moved into the BIOS "soon". */
     148    /** Current bus number (?). */
     149    uint8_t             uPciBiosBus;
     150    uint8_t             abAlignment2[7];
     151    /** The next I/O port address which the PCI BIOS will use. */
     152    uint32_t            uPciBiosIo;
     153    /** The next MMIO address which the PCI BIOS will use. */
     154    uint32_t            uPciBiosMmio;
     155    /** The next 64-bit MMIO address which the PCI BIOS will use. */
     156    uint64_t            uPciBiosMmio64;
     157#endif
     158
     159} DEVPCIROOT;
     160/** Pointer to PCI device globals. */
     161typedef DEVPCIROOT *PDEVPCIROOT;
     162
    87163
    88164#endif

  • trunk/src/VBox/Devices/testcase/tstDeviceStructSize.cpp

    r64418 r64419  
    2929#define VBOX_DEVICE_STRUCT_TESTCASE
    3030#undef LOG_GROUP
    31 #include "../Bus/DevPCI.cpp"
    32 #undef LOG_GROUP
    33 #include "../Bus/DevPciIch9.cpp"
     31#include "../Bus/DevPciInternal.h"
    3432#undef LOG_GROUP
    3533#include "../Graphics/DevVGA.cpp"
    … …  
    362360#endif
    363361    CHECK_MEMBER_ALIGNMENT(DEVPCIBUS, apDevices, 64);
    364 //    CHECK_MEMBER_ALIGNMENT(PCIGLOBALS, Piix3.auPciLegacyIrqLevels, 16); - reenable later
     362    CHECK_MEMBER_ALIGNMENT(DEVPCIROOT, auPciApicIrqLevels, 16);
     363    CHECK_MEMBER_ALIGNMENT(DEVPCIROOT, Piix3.auPciLegacyIrqLevels, 16);
    365364    CHECK_MEMBER_ALIGNMENT(PCNETSTATE, u64LastPoll, 8);
    366365    CHECK_MEMBER_ALIGNMENT(PCNETSTATE, CritSect, 8);

  • trunk/src/VBox/Devices/testcase/tstDeviceStructSizeRC.cpp

    r64418 r64419  
    3838#undef LOG_GROUP
    3939#include "../Bus/DevPciInternal.h"
    40 #undef LOG_GROUP
    41 #include "../Bus/DevPCI.cpp" /* must be first! */
    42 #undef LOG_GROUP
    43 #include "../Bus/DevPciIch9.cpp"
    4440#undef LOG_GROUP
    4541#include "../EFI/DevSmc.cpp"
    … …  
    191187    GEN_CHECK_OFF(DEVPCIBUS, pPciHlpRC);
    192188    GEN_CHECK_OFF(DEVPCIBUS, PciDev);
    193 
    194     /* DevPCI.cpp */
    195     GEN_CHECK_SIZE(PIIX3State);
    196     GEN_CHECK_SIZE(PCIGLOBALS);
    197     GEN_CHECK_OFF(PCIGLOBALS, uPciBiosIo);
    198     GEN_CHECK_OFF(PCIGLOBALS, uPciBiosMmio);
    199     GEN_CHECK_OFF(PCIGLOBALS, fUseIoApic);
    200     GEN_CHECK_OFF(PCIGLOBALS, pDevInsR3);
    201     GEN_CHECK_OFF(PCIGLOBALS, pDevInsR0);
    202     GEN_CHECK_OFF(PCIGLOBALS, pDevInsRC);
    203     GEN_CHECK_OFF(PCIGLOBALS, uConfigReg);
    204     GEN_CHECK_OFF(PCIGLOBALS, auPciApicIrqLevels);
    205     GEN_CHECK_OFF(PCIGLOBALS, auPciApicIrqLevels[1]);
    206     GEN_CHECK_OFF(PCIGLOBALS, Piix3.auPciLegacyIrqLevels);
    207     GEN_CHECK_OFF(PCIGLOBALS, Piix3.auPciLegacyIrqLevels[1]);
    208     GEN_CHECK_OFF(PCIGLOBALS, Piix3.iAcpiIrqLevel);
    209     GEN_CHECK_OFF(PCIGLOBALS, Piix3.iAcpiIrq);
    210     GEN_CHECK_OFF(PCIGLOBALS, Piix3.PIIX3State);
    211     GEN_CHECK_OFF(PCIGLOBALS, PciBus);
    212 
    213     /* DevPciIch9.cpp */
    214     GEN_CHECK_SIZE(ICH9PCIGLOBALS);
    215     GEN_CHECK_OFF(ICH9PCIGLOBALS, pDevInsR3);
    216     GEN_CHECK_OFF(ICH9PCIGLOBALS, pDevInsR0);
    217     GEN_CHECK_OFF(ICH9PCIGLOBALS, pDevInsRC);
    218     GEN_CHECK_OFF(ICH9PCIGLOBALS, uConfigReg);
    219     GEN_CHECK_OFF(ICH9PCIGLOBALS, auPciApicIrqLevels);
    220     GEN_CHECK_OFF(ICH9PCIGLOBALS, auPciApicIrqLevels[1]);
    221     GEN_CHECK_OFF(ICH9PCIGLOBALS, uPciBiosBus);
    222     GEN_CHECK_OFF(ICH9PCIGLOBALS, uPciBiosIo);
    223     GEN_CHECK_OFF(ICH9PCIGLOBALS, uPciBiosMmio);
    224     GEN_CHECK_OFF(ICH9PCIGLOBALS, uPciBiosMmio64);
    225     GEN_CHECK_OFF(ICH9PCIGLOBALS, u64PciConfigMMioAddress);
    226     GEN_CHECK_OFF(ICH9PCIGLOBALS, u64PciConfigMMioLength);
    227     GEN_CHECK_OFF(ICH9PCIGLOBALS, PciBus);
     189    GEN_CHECK_SIZE(PIIX3ISABRIDGE);
     190    GEN_CHECK_SIZE(DEVPCIROOT);
     191    GEN_CHECK_OFF(DEVPCIROOT, PciBus);
     192    GEN_CHECK_OFF(DEVPCIROOT, pDevInsR3);
     193    GEN_CHECK_OFF(DEVPCIROOT, pDevInsR0);
     194    GEN_CHECK_OFF(DEVPCIROOT, pDevInsRC);
     195    GEN_CHECK_OFF(DEVPCIROOT, fUseIoApic);
     196    GEN_CHECK_OFF(DEVPCIROOT, u64PciConfigMMioAddress);
     197    GEN_CHECK_OFF(DEVPCIROOT, u64PciConfigMMioLength);
     198    GEN_CHECK_OFF(DEVPCIROOT, auPciApicIrqLevels);
     199    GEN_CHECK_OFF(DEVPCIROOT, auPciApicIrqLevels[1]);
     200    GEN_CHECK_OFF(DEVPCIROOT, uConfigReg);
     201    GEN_CHECK_OFF(DEVPCIROOT, Piix3.iAcpiIrqLevel);
     202    GEN_CHECK_OFF(DEVPCIROOT, Piix3.iAcpiIrq);
     203    GEN_CHECK_OFF(DEVPCIROOT, Piix3.auPciLegacyIrqLevels);
     204    GEN_CHECK_OFF(DEVPCIROOT, Piix3.auPciLegacyIrqLevels[1]);
     205    GEN_CHECK_OFF(DEVPCIROOT, Piix3.PIIX3State);
     206    GEN_CHECK_OFF(DEVPCIROOT, uPciBiosBus);
     207    GEN_CHECK_OFF(DEVPCIROOT, uPciBiosIo);
     208    GEN_CHECK_OFF(DEVPCIROOT, uPciBiosMmio);
     209    GEN_CHECK_OFF(DEVPCIROOT, uPciBiosMmio64);
    228210
    229211    /* EFI/DevSMC.cpp */
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