Index: trunk/src/VBox/Devices/Bus/DevPCI.cpp
===================================================================
--- trunk/src/VBox/Devices/Bus/DevPCI.cpp	(revision 64418)
+++ trunk/src/VBox/Devices/Bus/DevPCI.cpp	(revision 64419)
@@ -71,78 +71,8 @@
 *   Structures and Typedefs                                                                                                      *
 *********************************************************************************************************************************/
-typedef DEVPCIBUS  PCIBUS;
-typedef PDEVPCIBUS PPCIBUS;
-
-
-/**
- * PIIX3 ISA Bridge state.
- */
-typedef struct PIIX3State
-{
-    /** The PCI device of the bridge. */
-    PDMPCIDEV dev;
-} PIIX3State, PIIX3, *PPIIX3;
-
-
-/**
- * PCI Globals - This is the host-to-pci bridge and the root bus.
- */
-typedef struct PCIGLOBALS
-{
-    /** PCI bus which is attached to the host-to-PCI bridge.
-     * This must come first!  */
-    DEVPCIBUS           PciBus;
-
-    /** R3 pointer to the device instance. */
-    PPDMDEVINSR3        pDevInsR3;
-    /** R0 pointer to the device instance. */
-    PPDMDEVINSR0        pDevInsR0;
-    /** RC pointer to the device instance. */
-    PPDMDEVINSRC        pDevInsRC;
-
-    /** I/O APIC usage flag */
-    bool                fUseIoApic;
-    /** Reserved for future config flags. */
-    bool                afFutureFlags[3];
-
-    /** Value latched in Configuration Address Port (0CF8h) */
-    uint32_t            uConfigReg;
-    uint32_t            u32Alignment;
-
-    /** I/O APIC irq levels */
-    volatile uint32_t   auPciApicIrqLevels[DEVPCI_APIC_IRQ_PINS];
-    /** Members only used by the PIIX3 code variant. */
-    struct
-    {
-        /** Irq levels for the four PCI Irqs.
-         * These count how many devices asserted the IRQ line.  If greater 0 an IRQ
-         * is sent to the guest.  If it drops to 0 the IRQ is deasserted.
-         * @remarks Labling this "legacy" might be a bit off...
-         */
-        volatile uint32_t   auPciLegacyIrqLevels[DEVPCI_LEGACY_IRQ_PINS];
-
-        /** ACPI IRQ level */
-        uint32_t            iAcpiIrqLevel;
-        /** ACPI PIC IRQ */
-        int32_t             iAcpiIrq;
-
-        /** ISA bridge state. */
-        PIIX3               PIIX3State;
-    } Piix3;
-
-#if 1 /* Will be moved into the BIOS "soon". */
-    /** The next I/O port address which the PCI BIOS will use. */
-    uint32_t            uPciBiosIo;
-    /** The next MMIO address which the PCI BIOS will use. */
-    uint32_t            uPciBiosMmio;
-    /** Actual bus number. */
-    uint8_t             uBus;
-    uint8_t             uAlignment0[7];
-#endif
-
-} PCIGLOBALS;
-/** Pointer to per VM data. */
-typedef PCIGLOBALS *PPCIGLOBALS;
-
+typedef DEVPCIBUS       PCIBUS;
+typedef PDEVPCIBUS      PPCIBUS;
+typedef DEVPCIROOT      PCIGLOBALS;
+typedef PDEVPCIROOT     PPCIGLOBALS;
 
 
@@ -765,5 +695,5 @@
 }
 
-static void pciR3Piix3Reset(PIIX3State *d)
+static void pciR3Piix3Reset(PIIX3ISABRIDGE *d)
 {
     uint8_t *pci_conf = d->dev.abConfig;
@@ -952,7 +882,7 @@
                 pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_PRIMARY_BUS, uBus);
 
-                AssertMsg(pGlobals->uBus < 255, ("Too many bridges on the bus\n"));
-                pGlobals->uBus++;
-                pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, pGlobals->uBus);
+                AssertMsg(pGlobals->uPciBiosBus < 255, ("Too many bridges on the bus\n"));
+                pGlobals->uPciBiosBus++;
+                pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, pGlobals->uPciBiosBus);
                 pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, 0xff); /* Temporary until we know how many other bridges are behind this one. */
 
@@ -985,5 +915,5 @@
 
                 /* The number of bridges behind the this one is now available. */
-                pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus);
+                pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uPciBiosBus);
 
                 /*
@@ -1702,7 +1632,7 @@
      * Set the start addresses.
      */
-    pGlobals->uPciBiosIo  = 0xd000;
+    pGlobals->uPciBiosBus  = 0;
+    pGlobals->uPciBiosIo   = 0xd000;
     pGlobals->uPciBiosMmio = UINT32_C(0xf0000000);
-    pGlobals->uBus = 0;
 
     /*
Index: trunk/src/VBox/Devices/Bus/DevPciIch9.cpp
===================================================================
--- trunk/src/VBox/Devices/Bus/DevPciIch9.cpp	(revision 64418)
+++ trunk/src/VBox/Devices/Bus/DevPciIch9.cpp	(revision 64419)
@@ -52,51 +52,10 @@
 *   Structures and Typedefs                                                                                                      *
 *********************************************************************************************************************************/
-typedef DEVPCIBUS  ICH9PCIBUS;
-typedef PDEVPCIBUS PICH9PCIBUS;
-
-
-/**
- * PCI Globals - This is the host-to-pci bridge and the root bus.
- */
-typedef struct
-{
-    /** PCI bus which is attached to the host-to-PCI bridge.
-     * This must come first so we can share more code with the bridges!  */
-    DEVPCIBUS           PciBus;
-
-    /** R3 pointer to the device instance. */
-    PPDMDEVINSR3        pDevInsR3;
-    /** R0 pointer to the device instance. */
-    PPDMDEVINSR0        pDevInsR0;
-    /** RC pointer to the device instance. */
-    PPDMDEVINSRC        pDevInsRC;
-
-    /** I/O APIC usage flag (always true of ICH9, see constructor). */
-    bool                fUseIoApic;
-    /** Reserved for future config flags. */
-    bool                afFutureFlags[3];
-    /** Physical address of PCI config space MMIO region. */
-    uint64_t            u64PciConfigMMioAddress;
-    /** Length of PCI config space MMIO region. */
-    uint64_t            u64PciConfigMMioLength;
-
-    /** I/O APIC irq levels */
-    volatile uint32_t   auPciApicIrqLevels[DEVPCI_APIC_IRQ_PINS];
-    /** Value latched in Configuration Address Port (0CF8h) */
-    uint32_t            uConfigReg;
-
-#if 1 /* Will be moved into the BIOS "soon". */
-    /** Current bus number (?). */
-    uint8_t             uPciBiosBus;
-    uint8_t             Alignment0[3];
-    /** The next I/O port address which the PCI BIOS will use. */
-    uint32_t            uPciBiosIo;
-    /** The next MMIO address which the PCI BIOS will use. */
-    uint32_t            uPciBiosMmio;
-    /** The next 64-bit MMIO address which the PCI BIOS will use. */
-    uint64_t            uPciBiosMmio64;
-#endif
-
-} ICH9PCIGLOBALS, *PICH9PCIGLOBALS;
+typedef DEVPCIBUS     ICH9PCIBUS;
+typedef PDEVPCIBUS    PICH9PCIBUS;
+typedef DEVPCIROOT    ICH9PCIGLOBALS;
+typedef PDEVPCIROOT   PICH9PCIGLOBALS;
+
+
 
 
Index: trunk/src/VBox/Devices/Bus/DevPciInternal.h
===================================================================
--- trunk/src/VBox/Devices/Bus/DevPciInternal.h	(revision 64418)
+++ trunk/src/VBox/Devices/Bus/DevPciInternal.h	(revision 64419)
@@ -85,4 +85,80 @@
 #define DEVPCI_LEGACY_IRQ_PINS  4
 
+/**
+ * PIIX3 ISA bridge state.
+ */
+typedef struct PIIX3ISABRIDGE
+{
+    /** The PCI device of the bridge. */
+    PDMPCIDEV dev;
+} PIIX3ISABRIDGE;
+
+
+/**
+ * PCI Globals - This is the host-to-pci bridge and the root bus.
+ *
+ * @note Only used by the root bus, not the bridges.
+ */
+typedef struct DEVPCIROOT
+{
+    /** PCI bus which is attached to the host-to-PCI bridge.
+     * @note This must come first so we can share more code with the bridges!  */
+    DEVPCIBUS           PciBus;
+
+    /** R3 pointer to the device instance. */
+    PPDMDEVINSR3        pDevInsR3;
+    /** R0 pointer to the device instance. */
+    PPDMDEVINSR0        pDevInsR0;
+    /** RC pointer to the device instance. */
+    PPDMDEVINSRC        pDevInsRC;
+
+    /** I/O APIC usage flag (always true of ICH9, see constructor). */
+    bool                fUseIoApic;
+    /** Reserved for future config flags. */
+    bool                afFutureFlags[3];
+    /** Physical address of PCI config space MMIO region. */
+    uint64_t            u64PciConfigMMioAddress;
+    /** Length of PCI config space MMIO region. */
+    uint64_t            u64PciConfigMMioLength;
+
+    /** I/O APIC irq levels */
+    volatile uint32_t   auPciApicIrqLevels[DEVPCI_APIC_IRQ_PINS];
+    /** Value latched in Configuration Address Port (0CF8h) */
+    uint32_t            uConfigReg;
+    /** Alignment padding.   */
+    uint32_t            u32Alignment1;
+    /** Members only used by the PIIX3 code variant. */
+    struct
+    {
+        /** ACPI IRQ level */
+        uint32_t            iAcpiIrqLevel;
+        /** ACPI PIC IRQ */
+        int32_t             iAcpiIrq;
+        /** Irq levels for the four PCI Irqs.
+         * These count how many devices asserted the IRQ line.  If greater 0 an IRQ
+         * is sent to the guest.  If it drops to 0 the IRQ is deasserted.
+         * @remarks Labling this "legacy" might be a bit off...
+         */
+        volatile uint32_t   auPciLegacyIrqLevels[DEVPCI_LEGACY_IRQ_PINS];
+        /** ISA bridge state. */
+        PIIX3ISABRIDGE      PIIX3State;
+    } Piix3;
+
+#if 1 /* Will be moved into the BIOS "soon". */
+    /** Current bus number (?). */
+    uint8_t             uPciBiosBus;
+    uint8_t             abAlignment2[7];
+    /** The next I/O port address which the PCI BIOS will use. */
+    uint32_t            uPciBiosIo;
+    /** The next MMIO address which the PCI BIOS will use. */
+    uint32_t            uPciBiosMmio;
+    /** The next 64-bit MMIO address which the PCI BIOS will use. */
+    uint64_t            uPciBiosMmio64;
+#endif
+
+} DEVPCIROOT;
+/** Pointer to PCI device globals. */
+typedef DEVPCIROOT *PDEVPCIROOT;
+
 
 #endif
Index: trunk/src/VBox/Devices/testcase/tstDeviceStructSize.cpp
===================================================================
--- trunk/src/VBox/Devices/testcase/tstDeviceStructSize.cpp	(revision 64418)
+++ trunk/src/VBox/Devices/testcase/tstDeviceStructSize.cpp	(revision 64419)
@@ -29,7 +29,5 @@
 #define VBOX_DEVICE_STRUCT_TESTCASE
 #undef LOG_GROUP
-#include "../Bus/DevPCI.cpp"
-#undef LOG_GROUP
-#include "../Bus/DevPciIch9.cpp"
+#include "../Bus/DevPciInternal.h"
 #undef LOG_GROUP
 #include "../Graphics/DevVGA.cpp"
@@ -362,5 +360,6 @@
 #endif
     CHECK_MEMBER_ALIGNMENT(DEVPCIBUS, apDevices, 64);
-//    CHECK_MEMBER_ALIGNMENT(PCIGLOBALS, Piix3.auPciLegacyIrqLevels, 16); - reenable later
+    CHECK_MEMBER_ALIGNMENT(DEVPCIROOT, auPciApicIrqLevels, 16);
+    CHECK_MEMBER_ALIGNMENT(DEVPCIROOT, Piix3.auPciLegacyIrqLevels, 16);
     CHECK_MEMBER_ALIGNMENT(PCNETSTATE, u64LastPoll, 8);
     CHECK_MEMBER_ALIGNMENT(PCNETSTATE, CritSect, 8);
Index: trunk/src/VBox/Devices/testcase/tstDeviceStructSizeRC.cpp
===================================================================
--- trunk/src/VBox/Devices/testcase/tstDeviceStructSizeRC.cpp	(revision 64418)
+++ trunk/src/VBox/Devices/testcase/tstDeviceStructSizeRC.cpp	(revision 64419)
@@ -38,8 +38,4 @@
 #undef LOG_GROUP
 #include "../Bus/DevPciInternal.h"
-#undef LOG_GROUP
-#include "../Bus/DevPCI.cpp" /* must be first! */
-#undef LOG_GROUP
-#include "../Bus/DevPciIch9.cpp"
 #undef LOG_GROUP
 #include "../EFI/DevSmc.cpp"
@@ -191,39 +187,25 @@
     GEN_CHECK_OFF(DEVPCIBUS, pPciHlpRC);
     GEN_CHECK_OFF(DEVPCIBUS, PciDev);
-
-    /* DevPCI.cpp */
-    GEN_CHECK_SIZE(PIIX3State);
-    GEN_CHECK_SIZE(PCIGLOBALS);
-    GEN_CHECK_OFF(PCIGLOBALS, uPciBiosIo);
-    GEN_CHECK_OFF(PCIGLOBALS, uPciBiosMmio);
-    GEN_CHECK_OFF(PCIGLOBALS, fUseIoApic);
-    GEN_CHECK_OFF(PCIGLOBALS, pDevInsR3);
-    GEN_CHECK_OFF(PCIGLOBALS, pDevInsR0);
-    GEN_CHECK_OFF(PCIGLOBALS, pDevInsRC);
-    GEN_CHECK_OFF(PCIGLOBALS, uConfigReg);
-    GEN_CHECK_OFF(PCIGLOBALS, auPciApicIrqLevels);
-    GEN_CHECK_OFF(PCIGLOBALS, auPciApicIrqLevels[1]);
-    GEN_CHECK_OFF(PCIGLOBALS, Piix3.auPciLegacyIrqLevels);
-    GEN_CHECK_OFF(PCIGLOBALS, Piix3.auPciLegacyIrqLevels[1]);
-    GEN_CHECK_OFF(PCIGLOBALS, Piix3.iAcpiIrqLevel);
-    GEN_CHECK_OFF(PCIGLOBALS, Piix3.iAcpiIrq);
-    GEN_CHECK_OFF(PCIGLOBALS, Piix3.PIIX3State);
-    GEN_CHECK_OFF(PCIGLOBALS, PciBus);
-
-    /* DevPciIch9.cpp */
-    GEN_CHECK_SIZE(ICH9PCIGLOBALS);
-    GEN_CHECK_OFF(ICH9PCIGLOBALS, pDevInsR3);
-    GEN_CHECK_OFF(ICH9PCIGLOBALS, pDevInsR0);
-    GEN_CHECK_OFF(ICH9PCIGLOBALS, pDevInsRC);
-    GEN_CHECK_OFF(ICH9PCIGLOBALS, uConfigReg);
-    GEN_CHECK_OFF(ICH9PCIGLOBALS, auPciApicIrqLevels);
-    GEN_CHECK_OFF(ICH9PCIGLOBALS, auPciApicIrqLevels[1]);
-    GEN_CHECK_OFF(ICH9PCIGLOBALS, uPciBiosBus);
-    GEN_CHECK_OFF(ICH9PCIGLOBALS, uPciBiosIo);
-    GEN_CHECK_OFF(ICH9PCIGLOBALS, uPciBiosMmio);
-    GEN_CHECK_OFF(ICH9PCIGLOBALS, uPciBiosMmio64);
-    GEN_CHECK_OFF(ICH9PCIGLOBALS, u64PciConfigMMioAddress);
-    GEN_CHECK_OFF(ICH9PCIGLOBALS, u64PciConfigMMioLength);
-    GEN_CHECK_OFF(ICH9PCIGLOBALS, PciBus);
+    GEN_CHECK_SIZE(PIIX3ISABRIDGE);
+    GEN_CHECK_SIZE(DEVPCIROOT);
+    GEN_CHECK_OFF(DEVPCIROOT, PciBus);
+    GEN_CHECK_OFF(DEVPCIROOT, pDevInsR3);
+    GEN_CHECK_OFF(DEVPCIROOT, pDevInsR0);
+    GEN_CHECK_OFF(DEVPCIROOT, pDevInsRC);
+    GEN_CHECK_OFF(DEVPCIROOT, fUseIoApic);
+    GEN_CHECK_OFF(DEVPCIROOT, u64PciConfigMMioAddress);
+    GEN_CHECK_OFF(DEVPCIROOT, u64PciConfigMMioLength);
+    GEN_CHECK_OFF(DEVPCIROOT, auPciApicIrqLevels);
+    GEN_CHECK_OFF(DEVPCIROOT, auPciApicIrqLevels[1]);
+    GEN_CHECK_OFF(DEVPCIROOT, uConfigReg);
+    GEN_CHECK_OFF(DEVPCIROOT, Piix3.iAcpiIrqLevel);
+    GEN_CHECK_OFF(DEVPCIROOT, Piix3.iAcpiIrq);
+    GEN_CHECK_OFF(DEVPCIROOT, Piix3.auPciLegacyIrqLevels);
+    GEN_CHECK_OFF(DEVPCIROOT, Piix3.auPciLegacyIrqLevels[1]);
+    GEN_CHECK_OFF(DEVPCIROOT, Piix3.PIIX3State);
+    GEN_CHECK_OFF(DEVPCIROOT, uPciBiosBus);
+    GEN_CHECK_OFF(DEVPCIROOT, uPciBiosIo);
+    GEN_CHECK_OFF(DEVPCIROOT, uPciBiosMmio);
+    GEN_CHECK_OFF(DEVPCIROOT, uPciBiosMmio64);
 
     /* EFI/DevSMC.cpp */
