VirtualBox

Changeset 64420 in vbox


Ignore:
Timestamp:
Oct 25, 2016 3:51:03 PM (9 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
111537
Message:

DevPci: Post ICH9PCIGLOBALS and PCIGLOBALS cleanups.

Location:
trunk/src/VBox/Devices/Bus
Files:
4 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/Devices/Bus/DevPCI.cpp

    r64419 r64420  
    6969
    7070/*********************************************************************************************************************************
    71 *   Structures and Typedefs                                                                                                      *
    72 *********************************************************************************************************************************/
    73 typedef DEVPCIBUS       PCIBUS;
    74 typedef PDEVPCIBUS      PPCIBUS;
    75 typedef DEVPCIROOT      PCIGLOBALS;
    76 typedef PDEVPCIROOT     PPCIGLOBALS;
    77 
    78 
    79 /*********************************************************************************************************************************
    8071*   Defined Constants And Macros                                                                                                 *
    8172*********************************************************************************************************************************/
    82 
    83 /** Converts a bus instance pointer to a device instance pointer. */
    84 #define PCIBUS_2_DEVINS(pPciBus)        ((pPciBus)->CTX_SUFF(pDevIns))
    85 /** Converts a PCI bus device instance pointer to a PCIGLOBALS pointer. */
    86 #define DEVINS_2_PCIGLOBALS(pDevIns)    ((PPCIGLOBALS)(PDMINS_2_DATA(pDevIns, PPCIGLOBALS)))
    87 /** Converts a PCI bus device instance pointer to a DEVPCIBUS pointer. */
    88 #define DEVINS_2_PCIBUS(pDevIns)        ((PPCIBUS)(&PDMINS_2_DATA(pDevIns, PPCIGLOBALS)->PciBus))
    89 
    90 /** Converts a pointer to a PCI bus instance to a PCIGLOBALS pointer.
    91  *  @note This works only if the bus number is 0!!!
    92  */
    93 #define PCIBUS_2_PCIGLOBALS(pPciBus)    RT_FROM_MEMBER(pPciBus, PCIGLOBALS, PciBus)
    94 
    95 /** @def PCI_LOCK
    96  * Acquires the PDM lock. This is a NOP if locking is disabled. */
    97 /** @def PCI_UNLOCK
    98  * Releases the PDM lock. This is a NOP if locking is disabled. */
    99 #define PCI_LOCK(pDevIns, rc) \
    100     do { \
    101         int rc2 = DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
    102         if (rc2 != VINF_SUCCESS) \
    103             return rc2; \
    104     } while (0)
    105 #define PCI_UNLOCK(pDevIns) \
    106     DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
    107 
    10873/** @def VBOX_PCI_SAVED_STATE_VERSION
    10974 * Saved state version of the PCI bus device.
    11075 */
    11176#define VBOX_PCI_SAVED_STATE_VERSION 3
    112 
    113 
    114 #ifndef VBOX_DEVICE_STRUCT_TESTCASE
    11577
    11678
    … …  
    12890
    12991#ifdef IN_RING3
    130 DECLINLINE(PPDMPCIDEV) pciR3FindBridge(PPCIBUS pBus, uint8_t iBus);
     92DECLINLINE(PPDMPCIDEV) pciR3FindBridge(PDEVPCIBUS pBus, uint8_t iBus);
    13193#endif
    13294
    … …  
    151113static void pci_update_mappings(PDMPCIDEV *d)
    152114{
    153     PPCIBUS pBus = d->Int.s.CTX_SUFF(pBus);
     115    PDEVPCIBUS pBus = d->Int.s.CTX_SUFF(pBus);
    154116    PCIIORegion *r;
    155117    int cmd, i;
    … …  
    391353#endif /* IN_RING3 */
    392354
    393 static int pci_data_write(PPCIGLOBALS pGlobals, uint32_t addr, uint32_t val, int len)
     355static int pci_data_write(PDEVPCIROOT pGlobals, uint32_t addr, uint32_t val, int len)
    394356{
    395357    uint8_t iBus, iDevice;
    … …  
    440402}
    441403
    442 static int pci_data_read(PPCIGLOBALS pGlobals, uint32_t addr, int len, uint32_t *pu32)
     404static int pci_data_read(PDEVPCIROOT pGlobals, uint32_t addr, int len, uint32_t *pu32)
    443405{
    444406    uint8_t iBus, iDevice;
    … …  
    507469}
    508470
    509 static inline int get_pci_irq_apic_level(PPCIGLOBALS pGlobals, int irq_num)
     471static inline int get_pci_irq_apic_level(PDEVPCIROOT pGlobals, int irq_num)
    510472{
    511473    return (pGlobals->auPciApicIrqLevels[irq_num] != 0);
    512474}
    513475
    514 static void apic_set_irq(PPCIBUS pBus, uint8_t uDevFn, PDMPCIDEV *pPciDev, int irq_num1, int iLevel, int iAcpiIrq, uint32_t uTagSrc)
     476static void apic_set_irq(PDEVPCIBUS pBus, uint8_t uDevFn, PDMPCIDEV *pPciDev, int irq_num1, int iLevel, int iAcpiIrq, uint32_t uTagSrc)
    515477{
    516478    /* This is only allowed to be called with a pointer to the host bus. */
    … …  
    519481    if (iAcpiIrq == -1) {
    520482        int apic_irq, apic_level;
    521         PPCIGLOBALS pGlobals = PCIBUS_2_PCIGLOBALS(pBus);
     483        PDEVPCIROOT pGlobals = DEVPCIBUS_2_DEVPCIROOT(pBus);
    522484        int irq_num = pci_slot_get_apic_pirq(uDevFn, irq_num1);
    523485
    … …  
    548510}
    549511
    550 DECLINLINE(int) get_pci_irq_level(PPCIGLOBALS pGlobals, int irq_num)
     512DECLINLINE(int) get_pci_irq_level(PDEVPCIROOT pGlobals, int irq_num)
    551513{
    552514    return (pGlobals->Piix3.auPciLegacyIrqLevels[irq_num] != 0);
    … …  
    566528 *          is needed to calculate the PIRQ value.
    567529 */
    568 static void pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
    569 {
    570     PPCIBUS     pBus =     &pGlobals->PciBus;
     530static void pciSetIrqInternal(PDEVPCIROOT pGlobals, uint8_t uDevFn, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
     531{
     532    PDEVPCIBUS     pBus =     &pGlobals->PciBus;
    571533    uint8_t    *pbCfg = pGlobals->Piix3.PIIX3State.dev.abConfig;
    572534    const bool  fIsAcpiDevice = pPciDev->abConfig[2] == 0x13 && pPciDev->abConfig[3] == 0x71;
    … …  
    660622PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
    661623{
    662     pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), pPciDev->uDevFn, pPciDev, iIrq, iLevel, uTagSrc);
     624    pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PDEVPCIROOT), pPciDev->uDevFn, pPciDev, iIrq, iLevel, uTagSrc);
    663625}
    664626
    … …  
    673635 * @param  iBus    Destination bus number.
    674636 */
    675 DECLINLINE(PPDMPCIDEV) pciR3FindBridge(PPCIBUS pBus, uint8_t iBus)
     637DECLINLINE(PPDMPCIDEV) pciR3FindBridge(PDEVPCIBUS pBus, uint8_t iBus)
    676638{
    677639    /* Search for a fitting bridge. */
    … …  
    729691}
    730692
    731 static void pci_config_writel(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
     693static void pci_config_writel(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
    732694{
    733695    pGlobals->uConfigReg = 0x80000000 | (uBus << 16) |
    … …  
    736698}
    737699
    738 static void pci_config_writew(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
     700static void pci_config_writew(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
    739701{
    740702    pGlobals->uConfigReg = 0x80000000 | (uBus << 16) |
    … …  
    743705}
    744706
    745 static void pci_config_writeb(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
     707static void pci_config_writeb(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
    746708{
    747709    pGlobals->uConfigReg = 0x80000000 | (uBus << 16) |
    … …  
    750712}
    751713
    752 static uint32_t pci_config_readl(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
     714static uint32_t pci_config_readl(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
    753715{
    754716    pGlobals->uConfigReg = 0x80000000 | (uBus << 16) |
    … …  
    760722}
    761723
    762 static uint32_t pci_config_readw(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
     724static uint32_t pci_config_readw(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
    763725{
    764726    pGlobals->uConfigReg = 0x80000000 | (uBus << 16) |
    … …  
    770732}
    771733
    772 static uint32_t pci_config_readb(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
     734static uint32_t pci_config_readb(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
    773735{
    774736    pGlobals->uConfigReg = 0x80000000 | (uBus << 16) |
    … …  
    783745static const uint8_t pci_irqs[4] = { 11, 9, 11, 9 }; /* bird: added const */
    784746
    785 static void pci_set_io_region_addr(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int region_num, uint32_t addr)
     747static void pci_set_io_region_addr(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn, int region_num, uint32_t addr)
    786748{
    787749    uint32_t ofs;
    … …  
    799761}
    800762
    801 static void pci_bios_init_device(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
     763static void pci_bios_init_device(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
    802764{
    803765    uint32_t *paddr;
    … …  
    10661028    if (cb == 4)
    10671029    {
    1068         PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
     1030        PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
    10691031        PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
    10701032        pThis->uConfigReg = u32 & ~3; /* Bits 0-1 are reserved and we silently clear them */
    … …  
    10851047    if (cb == 4)
    10861048    {
    1087         PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
     1049        PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
    10881050        PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
    10891051        *pu32 = pThis->uConfigReg;
    … …  
    11101072    {
    11111073        PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
    1112         rc = pci_data_write(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, u32, cb);
     1074        rc = pci_data_write(PDMINS_2_DATA(pDevIns, PDEVPCIROOT), Port, u32, cb);
    11131075        PCI_UNLOCK(pDevIns);
    11141076    }
    … …  
    11281090    {
    11291091        PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
    1130         int rc = pci_data_read(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, cb, pu32);
     1092        int rc = pci_data_read(PDMINS_2_DATA(pDevIns, PDEVPCIROOT), Port, cb, pu32);
    11311093        PCI_UNLOCK(pDevIns);
    11321094        Log(("pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
    … …  
    11601122 * @param   pSSM            The saved state handle.
    11611123 */
    1162 static int pciR3CommonSaveExec(PPCIBUS pBus, PSSMHANDLE pSSM)
     1124static int pciR3CommonSaveExec(PDEVPCIBUS pBus, PSSMHANDLE pSSM)
    11631125{
    11641126    /*
    … …  
    11881150{
    11891151    uint32_t    i;
    1190     PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
     1152    PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
    11911153
    11921154    /*
    … …  
    13911353 * @param   uPass               The pass.
    13921354 */
    1393 static DECLCALLBACK(int) pciR3CommonLoadExec(PPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
     1355static DECLCALLBACK(int) pciR3CommonLoadExec(PDEVPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
    13941356{
    13951357    uint32_t    u32;
    … …  
    15041466static DECLCALLBACK(int) pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
    15051467{
    1506     PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
    1507     PPCIBUS     pBus  = &pThis->PciBus;
     1468    PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
     1469    PDEVPCIBUS     pBus  = &pThis->PciBus;
    15081470    uint32_t    u32;
    15091471    int         rc;
    … …  
    16221584    unsigned        i;
    16231585    uint8_t         elcr[2]    = {0, 0};
    1624     PPCIGLOBALS     pGlobals   = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
     1586    PDEVPCIROOT     pGlobals   = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
    16251587    PVM             pVM        = PDMDevHlpGetVM(pDevIns); Assert(pVM);
    16261588    PVMCPU          pVCpu      = PDMDevHlpGetVMCPU(pDevIns); Assert(pVM);
    … …  
    16821644static DECLCALLBACK(void) pciR3IrqRouteInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
    16831645{
    1684     PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
     1646    PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
    16851647    NOREF(pszArgs);
    16861648
    … …  
    17041666static DECLCALLBACK(void) pciR3IrqInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
    17051667{
    1706     PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
     1668    PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
    17071669    NOREF(pszArgs);
    17081670
    … …  
    17331695 *                      of each device on the bus.
    17341696 */
    1735 static void pciR3BusInfo(PPCIBUS pBus, PCDBGFINFOHLP pHlp, int iIndent, bool fRegisters)
     1697static void pciR3BusInfo(PDEVPCIBUS pBus, PCDBGFINFOHLP pHlp, int iIndent, bool fRegisters)
    17361698{
    17371699    for (uint32_t iDev = 0; iDev < RT_ELEMENTS(pBus->apDevices); iDev++)
    … …  
    18341796        for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
    18351797        {
    1836             PPCIBUS pBusSub = PDMINS_2_DATA(pBus->papBridgesR3[iBridge]->Int.s.CTX_SUFF(pDevIns), PPCIBUS);
     1798            PDEVPCIBUS pBusSub = PDMINS_2_DATA(pBus->papBridgesR3[iBridge]->Int.s.CTX_SUFF(pDevIns), PDEVPCIBUS);
    18371799            pciR3BusInfo(pBusSub, pHlp, iIndent + 1, fRegisters);
    18381800        }
    … …  
    18461808static DECLCALLBACK(void) pciR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
    18471809{
    1848     PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
     1810    PDEVPCIBUS pBus = DEVINS_2_DEVPCIBUS(pDevIns);
    18491811
    18501812    if (pszArgs == NULL || !*pszArgs || !strcmp(pszArgs, "basic"))
    … …  
    18641826static DECLCALLBACK(void) pciR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
    18651827{
    1866     PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
    1867     PPCIBUS     pBus     = &pGlobals->PciBus;
     1828    PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
     1829    PDEVPCIBUS     pBus     = &pGlobals->PciBus;
    18681830    pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
    18691831
    … …  
    19291891     * Init data and register the PCI bus.
    19301892     */
    1931     PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
     1893    PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
    19321894    pGlobals->uPciBiosIo   = 0xc000;
    19331895    pGlobals->uPciBiosMmio = 0xf0000000;
    … …  
    19531915
    19541916    PDMPCIBUSREG PciBusReg;
    1955     PPCIBUS      pBus = &pGlobals->PciBus;
     1917    PDEVPCIBUS      pBus = &pGlobals->PciBus;
    19561918    PciBusReg.u32Version              = PDM_PCIBUSREG_VERSION;
    19571919    PciBusReg.pfnRegisterR3           = pciR3MergedRegister;
    … …  
    20732035    1,
    20742036    /* cbInstance */
    2075     sizeof(PCIGLOBALS),
     2037    sizeof(DEVPCIROOT),
    20762038    /* pfnConstruct */
    20772039    pciR3Construct,
    … …  
    21242086     * of our parent passing the device which asserted the interrupt instead of the device of the bridge.
    21252087     */
    2126     PPCIBUS    pBus          = PDMINS_2_DATA(pDevIns, PPCIBUS);
     2088    PDEVPCIBUS    pBus          = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
    21272089    PPDMPCIDEV pPciDevBus    = pPciDev;
    21282090    int        iIrqPinBridge = iIrq;
    … …  
    21412103
    21422104    AssertMsg(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
    2143     pciSetIrqInternal(PCIBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
     2105    pciSetIrqInternal(DEVPCIBUS_2_DEVPCIROOT(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
    21442106}
    21452107
    … …  
    21512113static DECLCALLBACK(void) pcibridgeR3ConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
    21522114{
    2153     PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
     2115    PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
    21542116
    21552117    LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
    … …  
    21832145static DECLCALLBACK(uint32_t) pcibridgeR3ConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
    21842146{
    2185     PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
     2147    PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
    21862148    uint32_t u32Value = 0xffffffff; /* Return value in case there is no device. */
    21872149
    … …  
    22182180static DECLCALLBACK(int) pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
    22192181{
    2220     PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
     2182    PDEVPCIBUS pThis = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
    22212183    return pciR3CommonSaveExec(pThis, pSSM);
    22222184}
    … …  
    22282190static DECLCALLBACK(int) pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
    22292191{
    2230     PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
     2192    PDEVPCIBUS pThis = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
    22312193    if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
    22322194        return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
    … …  
    22402202static DECLCALLBACK(void) pcibridgeR3Reset(PPDMDEVINS pDevIns)
    22412203{
    2242     PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
     2204    PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
    22432205
    22442206    /* Reset config space to default values. */
    … …  
    22542216static DECLCALLBACK(void) pcibridgeR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
    22552217{
    2256     PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
     2218    PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
    22572219    pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
    22582220
    … …  
    22972259     * Init data and register the PCI bus.
    22982260     */
    2299     PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
     2261    PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
    23002262    pBus->fTypePiix3  = true;
    23012263    pBus->fTypeIch9   = false;
    … …  
    24422404
    24432405#endif /* IN_RING3 */
    2444 #endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
     2406

  • trunk/src/VBox/Devices/Bus/DevPciIch9.cpp

    r64419 r64420  
    5252*   Structures and Typedefs                                                                                                      *
    5353*********************************************************************************************************************************/
    54 typedef DEVPCIBUS     ICH9PCIBUS;
    55 typedef PDEVPCIBUS    PICH9PCIBUS;
    56 typedef DEVPCIROOT    ICH9PCIGLOBALS;
    57 typedef PDEVPCIROOT   PICH9PCIGLOBALS;
    58 
    59 
    60 
    61 
    6254/**
    6355 * PCI configuration space address.
    … …  
    7062} PciAddress;
    7163
    72 #ifndef VBOX_DEVICE_STRUCT_TESTCASE
    73 
    7464
    7565/*********************************************************************************************************************************
    7666*   Defined Constants And Macros                                                                                                 *
    7767*********************************************************************************************************************************/
    78 
    7968/** @def VBOX_ICH9PCI_SAVED_STATE_VERSION
    8069 * Saved state version of the ICH9 PCI bus device.
    … …  
    8473#define VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI
    8574
    86 /** Converts a bus instance pointer to a device instance pointer. */
    87 #define PCIBUS_2_DEVINS(pPciBus)        ((pPciBus)->CTX_SUFF(pDevIns))
    88 /** Converts a device instance pointer to a ICH9PCIGLOBALS pointer. */
    89 #define DEVINS_2_PCIGLOBALS(pDevIns)    ((PICH9PCIGLOBALS)(PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS)))
    90 /** Converts a device instance pointer to a PCIBUS pointer. */
    91 #define DEVINS_2_PCIBUS(pDevIns)        ((PICH9PCIBUS)(&PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS)->PciBus))
    92 /** Converts a pointer to a PCI root bus instance to a PCIGLOBALS pointer. */
    93 #define PCIROOTBUS_2_PCIGLOBALS(pPciBus)    ( (PICH9PCIGLOBALS)((uintptr_t)(pPciBus) - RT_OFFSETOF(ICH9PCIGLOBALS, PciBus)) )
    94 
    95 /** @def PCI_LOCK
    96  * Acquires the PDM lock. This is a NOP if locking is disabled. */
    97 /** @def PCI_UNLOCK
    98  * Releases the PDM lock. This is a NOP if locking is disabled. */
    99 #define PCI_LOCK(pDevIns, rc) \
    100     do { \
    101         int rc2 = DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
    102         if (rc2 != VINF_SUCCESS) \
    103             return rc2; \
    104     } while (0)
    105 #define PCI_UNLOCK(pDevIns) \
    106     DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
    107 
     75
     76/*********************************************************************************************************************************
     77*   Internal Functions                                                                                                           *
     78*********************************************************************************************************************************/
    10879/* Prototypes */
    109 static void ich9pciSetIrqInternal(PICH9PCIGLOBALS pGlobals, uint8_t uDevFn, PPDMPCIDEV pPciDev,
     80static void ich9pciSetIrqInternal(PDEVPCIROOT pGlobals, uint8_t uDevFn, PPDMPCIDEV pPciDev,
    11081                                  int iIrq, int iLevel, uint32_t uTagSrc);
    11182#ifdef IN_RING3
    … …  
    11485static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t u32Address, unsigned len);
    11586static DECLCALLBACK(void)     ich9pciConfigWriteDev(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t u32Address, uint32_t val, unsigned len);
    116 DECLINLINE(PPDMPCIDEV) ich9pciFindBridge(PICH9PCIBUS pBus, uint8_t iBus);
    117 static void ich9pciBiosInitDevice(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn);
     87DECLINLINE(PPDMPCIDEV) ich9pciFindBridge(PDEVPCIBUS pBus, uint8_t iBus);
     88static void ich9pciBiosInitDevice(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn);
    11889#endif
    11990
    12091// See 7.2.2. PCI Express Enhanced Configuration Mechanism for details of address
    12192// mapping, we take n=6 approach
    122 DECLINLINE(void) ich9pciPhysToPciAddr(PICH9PCIGLOBALS pGlobals, RTGCPHYS GCPhysAddr, PciAddress* pPciAddr)
     93DECLINLINE(void) ich9pciPhysToPciAddr(PDEVPCIROOT pGlobals, RTGCPHYS GCPhysAddr, PciAddress* pPciAddr)
    12394{
    12495    NOREF(pGlobals);
    … …  
    12899}
    129100
    130 DECLINLINE(void) ich9pciStateToPciAddr(PICH9PCIGLOBALS pGlobals, RTGCPHYS addr, PciAddress* pPciAddr)
     101DECLINLINE(void) ich9pciStateToPciAddr(PDEVPCIROOT pGlobals, RTGCPHYS addr, PciAddress* pPciAddr)
    131102{
    132103    pPciAddr->iBus         = (pGlobals->uConfigReg >> 16) & 0xff;
    … …  
    138109{
    139110    LogFlowFunc(("invoked by %p/%d: iIrq=%d iLevel=%d uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, iIrq, iLevel, uTagSrc));
    140     ich9pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS), pPciDev->uDevFn, pPciDev, iIrq, iLevel, uTagSrc);
     111    ich9pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PDEVPCIROOT), pPciDev->uDevFn, pPciDev, iIrq, iLevel, uTagSrc);
    141112}
    142113
    … …  
    150121     * of our parent passing the device which asserted the interrupt instead of the device of the bridge.
    151122     */
    152     PICH9PCIBUS    pBus          = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
     123    PDEVPCIBUS    pBus          = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
    153124    PPDMPCIDEV     pPciDevBus    = pPciDev;
    154125    int            iIrqPinBridge = iIrq;
    … …  
    167138
    168139    AssertMsgReturnVoid(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
    169     ich9pciSetIrqInternal(PCIROOTBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
     140    ich9pciSetIrqInternal(DEVPCIBUS_2_DEVPCIROOT(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
    170141}
    171142
    … …  
    191162    if (cb == 4)
    192163    {
    193         PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
     164        PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
    194165
    195166        /*
    … …  
    227198    if (cb == 4)
    228199    {
    229         PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
     200        PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
    230201
    231202        PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
    … …  
    245216 * Perform configuration space write.
    246217 */
    247 static int ich9pciDataWriteAddr(PICH9PCIGLOBALS pGlobals, PciAddress* pAddr,
     218static int ich9pciDataWriteAddr(PDEVPCIROOT pGlobals, PciAddress* pAddr,
    248219                                uint32_t val, int cb, int rcReschedule)
    249220{
    … …  
    300271 * similarly named functions.
    301272 */
    302 static int ich9pciDataWrite(PICH9PCIGLOBALS pGlobals, uint32_t addr, uint32_t val, int len)
     273static int ich9pciDataWrite(PDEVPCIROOT pGlobals, uint32_t addr, uint32_t val, int len)
    303274{
    304275    LogFlow(("ich9pciDataWrite: config=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
    … …  
    338309    if (!(Port % cb))
    339310    {
    340         PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
     311        PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
    341312
    342313        PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
    … …  
    360331 * Perform configuration space read.
    361332 */
    362 static int ich9pciDataReadAddr(PICH9PCIGLOBALS pGlobals, PciAddress* pPciAddr, int cb,
     333static int ich9pciDataReadAddr(PDEVPCIROOT pGlobals, PciAddress* pPciAddr, int cb,
    363334                               uint32_t *pu32, int rcReschedule)
    364335{
    … …  
    419390 * similarly named functions.
    420391 */
    421 static int ich9pciDataRead(PICH9PCIGLOBALS pGlobals, uint32_t addr, int cb, uint32_t *pu32)
     392static int ich9pciDataRead(PDEVPCIROOT pGlobals, uint32_t addr, int cb, uint32_t *pu32)
    422393{
    423394    LogFlow(("ich9pciDataRead: config=%x cb=%d\n",  pGlobals->uConfigReg, cb));
    … …  
    457428    if (!(Port % cb))
    458429    {
    459         PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
     430        PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
    460431
    461432        PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
    … …  
    495466
    496467/* Add one more level up request on APIC input line */
    497 DECLINLINE(void) ich9pciApicLevelUp(PICH9PCIGLOBALS pGlobals, int irq_num)
     468DECLINLINE(void) ich9pciApicLevelUp(PDEVPCIROOT pGlobals, int irq_num)
    498469{
    499470    ASMAtomicIncU32(&pGlobals->auPciApicIrqLevels[irq_num]);
    … …  
    501472
    502473/* Remove one level up request on APIC input line */
    503 DECLINLINE(void) ich9pciApicLevelDown(PICH9PCIGLOBALS pGlobals, int irq_num)
     474DECLINLINE(void) ich9pciApicLevelDown(PDEVPCIROOT pGlobals, int irq_num)
    504475{
    505476    ASMAtomicDecU32(&pGlobals->auPciApicIrqLevels[irq_num]);
    506477}
    507478
    508 static void ich9pciApicSetIrq(PICH9PCIBUS pBus, uint8_t uDevFn, PDMPCIDEV *pPciDev, int irq_num1, int iLevel,
     479static void ich9pciApicSetIrq(PDEVPCIBUS pBus, uint8_t uDevFn, PDMPCIDEV *pPciDev, int irq_num1, int iLevel,
    509480                              uint32_t uTagSrc, int iForcedIrq)
    510481{
    … …  
    515486    {
    516487        int apic_irq, apic_level;
    517         PICH9PCIGLOBALS pGlobals = PCIROOTBUS_2_PCIGLOBALS(pBus);
     488        PDEVPCIROOT pGlobals = DEVPCIBUS_2_DEVPCIROOT(pBus);
    518489        int irq_num = ich9pciSlot2ApicIrq(uDevFn >> 3, irq_num1);
    519490
    … …  
    549520}
    550521
    551 static void ich9pciSetIrqInternal(PICH9PCIGLOBALS pGlobals, uint8_t uDevFn, PPDMPCIDEV pPciDev,
     522static void ich9pciSetIrqInternal(PDEVPCIROOT pGlobals, uint8_t uDevFn, PPDMPCIDEV pPciDev,
    552523                                  int iIrq, int iLevel, uint32_t uTagSrc)
    553524{
    … …  
    574545    }
    575546
    576     PICH9PCIBUS     pBus      =     &pGlobals->PciBus;
     547    PDEVPCIBUS     pBus      =     &pGlobals->PciBus;
    577548    const bool  fIsAcpiDevice = PCIDevGetDeviceId(pPciDev) == 0x7113;
    578549
    … …  
    615586PDMBOTHCBDECL(int) ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
    616587{
    617     PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
     588    PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
    618589    uint32_t u32 = 0;
    619590    NOREF(pvUser);
    … …  
    667638PDMBOTHCBDECL(int) ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
    668639{
    669     PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
     640    PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
    670641    uint32_t    rv;
    671642    NOREF(pvUser);
    … …  
    719690
    720691
    721 DECLINLINE(PPDMPCIDEV) ich9pciFindBridge(PICH9PCIBUS pBus, uint8_t iBus)
     692DECLINLINE(PPDMPCIDEV) ich9pciFindBridge(PDEVPCIBUS pBus, uint8_t iBus)
    722693{
    723694    /* Search for a fitting bridge. */
    … …  
    774745    PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
    775746    int rc = VINF_SUCCESS;
    776     PICH9PCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
     747    PDEVPCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
    777748
    778749    Assert (pRegion->size != 0);
    … …  
    980951}
    981952
    982 static int ich9pciR3CommonSaveExec(PICH9PCIBUS pBus, PSSMHANDLE pSSM)
     953static int ich9pciR3CommonSaveExec(PDEVPCIBUS pBus, PSSMHANDLE pSSM)
    983954{
    984955    /*
    … …  
    10351006static DECLCALLBACK(int) ich9pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
    10361007{
    1037     PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
     1008    PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
    10381009
    10391010    /*
    … …  
    10561027static DECLCALLBACK(int) ich9pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
    10571028{
    1058     PICH9PCIBUS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
     1029    PDEVPCIBUS pThis = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
    10591030    return ich9pciR3CommonSaveExec(pThis, pSSM);
    10601031}
    … …  
    10631034static DECLCALLBACK(void) ich9pcibridgeConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
    10641035{
    1065     PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
     1036    PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
    10661037
    10671038    LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
    … …  
    10921063static DECLCALLBACK(uint32_t) ich9pcibridgeConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
    10931064{
    1094     PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
     1065    PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
    10951066    uint32_t u32Value;
    10961067
    … …  
    13031274 * @param   uPass               The pass.
    13041275 */
    1305 static DECLCALLBACK(int) ich9pciR3CommonLoadExec(PICH9PCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
     1276static DECLCALLBACK(int) ich9pciR3CommonLoadExec(PDEVPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
    13061277{
    13071278    uint32_t    u32;
    … …  
    14441415static DECLCALLBACK(int) ich9pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
    14451416{
    1446     PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
    1447     PICH9PCIBUS     pBus  = &pThis->PciBus;
     1417    PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
     1418    PDEVPCIBUS     pBus  = &pThis->PciBus;
    14481419    uint32_t        u32;
    14491420    int             rc;
    … …  
    14781449static DECLCALLBACK(int) ich9pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
    14791450{
    1480     PICH9PCIBUS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
     1451    PDEVPCIBUS pThis = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
    14811452    if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
    14821453        return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
    … …  
    14891460 * Cannot be rescheduled, as already in R3.
    14901461 */
    1491 static uint32_t ich9pciConfigRead(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t len)
     1462static uint32_t ich9pciConfigRead(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t len)
    14921463{
    14931464    PciAddress aPciAddr;
    … …  
    15081479 * Cannot be rescheduled, as already in R3.
    15091480 */
    1510 static void ich9pciConfigWrite(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val, uint32_t len)
     1481static void ich9pciConfigWrite(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val, uint32_t len)
    15111482{
    15121483    PciAddress aPciAddr;
    … …  
    15201491
    15211492
    1522 static void ich9pciSetRegionAddress(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int iRegion, uint64_t addr)
     1493static void ich9pciSetRegionAddress(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn, int iRegion, uint64_t addr)
    15231494{
    15241495    uint32_t uReg = ich9pciGetRegionReg(iRegion);
    … …  
    15391510
    15401511
    1541 static void ich9pciBiosInitBridge(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn)
     1512static void ich9pciBiosInitBridge(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn)
    15421513{
    15431514    Log(("BIOS init bridge: %02x::%02x.%d\n", uBus, uDevFn >> 3, uDevFn & 7));
    … …  
    16051576}
    16061577
    1607 static void ich9pciBiosInitDevice(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn)
     1578static void ich9pciBiosInitDevice(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn)
    16081579{
    16091580    uint16_t uDevClass, uVendor, uDevice;
    … …  
    17841755        {
    17851756            /* Find bus this device attached to. */
    1786             PICH9PCIBUS pBus = &pGlobals->PciBus;
     1757            PDEVPCIBUS pBus = &pGlobals->PciBus;
    17871758            while (1)
    17881759            {
    … …  
    17981769                    break;
    17991770                }
    1800                 pBus = PDMINS_2_DATA(pBridge->Int.s.CTX_SUFF(pDevIns), PICH9PCIBUS);
     1771                pBus = PDMINS_2_DATA(pBridge->Int.s.CTX_SUFF(pDevIns), PDEVPCIBUS);
    18011772            }
    18021773
    … …  
    18281799 * @param   uBusSecondary    The secondary bus number, i.e. the bus number behind the bridge.
    18291800 */
    1830 static void ich9pciInitBridgeTopology(PICH9PCIGLOBALS pGlobals, PICH9PCIBUS pBus, unsigned uBusPrimary,
     1801static void ich9pciInitBridgeTopology(PDEVPCIROOT pGlobals, PDEVPCIBUS pBus, unsigned uBusPrimary,
    18311802                                      unsigned uBusSecondary)
    18321803{
    … …  
    18451816        AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge),
    18461817                  ("Device is not a PCI bridge but on the list of PCI bridges\n"));
    1847         PICH9PCIBUS pChildBus = PDMINS_2_DATA(pBridge->Int.s.CTX_SUFF(pDevIns), PICH9PCIBUS);
     1818        PDEVPCIBUS pChildBus = PDMINS_2_DATA(pBridge->Int.s.CTX_SUFF(pDevIns), PDEVPCIBUS);
    18481819        pGlobals->uPciBiosBus++;
    18491820        ich9pciInitBridgeTopology(pGlobals, pChildBus, uBusSecondary, pGlobals->uPciBiosBus);
    … …  
    18611832static DECLCALLBACK(int) ich9pciFakePCIBIOS(PPDMDEVINS pDevIns)
    18621833{
    1863     PICH9PCIGLOBALS pGlobals   = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
     1834    PDEVPCIROOT pGlobals   = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
    18641835    PVM             pVM        = PDMDevHlpGetVM(pDevIns);
    18651836    uint32_t const  cbBelow4GB = MMR3PhysGetRamSizeBelow4GB(pVM);
    … …  
    18851856     * Assign bridge topology, for further routing to work.
    18861857     */
    1887     PICH9PCIBUS pBus = &pGlobals->PciBus;
     1858    PDEVPCIBUS pBus = &pGlobals->PciBus;
    18881859    ich9pciInitBridgeTopology(pGlobals, pBus, 0, 0);
    18891860
    … …  
    21662137}
    21672138
    2168 static void ich9pciBusInfo(PICH9PCIBUS pBus, PCDBGFINFOHLP pHlp, int iIndent, bool fRegisters)
     2139static void ich9pciBusInfo(PDEVPCIBUS pBus, PCDBGFINFOHLP pHlp, int iIndent, bool fRegisters)
    21692140{
    21702141    for (uint32_t iDev = 0; iDev < RT_ELEMENTS(pBus->apDevices); iDev++)
    … …  
    22842255        for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
    22852256        {
    2286             PICH9PCIBUS pBusSub = PDMINS_2_DATA(pBus->papBridgesR3[iBridge]->Int.s.CTX_SUFF(pDevIns), PICH9PCIBUS);
     2257            PDEVPCIBUS pBusSub = PDMINS_2_DATA(pBus->papBridgesR3[iBridge]->Int.s.CTX_SUFF(pDevIns), PDEVPCIBUS);
    22872258            ich9pciBusInfo(pBusSub, pHlp, iIndent + 1, fRegisters);
    22882259        }
    … …  
    22992270static DECLCALLBACK(void) ich9pciInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
    23002271{
    2301     PICH9PCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
     2272    PDEVPCIBUS pBus = DEVINS_2_DEVPCIBUS(pDevIns);
    23022273
    23032274    if (pszArgs == NULL || !strcmp(pszArgs, "basic"))
    … …  
    23592330     * Init data.
    23602331     */
    2361     PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
    2362     PICH9PCIBUS     pBus     = &pGlobals->PciBus;
     2332    PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
     2333    PDEVPCIBUS     pBus     = &pGlobals->PciBus;
    23632334    /* Zero out everything */
    23642335    memset(pGlobals, 0, sizeof(*pGlobals));
    … …  
    25632534static DECLCALLBACK(void) ich9pciReset(PPDMDEVINS pDevIns)
    25642535{
    2565     PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
    2566     PICH9PCIBUS     pBus     = &pGlobals->PciBus;
     2536    PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
     2537    PDEVPCIBUS     pBus     = &pGlobals->PciBus;
    25672538
    25682539    /* PCI-specific reset for each device. */
    … …  
    25972568static DECLCALLBACK(void) ich9pciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
    25982569{
    2599     PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
    2600     PICH9PCIBUS     pBus     = &pGlobals->PciBus;
     2570    PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
     2571    PDEVPCIBUS     pBus     = &pGlobals->PciBus;
    26012572    pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
    26022573
    … …  
    26432614     * Init data and register the PCI bus.
    26442615     */
    2645     PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
     2616    PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
    26462617    pBus->fTypePiix3  = false;
    26472618    pBus->fTypeIch9   = true;
    … …  
    27412712static void ich9pcibridgeReset(PPDMDEVINS pDevIns)
    27422713{
    2743     PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
     2714    PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
    27442715
    27452716    /* Reset config space to default values. */
    … …  
    27622733static DECLCALLBACK(void) ich9pcibridgeRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
    27632734{
    2764     PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
     2735    PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
    27652736    pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
    27662737
    … …  
    27922763    1,
    27932764    /* cbInstance */
    2794     sizeof(ICH9PCIGLOBALS),
     2765    sizeof(DEVPCIROOT),
    27952766    /* pfnConstruct */
    27962767    ich9pciConstruct,
    … …  
    28822853
    28832854#endif /* IN_RING3 */
    2884 #endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
     2855

  • trunk/src/VBox/Devices/Bus/DevPciInternal.h

    r64419 r64420  
    162162
    163163
     164/** Converts a PCI bus device instance pointer to a DEVPCIBUS pointer. */
     165#define DEVINS_2_DEVPCIBUS(pDevIns)     (&PDMINS_2_DATA(pDevIns, PDEVPCIROOT)->PciBus)
     166/** Converts a pointer to a PCI bus instance to a DEVPCIROOT pointer. */
     167#define DEVPCIBUS_2_DEVPCIROOT(pPciBus) RT_FROM_MEMBER(pPciBus, DEVPCIROOT, PciBus)
     168
     169/** @def PCI_LOCK
     170 * Acquires the PDM lock. This is a NOP if locking is disabled. */
     171/** @def PCI_UNLOCK
     172 * Releases the PDM lock. This is a NOP if locking is disabled. */
     173#define PCI_LOCK(pDevIns, rc) \
     174    do { \
     175        int rc2 = DEVINS_2_DEVPCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
     176        if (rc2 != VINF_SUCCESS) \
     177            return rc2; \
     178    } while (0)
     179#define PCI_UNLOCK(pDevIns) \
     180    DEVINS_2_DEVPCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
     181
     182
    164183#endif
    165184

  • trunk/src/VBox/Devices/Bus/DevPciMerge1.cpp.h

    r64414 r64420  
    221221                                             uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName)
    222222{
    223     PDEVPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
     223    PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
     224    AssertCompileMemberOffset(DEVPCIROOT, PciBus, 0);
    224225    return pciR3MergedRegisterDeviceOnBus(pBus, pPciDev, fFlags, uPciDevNo, uPciFunNo, pszName,
    225226                                          pciR3UnmergedConfigReadDev, pciR3UnmergedConfigWriteDev);
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