Changeset 64456 in vbox for trunk/src/VBox
- Timestamp:
- Oct 28, 2016 1:03:24 PM (8 years ago)
- Location:
- trunk/src/VBox/Devices/Bus
- Files:
-
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/Bus/DevPCI.cpp
r64452 r64456 205 205 206 206 207 static DECLCALLBACK(uint32_t) pci_default_read_config(PPDMDEVINS pDevIns, PDMPCIDEV *d, uint32_t address, unsigned len)208 {209 NOREF(pDevIns);210 uint32_t val;211 switch(len) {212 case 1:213 val = d->abConfig[address];214 break;215 case 2:216 val = RT_LE2H_U16(*(uint16_t *)(d->abConfig + address));217 break;218 default:219 case 4:220 val = RT_LE2H_U32(*(uint32_t *)(d->abConfig + address));221 break;222 }223 return val;224 }225 226 207 static DECLCALLBACK(void) pci_default_write_config(PPDMDEVINS pDevIns, PDMPCIDEV *d, uint32_t address, uint32_t val, unsigned len) 227 208 { … … 1105 1086 * as a possible file #2 contains external code if there's any left. 1106 1087 */ 1107 # define pciR3UnmergedConfigReadDev pci_default_read_config1108 1088 # define pciR3UnmergedConfigWriteDev pci_default_write_config 1109 1089 # include "DevPciMerge1.cpp.h" -
trunk/src/VBox/Devices/Bus/DevPciIch9.cpp
r64454 r64456 81 81 static void ich9pcibridgeReset(PPDMDEVINS pDevIns); 82 82 static void ich9pciUpdateMappings(PDMPCIDEV *pDev); 83 static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t u32Address, unsigned len);84 83 static DECLCALLBACK(void) ich9pciConfigWriteDev(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t u32Address, uint32_t val, unsigned len); 85 84 DECLINLINE(PPDMPCIDEV) ich9pciFindBridge(PDEVPCIBUS pBus, uint8_t iBus); … … 684 683 * as a possible file #2 contains external code if there's any left. 685 684 */ 686 # define pciR3UnmergedConfigReadDev ich9pciConfigReadDev687 685 # define pciR3UnmergedConfigWriteDev ich9pciConfigWriteDev 688 686 # include "DevPciMerge1.cpp.h" … … 1887 1885 * @callback_method_impl{PFNPCICONFIGREAD, Default config space read callback.} 1888 1886 */ 1889 static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress, unsigned cb)1887 DECLCALLBACK(uint32_t) devpciR3CommonDefaultConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress, unsigned cb) 1890 1888 { 1891 1889 NOREF(pDevIns); … … 1914 1912 if ( pciDevIsMsiCapable(pPciDev) 1915 1913 && uAddress - (uint32_t)pPciDev->Int.s.u8MsiCapOffset < (uint32_t)pPciDev->Int.s.u8MsiCapSize ) 1916 Log2((" ich9pciConfigReadDev: MSI CAP: %#x LB %u -> %#x\n", uAddress - (uint32_t)pPciDev->Int.s.u8MsiCapOffset, cb, uValue));1914 Log2(("devpciR3CommonDefaultConfigRead: MSI CAP: %#x LB %u -> %#x\n", uAddress - (uint32_t)pPciDev->Int.s.u8MsiCapOffset, cb, uValue)); 1917 1915 else if ( pciDevIsMsixCapable(pPciDev) 1918 1916 && uAddress - (uint32_t)pPciDev->Int.s.u8MsixCapOffset < (uint32_t)pPciDev->Int.s.u8MsixCapSize) 1919 Log2((" ich9pciConfigReadDev: MSI-X CAP: %#x LB %u -> %#x\n", uAddress - (uint32_t)pPciDev->Int.s.u8MsiCapOffset, cb, uValue));1917 Log2(("devpciR3CommonDefaultConfigRead: MSI-X CAP: %#x LB %u -> %#x\n", uAddress - (uint32_t)pPciDev->Int.s.u8MsiCapOffset, cb, uValue)); 1920 1918 #endif 1921 1919 } … … 1978 1976 1979 1977 /** 1980 * Configuration space write callback (PCIDEVICEINT::pfnConfigWrite)1981 * for connected devices.1978 * @callback_method_impl{PFNPCICONFIGWRITE, 1979 * Default config space write callback.} 1982 1980 * 1983 1981 * See paragraph 7.5 of PCI Express specification (p. 349) for … … 1985 1983 */ 1986 1984 static DECLCALLBACK(void) ich9pciConfigWriteDev(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, 1987 uint32_t u 32Address, uint32_t val, unsigned len)1985 uint32_t uAddress, uint32_t u32Value, unsigned cb) 1988 1986 { 1989 1987 NOREF(pDevIns); 1990 Assert( len<= 4);1991 1992 if ((u 32Address + len) > 256 && (u32Address + len) < 4096)1988 Assert(cb <= 4); 1989 1990 if ((uAddress + cb) > 256 && (uAddress + cb) < 4096) 1993 1991 { 1994 1992 LogRel(("PCI: %8s/%u: Write to extended register %d fallen back to generic code\n", 1995 pPciDev->pszNameR3, pPciDev->Int.s.CTX_SUFF(pDevIns)->iInstance, u 32Address));1993 pPciDev->pszNameR3, pPciDev->Int.s.CTX_SUFF(pDevIns)->iInstance, uAddress)); 1996 1994 return; 1997 1995 } 1998 1996 1999 AssertMsgReturnVoid(u 32Address + len<= 256, ("Write after end of PCI config space\n"));1997 AssertMsgReturnVoid(uAddress + cb <= 256, ("Write after end of PCI config space\n")); 2000 1998 2001 1999 if ( pciDevIsMsiCapable(pPciDev) 2002 && (u 32Address >= pPciDev->Int.s.u8MsiCapOffset)2003 && (u 32Address < (unsigned)(pPciDev->Int.s.u8MsiCapOffset + pPciDev->Int.s.u8MsiCapSize))2000 && (uAddress >= pPciDev->Int.s.u8MsiCapOffset) 2001 && (uAddress < (unsigned)(pPciDev->Int.s.u8MsiCapOffset + pPciDev->Int.s.u8MsiCapSize)) 2004 2002 ) 2005 2003 { 2006 2004 MsiPciConfigWrite(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), 2007 2005 pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp), 2008 pPciDev, u 32Address, val, len);2006 pPciDev, uAddress, u32Value, cb); 2009 2007 return; 2010 2008 } 2011 2009 2012 2010 if ( pciDevIsMsixCapable(pPciDev) 2013 && (u 32Address >= pPciDev->Int.s.u8MsixCapOffset)2014 && (u 32Address < (unsigned)(pPciDev->Int.s.u8MsixCapOffset + pPciDev->Int.s.u8MsixCapSize))2011 && (uAddress >= pPciDev->Int.s.u8MsixCapOffset) 2012 && (uAddress < (unsigned)(pPciDev->Int.s.u8MsixCapOffset + pPciDev->Int.s.u8MsixCapSize)) 2015 2013 ) 2016 2014 { 2017 2015 MsixPciConfigWrite(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), 2018 2016 pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp), 2019 pPciDev, u 32Address, val, len);2017 pPciDev, uAddress, u32Value, cb); 2020 2018 return; 2021 2019 } 2022 2020 2023 uint32_t addr = u32Address;2024 2021 bool fUpdateMappings = false; 2025 bool fP2PBridge = false; 2026 /*bool fPassthrough = pciDevIsPassthrough(pPciDev);*/ 2027 uint8_t u8HeaderType = ich9pciGetByte(pPciDev, VBOX_PCI_HEADER_TYPE); 2028 2029 for (uint32_t i = 0; i < len; i++) 2022 bool fP2PBridge = false; 2023 uint8_t bHeaderType = ich9pciGetByte(pPciDev, VBOX_PCI_HEADER_TYPE); 2024 while (cb-- > 0) 2030 2025 { 2031 2026 bool fWritable = false; 2032 bool fRom = false; 2033 switch (u8HeaderType) 2027 switch (bHeaderType) 2034 2028 { 2035 2029 case 0x00: /* normal device */ 2036 2030 case 0x80: /* multi-function device */ 2037 switch ( addr)2031 switch (uAddress) 2038 2032 { 2039 2033 /* Read-only registers */ 2040 case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1: 2041 case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1: 2034 case VBOX_PCI_VENDOR_ID: 2035 case VBOX_PCI_VENDOR_ID+1: 2036 case VBOX_PCI_DEVICE_ID: 2037 case VBOX_PCI_DEVICE_ID+1: 2042 2038 case VBOX_PCI_REVISION_ID: 2043 2039 case VBOX_PCI_CLASS_PROG: … … 2045 2041 case VBOX_PCI_CLASS_BASE: 2046 2042 case VBOX_PCI_HEADER_TYPE: 2047 case VBOX_PCI_SUBSYSTEM_VENDOR_ID: case VBOX_PCI_SUBSYSTEM_VENDOR_ID+1: 2048 case VBOX_PCI_SUBSYSTEM_ID: case VBOX_PCI_SUBSYSTEM_ID+1: 2049 case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS+1: case VBOX_PCI_ROM_ADDRESS+2: case VBOX_PCI_ROM_ADDRESS+3: 2043 case VBOX_PCI_SUBSYSTEM_VENDOR_ID: 2044 case VBOX_PCI_SUBSYSTEM_VENDOR_ID+1: 2045 case VBOX_PCI_SUBSYSTEM_ID: 2046 case VBOX_PCI_SUBSYSTEM_ID+1: 2047 case VBOX_PCI_ROM_ADDRESS: 2048 case VBOX_PCI_ROM_ADDRESS+1: 2049 case VBOX_PCI_ROM_ADDRESS+2: 2050 case VBOX_PCI_ROM_ADDRESS+3: 2050 2051 case VBOX_PCI_CAPABILITY_LIST: 2051 2052 case VBOX_PCI_INTERRUPT_PIN: … … 2060 2061 case 0x01: /* PCI-PCI bridge */ 2061 2062 fP2PBridge = true; 2062 switch ( addr)2063 switch (uAddress) 2063 2064 { 2064 2065 /* Read-only registers */ 2065 case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1: 2066 case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1: 2066 case VBOX_PCI_VENDOR_ID: 2067 case VBOX_PCI_VENDOR_ID+1: 2068 case VBOX_PCI_DEVICE_ID: 2069 case VBOX_PCI_DEVICE_ID+1: 2067 2070 case VBOX_PCI_REVISION_ID: 2068 2071 case VBOX_PCI_CLASS_PROG: … … 2070 2073 case VBOX_PCI_CLASS_BASE: 2071 2074 case VBOX_PCI_HEADER_TYPE: 2072 case VBOX_PCI_ROM_ADDRESS_BR: case VBOX_PCI_ROM_ADDRESS_BR+1: case VBOX_PCI_ROM_ADDRESS_BR+2: case VBOX_PCI_ROM_ADDRESS_BR+3: 2075 case VBOX_PCI_ROM_ADDRESS_BR: 2076 case VBOX_PCI_ROM_ADDRESS_BR+1: 2077 case VBOX_PCI_ROM_ADDRESS_BR+2: 2078 case VBOX_PCI_ROM_ADDRESS_BR+3: 2073 2079 case VBOX_PCI_INTERRUPT_PIN: 2074 2080 fWritable = false; … … 2085 2091 } 2086 2092 2087 uint8_t u8Val = (uint8_t)val; 2088 switch (addr) 2093 bool fRom = false; 2094 uint8_t bVal = (uint8_t)u32Value; 2095 switch (uAddress) 2089 2096 { 2090 2097 case VBOX_PCI_COMMAND: /* Command register, bits 0-7. */ 2091 2098 fUpdateMappings = true; 2092 goto default_case;2099 goto l_default_case; 2093 2100 case VBOX_PCI_COMMAND+1: /* Command register, bits 8-15. */ 2094 2101 /* don't change reserved bits (11-15) */ 2095 u8Val &= ~UINT32_C(0xf8);2102 bVal &= ~UINT32_C(0xf8); 2096 2103 fUpdateMappings = true; 2097 goto default_case;2104 goto l_default_case; 2098 2105 case VBOX_PCI_STATUS: /* Status register, bits 0-7. */ 2099 2106 /* don't change read-only bits => actually all lower bits are read-only */ 2100 u8Val &= ~UINT32_C(0xff);2107 bVal &= ~UINT32_C(0xff); 2101 2108 /* status register, low part: clear bits by writing a '1' to the corresponding bit */ 2102 pPciDev->abConfig[ addr] &= ~u8Val;2109 pPciDev->abConfig[uAddress] &= ~bVal; 2103 2110 break; 2104 2111 case VBOX_PCI_STATUS+1: /* Status register, bits 8-15. */ 2105 2112 /* don't change read-only bits */ 2106 u8Val &= ~UINT32_C(0x06);2113 bVal &= ~UINT32_C(0x06); 2107 2114 /* status register, high part: clear bits by writing a '1' to the corresponding bit */ 2108 pPciDev->abConfig[ addr] &= ~u8Val;2115 pPciDev->abConfig[uAddress] &= ~bVal; 2109 2116 break; 2110 2117 case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS +1: case VBOX_PCI_ROM_ADDRESS +2: case VBOX_PCI_ROM_ADDRESS +3: … … 2116 2123 case VBOX_PCI_BASE_ADDRESS_4: case VBOX_PCI_BASE_ADDRESS_4+1: case VBOX_PCI_BASE_ADDRESS_4+2: case VBOX_PCI_BASE_ADDRESS_4+3: 2117 2124 case VBOX_PCI_BASE_ADDRESS_5: case VBOX_PCI_BASE_ADDRESS_5+1: case VBOX_PCI_BASE_ADDRESS_5+2: case VBOX_PCI_BASE_ADDRESS_5+3: 2118 {2119 2125 /* We check that, as same PCI register numbers as BARs may mean different registers for bridges */ 2120 if (fP2PBridge) 2121 goto default_case; 2122 else 2126 if (!fP2PBridge) 2123 2127 { 2124 int iRegion = fRom ? VBOX_PCI_ROM_SLOT : (addr - VBOX_PCI_BASE_ADDRESS_0) >> 2; 2125 int iOffset = addr & 0x3; 2126 ich9pciWriteBarByte(pPciDev, iRegion, iOffset, u8Val); 2128 2129 uint32_t iRegion = fRom ? VBOX_PCI_ROM_SLOT : (uAddress - VBOX_PCI_BASE_ADDRESS_0) >> 2; 2130 uint32_t off = uAddress & 0x3; 2131 ich9pciWriteBarByte(pPciDev, iRegion, off, bVal); 2127 2132 fUpdateMappings = true; 2133 break; 2128 2134 } 2135 /* fall thru (bridge) */ 2136 default: 2137 l_default_case: 2138 if (fWritable) 2139 PCIDevSetByte(pPciDev, uAddress, bVal); 2129 2140 break; 2130 } 2131 default: 2132 default_case: 2133 if (fWritable) 2134 PCIDevSetByte(pPciDev, addr, u8Val); 2135 } 2136 addr++; 2137 val >>= 8; 2141 } 2142 uAddress++; 2143 u32Value >>= 8; 2138 2144 } 2139 2145 -
trunk/src/VBox/Devices/Bus/DevPciInternal.h
r64452 r64456 190 190 PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld, 191 191 PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld); 192 DECLCALLBACK(uint32_t) devpciR3CommonDefaultConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress, unsigned cb); 192 193 void devpciR3CommonRestoreConfig(PPDMPCIDEV pDev, uint8_t const *pbSrcConfig, bool fIsBridge); 193 194 -
trunk/src/VBox/Devices/Bus/DevPciMerge1.cpp.h
r64423 r64456 224 224 AssertCompileMemberOffset(DEVPCIROOT, PciBus, 0); 225 225 return pciR3MergedRegisterDeviceOnBus(pBus, pPciDev, fFlags, uPciDevNo, uPciFunNo, pszName, 226 pciR3UnmergedConfigReadDev, pciR3UnmergedConfigWriteDev);226 devpciR3CommonDefaultConfigRead, pciR3UnmergedConfigWriteDev); 227 227 } 228 228 … … 236 236 PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS); 237 237 return pciR3MergedRegisterDeviceOnBus(pBus, pPciDev, fFlags, uPciDevNo, uPciFunNo, pszName, 238 pciR3UnmergedConfigReadDev, pciR3UnmergedConfigWriteDev);239 } 240 238 devpciR3CommonDefaultConfigRead, pciR3UnmergedConfigWriteDev); 239 } 240
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