Changeset 64463 in vbox

Timestamp:

Oct 28, 2016 2:21:03 PM (8 years ago)

Author:

vboxsync

Message:

DevPci: Cleaning up ich9pciConfigWriteDev.

File:

• trunk/src/VBox/Devices/Bus/DevPciIch9.cpp (modified) (4 diffs)

trunk/src/VBox/Devices/Bus/DevPciIch9.cpp

@@ -1930 +1930 @@
 
 
-DECLINLINE(void) ich9pciWriteBarByte(PPDMPCIDEV pPciDev, uint32_t iRegion, uint32_t off, uint8_t bVal)
+/**
+ * Worker for devpciR3CommonDefaultConfigWrite that write a byte to a BAR.
+ *
+ * @param   pPciDev             The PCI device.
+ * @param   iRegion             The region.
+ * @param   off                 The BAR offset.
+ * @param   bVal                The byte to write.
+ */
+DECLINLINE(void) devpciR3WriteBarByte(PPDMPCIDEV pPciDev, uint32_t iRegion, uint32_t off, uint8_t bVal)
 {
     PCIIORegion *pRegion = &pPciDev->Int.s.aIORegions[iRegion];
-    Log3(("ich9pciWriteBarByte: region=%d off=%d val=%#x size=%#llx\n", iRegion, off, bVal, pRegion->size));
+    Log3(("devpciR3WriteBarByte: region=%d off=%d val=%#x size=%#llx\n", iRegion, off, bVal, pRegion->size));
     Assert(off <= 3);
 
@@ -1960 +1968 @@
         bVal = (bOld & bMask) | (bVal & ~bMask);
 
-        Log3(("ich9pciWriteBarByte: %x changed to  %x\n", bOld, bVal));
+        Log3(("devpciR3WriteBarByte: %x changed to  %x\n", bOld, bVal));
 
         PCIDevSetByte(pPciDev, uAddr, bVal);
+    }
+}
+
+
+/**
+ * Checks if the given configuration byte is writable.
+ *
+ * @returns true if writable, false if not
+ * @param   uAddress            The config space byte byte.
+ * @param   bHeaderType         The device header byte.
+ */
+DECLINLINE(bool) devpciR3IsConfigByteWritable(uint32_t uAddress, uint8_t bHeaderType)
+{
+    switch (bHeaderType)
+    {
+        case 0x00: /* normal device */
+        case 0x80: /* multi-function device */
+            switch (uAddress)
+            {
+                /* Read-only registers. */
+                case VBOX_PCI_VENDOR_ID:
+                case VBOX_PCI_VENDOR_ID+1:
+                case VBOX_PCI_DEVICE_ID:
+                case VBOX_PCI_DEVICE_ID+1:
+                case VBOX_PCI_REVISION_ID:
+                case VBOX_PCI_CLASS_PROG:
+                case VBOX_PCI_CLASS_SUB:
+                case VBOX_PCI_CLASS_BASE:
+                case VBOX_PCI_HEADER_TYPE:
+                case VBOX_PCI_SUBSYSTEM_VENDOR_ID:
+                case VBOX_PCI_SUBSYSTEM_VENDOR_ID+1:
+                case VBOX_PCI_SUBSYSTEM_ID:
+                case VBOX_PCI_SUBSYSTEM_ID+1:
+                case VBOX_PCI_ROM_ADDRESS:
+                case VBOX_PCI_ROM_ADDRESS+1:
+                case VBOX_PCI_ROM_ADDRESS+2:
+                case VBOX_PCI_ROM_ADDRESS+3:
+                case VBOX_PCI_CAPABILITY_LIST:
+                case VBOX_PCI_INTERRUPT_PIN:
+                    return false;
+                /* Other registers can be written. */
+                default:
+                    return true;
+            }
+            break;
+        case 0x01: /* PCI-PCI bridge */
+            switch (uAddress)
+            {
+                /* Read-only registers. */
+                case VBOX_PCI_VENDOR_ID:
+                case VBOX_PCI_VENDOR_ID+1:
+                case VBOX_PCI_DEVICE_ID:
+                case VBOX_PCI_DEVICE_ID+1:
+                case VBOX_PCI_REVISION_ID:
+                case VBOX_PCI_CLASS_PROG:
+                case VBOX_PCI_CLASS_SUB:
+                case VBOX_PCI_CLASS_BASE:
+                case VBOX_PCI_HEADER_TYPE:
+                case VBOX_PCI_ROM_ADDRESS_BR:
+                case VBOX_PCI_ROM_ADDRESS_BR+1:
+                case VBOX_PCI_ROM_ADDRESS_BR+2:
+                case VBOX_PCI_ROM_ADDRESS_BR+3:
+                case VBOX_PCI_INTERRUPT_PIN:
+                    return false;
+                /* Other registers can be written. */
+                default:
+                    return true;
+            }
+            break;
+        default:
+            AssertMsgFailed(("Unknown header type %#x\n", bHeaderType));
+            return false;
     }
 }
@@ -2004 +2084 @@
              *       try emulate that.
              */
-            bool     fUpdateMappings = false;
-            bool     fP2PBridge      = false;
-            uint8_t  bHeaderType     = ich9pciGetByte(pPciDev, VBOX_PCI_HEADER_TYPE);
+            uint8_t const   bHeaderType     = ich9pciGetByte(pPciDev, VBOX_PCI_HEADER_TYPE);
+            bool const      fP2PBridge      = bHeaderType == 0x01; /* PCI-PCI bridge */
+            bool            fUpdateMappings = false;
             while (cb-- > 0)
             {
-                /*
-                 * Check writability first.
-                 */
-                bool fWritable = false;
-                switch (bHeaderType)
-                {
-                    case 0x00: /* normal device */
-                    case 0x80: /* multi-function device */
-                        switch (uAddress)
-                        {
-                            /* Read-only registers. */
-                            case VBOX_PCI_VENDOR_ID:
-                            case VBOX_PCI_VENDOR_ID+1:
-                            case VBOX_PCI_DEVICE_ID:
-                            case VBOX_PCI_DEVICE_ID+1:
-                            case VBOX_PCI_REVISION_ID:
-                            case VBOX_PCI_CLASS_PROG:
-                            case VBOX_PCI_CLASS_SUB:
-                            case VBOX_PCI_CLASS_BASE:
-                            case VBOX_PCI_HEADER_TYPE:
-                            case VBOX_PCI_SUBSYSTEM_VENDOR_ID:
-                            case VBOX_PCI_SUBSYSTEM_VENDOR_ID+1:
-                            case VBOX_PCI_SUBSYSTEM_ID:
-                            case VBOX_PCI_SUBSYSTEM_ID+1:
-                            case VBOX_PCI_ROM_ADDRESS:
-                            case VBOX_PCI_ROM_ADDRESS+1:
-                            case VBOX_PCI_ROM_ADDRESS+2:
-                            case VBOX_PCI_ROM_ADDRESS+3:
-                            case VBOX_PCI_CAPABILITY_LIST:
-                            case VBOX_PCI_INTERRUPT_PIN:
-                                fWritable = false;
-                                break;
-                            /* Other registers can be written. */
-                            default:
-                                fWritable = true;
-                                break;
-                        }
-                        break;
-                    case 0x01: /* PCI-PCI bridge */
-                        fP2PBridge = true;
-                        switch (uAddress)
-                        {
-                            /* Read-only registers. */
-                            case VBOX_PCI_VENDOR_ID:
-                            case VBOX_PCI_VENDOR_ID+1:
-                            case VBOX_PCI_DEVICE_ID:
-                            case VBOX_PCI_DEVICE_ID+1:
-                            case VBOX_PCI_REVISION_ID:
-                            case VBOX_PCI_CLASS_PROG:
-                            case VBOX_PCI_CLASS_SUB:
-                            case VBOX_PCI_CLASS_BASE:
-                            case VBOX_PCI_HEADER_TYPE:
-                            case VBOX_PCI_ROM_ADDRESS_BR:
-                            case VBOX_PCI_ROM_ADDRESS_BR+1:
-                            case VBOX_PCI_ROM_ADDRESS_BR+2:
-                            case VBOX_PCI_ROM_ADDRESS_BR+3:
-                            case VBOX_PCI_INTERRUPT_PIN:
-                                fWritable = false;
-                                break;
-                            /* Other registers can be written. */
-                            default:
-                                fWritable = true;
-                                break;
-                        }
-                        break;
-                    default:
-                        AssertMsgFailed(("Unknown header type %#x\n", bHeaderType));
-                        fWritable = false;
-                        break;
-                }
-
+                bool    fWritable = devpciR3IsConfigByteWritable(uAddress, bHeaderType);
+                uint8_t bVal = (uint8_t)u32Value;
                 bool    fRom = false;
-                uint8_t bVal = (uint8_t)u32Value;
                 switch (uAddress)
                 {
@@ -2128 +2138 @@
                         {
                             uint32_t iRegion = fRom ? VBOX_PCI_ROM_SLOT : (uAddress - VBOX_PCI_BASE_ADDRESS_0) >> 2;
-                            ich9pciWriteBarByte(pPciDev, iRegion, uAddress & 0x3, bVal);
+                            devpciR3WriteBarByte(pPciDev, iRegion, uAddress & 0x3, bVal);
                             fUpdateMappings = true;
                             break;