Changeset 64468 in vbox for trunk/src/VBox/Devices
- Timestamp:
- Oct 28, 2016 3:20:05 PM (8 years ago)
- File:
-
- 1 edited
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- Added
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trunk/src/VBox/Devices/Bus/DevPCI.cpp
r64462 r64468 105 105 #define PCI_MAX_LAT 0x3f /* 8 bits */ 106 106 107 108 #ifdef IN_RING3109 110 #if 0111 static void pci_update_mappings(PDMPCIDEV *d)112 {113 PDEVPCIBUS pBus = d->Int.s.CTX_SUFF(pBus);114 PCIIORegion *r;115 int cmd, i;116 uint32_t last_addr, new_addr, config_ofs;117 118 cmd = RT_LE2H_U16(*(uint16_t *)(d->abConfig + PCI_COMMAND));119 for(i = 0; i < PCI_NUM_REGIONS; i++) {120 r = &d->Int.s.aIORegions[i];121 if (i == PCI_ROM_SLOT) {122 config_ofs = 0x30;123 } else {124 config_ofs = 0x10 + i * 4;125 }126 if (r->size != 0) {127 if (r->type & PCI_ADDRESS_SPACE_IO) {128 if (cmd & PCI_COMMAND_IO) {129 new_addr = RT_LE2H_U32(*(uint32_t *)(d->abConfig +130 config_ofs));131 new_addr = new_addr & ~(r->size - 1);132 last_addr = new_addr + r->size - 1;133 /* NOTE: we have only 64K ioports on PC */134 if (last_addr <= new_addr || new_addr == 0 ||135 last_addr >= 0x10000) {136 new_addr = ~0U;137 }138 } else {139 new_addr = ~0U;140 }141 } else {142 if (cmd & PCI_COMMAND_MEMORY) {143 new_addr = RT_LE2H_U32(*(uint32_t *)(d->abConfig +144 config_ofs));145 /* the ROM slot has a specific enable bit */146 if (i == PCI_ROM_SLOT && !(new_addr & 1))147 goto no_mem_map;148 new_addr = new_addr & ~(r->size - 1);149 last_addr = new_addr + r->size - 1;150 /* NOTE: we do not support wrapping */151 /* XXX: as we cannot support really dynamic152 mappings, we handle specific values as invalid153 mappings. */154 /* Unconditionally exclude I/O-APIC/HPET/ROM. Pessimistic, but better than causing a mess. */155 if (last_addr <= new_addr || new_addr == 0 ||156 (new_addr <= ~0U && last_addr >= 0xfec00000U)) {157 new_addr = ~0U;158 }159 } else {160 no_mem_map:161 new_addr = ~0U;162 }163 }164 //LogRel(("PCI: config dev %u/%u BAR%i uOld=%#018llx uNew=%#018llx size=%llu\n", d->uDevFn >> 3, d->uDevFn & 7, i, r->addr, new_addr, r->size));165 /* now do the real mapping */166 if (new_addr != r->addr) {167 if (r->addr != ~0U) {168 if (r->type & PCI_ADDRESS_SPACE_IO) {169 int devclass;170 /* NOTE: specific hack for IDE in PC case:171 only one byte must be mapped. */172 devclass = d->abConfig[0x0a] | (d->abConfig[0x0b] << 8);173 if (devclass == 0x0101 && r->size == 4) {174 int rc = PDMDevHlpIOPortDeregister(d->Int.s.CTX_SUFF(pDevIns), r->addr + 2, 1);175 AssertRC(rc);176 } else {177 int rc = PDMDevHlpIOPortDeregister(d->Int.s.CTX_SUFF(pDevIns), r->addr, r->size);178 AssertRC(rc);179 }180 } else {181 RTGCPHYS GCPhysBase = r->addr;182 int rc;183 if (pBus->pPciHlpR3->pfnIsMMIOExBase(pBus->pDevInsR3, d->Int.s.CTX_SUFF(pDevIns), GCPhysBase))184 {185 /* unmap it. */186 rc = r->map_func(d->Int.s.pDevInsR3, d, i, NIL_RTGCPHYS, r->size, (PCIADDRESSSPACE)(r->type));187 AssertRC(rc);188 rc = PDMDevHlpMMIOExUnmap(d->Int.s.CTX_SUFF(pDevIns), d, i, GCPhysBase);189 }190 else191 rc = PDMDevHlpMMIODeregister(d->Int.s.CTX_SUFF(pDevIns), GCPhysBase, r->size);192 AssertMsgRC(rc, ("rc=%Rrc d=%s i=%d GCPhysBase=%RGp size=%#x\n", rc, d->pszNameR3, i, GCPhysBase, r->size));193 }194 }195 r->addr = new_addr;196 if (r->addr != ~0U) {197 int rc = r->map_func(d->Int.s.pDevInsR3, d, i,198 r->addr + (r->type & PCI_ADDRESS_SPACE_IO ? 0 : 0),199 r->size, (PCIADDRESSSPACE)(r->type));200 AssertRC(rc);201 }202 }203 }204 }205 }206 #endif207 208 #endif /* IN_RING3 */209 107 210 108 static int pci_data_write(PDEVPCIROOT pGlobals, uint32_t addr, uint32_t val, int len)
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