VirtualBox

Changeset 64472 in vbox for trunk


Ignore:
Timestamp:
Oct 28, 2016 3:29:59 PM (8 years ago)
Author:
vboxsync
Message:

DevPci: Cleaning up (fake) pci bios init.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/Devices/Bus/DevPciIch9.cpp

    r64471 r64472  
    684684 *       as a possible file #2 contains external code if there's any left.
    685685 */
    686 # define pciR3UnmergedConfigWriteDev ich9pciConfigWriteDev
    687686# include "DevPciMerge1.cpp.h"
    688687
    … …  
    987986    return u32Value;
    988987}
     988
     989
     990
     991/* -=-=-=-=-=- Saved State -=-=-=-=-=- */
    989992
    990993
    … …  
    13471350
    13481351
     1352
     1353/* -=-=-=-=-=- Fake PCI BIOS Init -=-=-=-=-=- */
     1354
     1355
    13491356/*
    13501357 * Perform imeediate read of configuration space register.
    13511358 * Cannot be rescheduled, as already in R3.
    13521359 */
    1353 static uint32_t ich9pciConfigRead(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t len)
     1360static uint32_t ich9pciBiosInitReadConfig(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t len)
    13541361{
    13551362    PciAddress aPciAddr;
    … …  
    13701377 * Cannot be rescheduled, as already in R3.
    13711378 */
    1372 static void ich9pciConfigWrite(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val, uint32_t len)
     1379static void ich9pciBiosInitWriteConfig(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val, uint32_t len)
    13731380{
    13741381    PciAddress aPciAddr;
    … …  
    13821389
    13831390
    1384 static void ich9pciSetRegionAddress(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn, int iRegion, uint64_t addr)
     1391static void ich9pciBiosInitSetRegionAddress(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn, int iRegion, uint64_t addr)
    13851392{
    13861393    uint32_t uReg = ich9pciGetRegionReg(iRegion);
    13871394
    13881395    /* Read memory type first. */
    1389     uint8_t uResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, uReg, 1);
     1396    uint8_t uResourceType = ich9pciBiosInitReadConfig(pGlobals, uBus, uDevFn, uReg, 1);
    13901397    bool    f64Bit =    (uResourceType & ((uint8_t)(PCI_ADDRESS_SPACE_BAR64 | PCI_ADDRESS_SPACE_IO)))
    13911398                     == PCI_ADDRESS_SPACE_BAR64;
    … …  
    13951402
    13961403    /* Write address of the device. */
    1397     ich9pciConfigWrite(pGlobals, uBus, uDevFn, uReg, (uint32_t)addr, 4);
     1404    ich9pciBiosInitWriteConfig(pGlobals, uBus, uDevFn, uReg, (uint32_t)addr, 4);
    13981405    if (f64Bit)
    1399         ich9pciConfigWrite(pGlobals, uBus, uDevFn, uReg + 4, (uint32_t)(addr >> 32), 4);
     1406        ich9pciBiosInitWriteConfig(pGlobals, uBus, uDevFn, uReg + 4, (uint32_t)(addr >> 32), 4);
    14001407}
    14011408
    … …  
    14151422        Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosIo));
    14161423    }
    1417     ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0, 1);
     1424    ich9pciBiosInitWriteConfig(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0, 1);
    14181425
    14191426    /* The MMIO range for the bridge must be aligned to a 1MB boundary. */
    … …  
    14231430        Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosMmio));
    14241431    }
    1425     ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0), 2);
     1432    ich9pciBiosInitWriteConfig(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0), 2);
    14261433
    14271434    /* Save values to compare later to. */
    14281435    uint32_t u32IoAddressBase = pGlobals->uPciBiosIo;
    14291436    uint32_t u32MMIOAddressBase = pGlobals->uPciBiosMmio;
    1430     uint8_t uBridgeBus = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, 1);
     1437    uint8_t uBridgeBus = ich9pciBiosInitReadConfig(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, 1);
    14311438
    14321439    /* Init devices behind the bridge and possibly other bridges as well. */
    … …  
    14461453    }
    14471454
    1448     ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1, 1);
     1455    ich9pciBiosInitWriteConfig(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1, 1);
    14491456
    14501457    /* Same with the MMIO limit register but with 1MB boundary here. */
    … …  
    14541461        pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
    14551462    }
    1456     ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1, 2);
     1463    ich9pciBiosInitWriteConfig(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1, 2);
    14571464
    14581465    /*
    … …  
    14611468     * the base register than in the limit register.
    14621469     */
    1463     ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0, 2);
    1464     ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0, 2);
    1465     ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00, 4);
    1466     ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00, 4);
     1470    ich9pciBiosInitWriteConfig(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0, 2);
     1471    ich9pciBiosInitWriteConfig(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0, 2);
     1472    ich9pciBiosInitWriteConfig(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00, 4);
     1473    ich9pciBiosInitWriteConfig(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00, 4);
    14671474}
    14681475
    … …  
    14721479    uint8_t uCmd;
    14731480
    1474     uDevClass  = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_CLASS_DEVICE, 2);
    1475     uVendor    = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_VENDOR_ID, 2);
    1476     uDevice    = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_DEVICE_ID, 2);
     1481    uDevClass  = ich9pciBiosInitReadConfig(pGlobals, uBus, uDevFn, VBOX_PCI_CLASS_DEVICE, 2);
     1482    uVendor    = ich9pciBiosInitReadConfig(pGlobals, uBus, uDevFn, VBOX_PCI_VENDOR_ID, 2);
     1483    uDevice    = ich9pciBiosInitReadConfig(pGlobals, uBus, uDevFn, VBOX_PCI_DEVICE_ID, 2);
    14771484
    14781485    /* If device is present */
    … …  
    14861493        case 0x0101:
    14871494            /* IDE controller */
    1488             ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x40, 0x8000, 2); /* enable IDE0 */
    1489             ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x42, 0x8000, 2); /* enable IDE1 */
     1495            ich9pciBiosInitWriteConfig(pGlobals, uBus, uDevFn, 0x40, 0x8000, 2); /* enable IDE0 */
     1496            ich9pciBiosInitWriteConfig(pGlobals, uBus, uDevFn, 0x42, 0x8000, 2); /* enable IDE1 */
    14901497            goto default_map;
    14911498            break;
    … …  
    15021509             * ich9pciSetRegionAddress, so don't forget to enable I/O decoding.
    15031510             */
    1504             uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 1);
    1505             ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND,
    1506                                uCmd | PCI_COMMAND_IOACCESS,
    1507                                1);
     1511            uCmd = ich9pciBiosInitReadConfig(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 1);
     1512            ich9pciBiosInitWriteConfig(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND,
     1513                                       uCmd | PCI_COMMAND_IOACCESS,
     1514                                       1);
    15081515            goto default_map;
    15091516            break;
    … …  
    15281535                /* Calculate size - we write all 1s into the BAR, and then evaluate which bits
    15291536                   are cleared. */
    1530                 uint8_t u8ResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 1);
     1537                uint8_t u8ResourceType = ich9pciBiosInitReadConfig(pGlobals, uBus, uDevFn, u32Address, 1);
    15311538
    15321539                bool f64Bit =    (u8ResourceType & ((uint8_t)(PCI_ADDRESS_SPACE_BAR64 | PCI_ADDRESS_SPACE_IO)))
    … …  
    15371544                if (f64Bit)
    15381545                {
    1539                     ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address,   UINT32_C(0xffffffff), 4);
    1540                     ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address+4, UINT32_C(0xffffffff), 4);
    1541                     cbRegSize64  =            ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address,   4);
    1542                     cbRegSize64 |= ((uint64_t)ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address+4, 4) << 32);
     1546                    ich9pciBiosInitWriteConfig(pGlobals, uBus, uDevFn, u32Address,   UINT32_C(0xffffffff), 4);
     1547                    ich9pciBiosInitWriteConfig(pGlobals, uBus, uDevFn, u32Address+4, UINT32_C(0xffffffff), 4);
     1548                    cbRegSize64  =            ich9pciBiosInitReadConfig(pGlobals, uBus, uDevFn, u32Address,   4);
     1549                    cbRegSize64 |= ((uint64_t)ich9pciBiosInitReadConfig(pGlobals, uBus, uDevFn, u32Address+4, 4) << 32);
    15431550                    cbRegSize64 &= ~UINT64_C(0x0f);
    15441551                    cbRegSize64 = (~cbRegSize64) + 1;
    … …  
    15521559                {
    15531560                    uint32_t cbRegSize32;
    1554                     ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
    1555                     cbRegSize32 = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 4);
     1561                    ich9pciBiosInitWriteConfig(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
     1562                    cbRegSize32 = ich9pciBiosInitReadConfig(pGlobals, uBus, uDevFn, u32Address, 4);
    15561563
    15571564                    /* Clear resource information depending on resource type. */
    … …  
    15961603                            uNew = (uNew + cbRegSize64 - 1) & ~(cbRegSize64 - 1);
    15971604                            LogFunc(("Start address of 64-bit MMIO region %u/%u is %#llx\n", iRegion, iRegion + 1, uNew));
    1598                             ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, iRegion, uNew);
     1605                            ich9pciBiosInitSetRegionAddress(pGlobals, uBus, uDevFn, iRegion, uNew);
    15991606                            fActiveMemRegion = true;
    16001607                            pGlobals->uPciBiosMmio64 = uNew + cbRegSize64;
    … …  
    16061613                                    iRegion, uBus, uDevFn >> 3, uDevFn & 7, uVendor, uDevice)); /** @todo make this a VM start failure later. */
    16071614                            /* Undo the mapping mess caused by the size probing. */
    1608                             ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0), 4);
     1615                            ich9pciBiosInitWriteConfig(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0), 4);
    16091616                        }
    16101617                    }
    … …  
    16121619                    {
    16131620                        LogFunc(("Start address of %s region %u is %#x\n", (fIsPio ? "I/O" : "MMIO"), iRegion, uNew));
    1614                         ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, iRegion, uNew);
     1621                        ich9pciBiosInitSetRegionAddress(pGlobals, uBus, uDevFn, iRegion, uNew);
    16151622                        if (fIsPio)
    16161623                            fActiveIORegion = true;
    … …  
    16271634
    16281635            /* Update the command word appropriately. */
    1629             uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 2);
     1636            uCmd = ich9pciBiosInitReadConfig(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 2);
    16301637            if (fActiveMemRegion)
    16311638                uCmd |= PCI_COMMAND_MEMACCESS; /* Enable MMIO access. */
    16321639            if (fActiveIORegion)
    16331640                uCmd |= PCI_COMMAND_IOACCESS; /* Enable I/O space access. */
    1634             ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, uCmd, 2);
     1641            ich9pciBiosInitWriteConfig(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, uCmd, 2);
    16351642            break;
    16361643        }
    … …  
    16381645
    16391646    /* map the interrupt */
    1640     uint32_t iPin = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_PIN, 1);
     1647    uint32_t iPin = ich9pciBiosInitReadConfig(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_PIN, 1);
    16411648    if (iPin != 0)
    16421649    {
    … …  
    16771684        Log(("Using pin %d and IRQ %d for device %02x:%02x.%d\n",
    16781685             iPin, iIrq, uBus, uDevFn>>3, uDevFn&7));
    1679         ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_LINE, iIrq, 1);
     1686        ich9pciBiosInitWriteConfig(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_LINE, iIrq, 1);
    16801687    }
    16811688}
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