Index: trunk/src/VBox/Devices/Bus/DevPciIch9.cpp
===================================================================
--- trunk/src/VBox/Devices/Bus/DevPciIch9.cpp	(revision 64471)
+++ trunk/src/VBox/Devices/Bus/DevPciIch9.cpp	(revision 64472)
@@ -684,5 +684,4 @@
  *       as a possible file #2 contains external code if there's any left.
  */
-# define pciR3UnmergedConfigWriteDev ich9pciConfigWriteDev
 # include "DevPciMerge1.cpp.h"
 
@@ -987,4 +986,8 @@
     return u32Value;
 }
+
+
+
+/* -=-=-=-=-=- Saved State -=-=-=-=-=- */
 
 
@@ -1347,9 +1350,13 @@
 
 
+
+/* -=-=-=-=-=- Fake PCI BIOS Init -=-=-=-=-=- */
+
+
 /*
  * Perform imeediate read of configuration space register.
  * Cannot be rescheduled, as already in R3.
  */
-static uint32_t ich9pciConfigRead(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t len)
+static uint32_t ich9pciBiosInitReadConfig(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t len)
 {
     PciAddress aPciAddr;
@@ -1370,5 +1377,5 @@
  * Cannot be rescheduled, as already in R3.
  */
-static void ich9pciConfigWrite(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val, uint32_t len)
+static void ich9pciBiosInitWriteConfig(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val, uint32_t len)
 {
     PciAddress aPciAddr;
@@ -1382,10 +1389,10 @@
 
 
-static void ich9pciSetRegionAddress(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn, int iRegion, uint64_t addr)
+static void ich9pciBiosInitSetRegionAddress(PDEVPCIROOT pGlobals, uint8_t uBus, uint8_t uDevFn, int iRegion, uint64_t addr)
 {
     uint32_t uReg = ich9pciGetRegionReg(iRegion);
 
     /* Read memory type first. */
-    uint8_t uResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, uReg, 1);
+    uint8_t uResourceType = ich9pciBiosInitReadConfig(pGlobals, uBus, uDevFn, uReg, 1);
     bool    f64Bit =    (uResourceType & ((uint8_t)(PCI_ADDRESS_SPACE_BAR64 | PCI_ADDRESS_SPACE_IO)))
                      == PCI_ADDRESS_SPACE_BAR64;
@@ -1395,7 +1402,7 @@
 
     /* Write address of the device. */
-    ich9pciConfigWrite(pGlobals, uBus, uDevFn, uReg, (uint32_t)addr, 4);
+    ich9pciBiosInitWriteConfig(pGlobals, uBus, uDevFn, uReg, (uint32_t)addr, 4);
     if (f64Bit)
-        ich9pciConfigWrite(pGlobals, uBus, uDevFn, uReg + 4, (uint32_t)(addr >> 32), 4);
+        ich9pciBiosInitWriteConfig(pGlobals, uBus, uDevFn, uReg + 4, (uint32_t)(addr >> 32), 4);
 }
 
@@ -1415,5 +1422,5 @@
         Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosIo));
     }
-    ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0, 1);
+    ich9pciBiosInitWriteConfig(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0, 1);
 
     /* The MMIO range for the bridge must be aligned to a 1MB boundary. */
@@ -1423,10 +1430,10 @@
         Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosMmio));
     }
-    ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0), 2);
+    ich9pciBiosInitWriteConfig(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0), 2);
 
     /* Save values to compare later to. */
     uint32_t u32IoAddressBase = pGlobals->uPciBiosIo;
     uint32_t u32MMIOAddressBase = pGlobals->uPciBiosMmio;
-    uint8_t uBridgeBus = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, 1);
+    uint8_t uBridgeBus = ich9pciBiosInitReadConfig(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, 1);
 
     /* Init devices behind the bridge and possibly other bridges as well. */
@@ -1446,5 +1453,5 @@
     }
 
-    ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1, 1);
+    ich9pciBiosInitWriteConfig(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1, 1);
 
     /* Same with the MMIO limit register but with 1MB boundary here. */
@@ -1454,5 +1461,5 @@
         pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
     }
-    ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1, 2);
+    ich9pciBiosInitWriteConfig(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1, 2);
 
     /*
@@ -1461,8 +1468,8 @@
      * the base register than in the limit register.
      */
-    ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0, 2);
-    ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0, 2);
-    ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00, 4);
-    ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00, 4);
+    ich9pciBiosInitWriteConfig(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0, 2);
+    ich9pciBiosInitWriteConfig(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0, 2);
+    ich9pciBiosInitWriteConfig(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00, 4);
+    ich9pciBiosInitWriteConfig(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00, 4);
 }
 
@@ -1472,7 +1479,7 @@
     uint8_t uCmd;
 
-    uDevClass  = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_CLASS_DEVICE, 2);
-    uVendor    = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_VENDOR_ID, 2);
-    uDevice    = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_DEVICE_ID, 2);
+    uDevClass  = ich9pciBiosInitReadConfig(pGlobals, uBus, uDevFn, VBOX_PCI_CLASS_DEVICE, 2);
+    uVendor    = ich9pciBiosInitReadConfig(pGlobals, uBus, uDevFn, VBOX_PCI_VENDOR_ID, 2);
+    uDevice    = ich9pciBiosInitReadConfig(pGlobals, uBus, uDevFn, VBOX_PCI_DEVICE_ID, 2);
 
     /* If device is present */
@@ -1486,6 +1493,6 @@
         case 0x0101:
             /* IDE controller */
-            ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x40, 0x8000, 2); /* enable IDE0 */
-            ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x42, 0x8000, 2); /* enable IDE1 */
+            ich9pciBiosInitWriteConfig(pGlobals, uBus, uDevFn, 0x40, 0x8000, 2); /* enable IDE0 */
+            ich9pciBiosInitWriteConfig(pGlobals, uBus, uDevFn, 0x42, 0x8000, 2); /* enable IDE1 */
             goto default_map;
             break;
@@ -1502,8 +1509,8 @@
              * ich9pciSetRegionAddress, so don't forget to enable I/O decoding.
              */
-            uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 1);
-            ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND,
-                               uCmd | PCI_COMMAND_IOACCESS,
-                               1);
+            uCmd = ich9pciBiosInitReadConfig(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 1);
+            ich9pciBiosInitWriteConfig(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND,
+                                       uCmd | PCI_COMMAND_IOACCESS,
+                                       1);
             goto default_map;
             break;
@@ -1528,5 +1535,5 @@
                 /* Calculate size - we write all 1s into the BAR, and then evaluate which bits
                    are cleared. */
-                uint8_t u8ResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 1);
+                uint8_t u8ResourceType = ich9pciBiosInitReadConfig(pGlobals, uBus, uDevFn, u32Address, 1);
 
                 bool f64Bit =    (u8ResourceType & ((uint8_t)(PCI_ADDRESS_SPACE_BAR64 | PCI_ADDRESS_SPACE_IO)))
@@ -1537,8 +1544,8 @@
                 if (f64Bit)
                 {
-                    ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address,   UINT32_C(0xffffffff), 4);
-                    ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address+4, UINT32_C(0xffffffff), 4);
-                    cbRegSize64  =            ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address,   4);
-                    cbRegSize64 |= ((uint64_t)ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address+4, 4) << 32);
+                    ich9pciBiosInitWriteConfig(pGlobals, uBus, uDevFn, u32Address,   UINT32_C(0xffffffff), 4);
+                    ich9pciBiosInitWriteConfig(pGlobals, uBus, uDevFn, u32Address+4, UINT32_C(0xffffffff), 4);
+                    cbRegSize64  =            ich9pciBiosInitReadConfig(pGlobals, uBus, uDevFn, u32Address,   4);
+                    cbRegSize64 |= ((uint64_t)ich9pciBiosInitReadConfig(pGlobals, uBus, uDevFn, u32Address+4, 4) << 32);
                     cbRegSize64 &= ~UINT64_C(0x0f);
                     cbRegSize64 = (~cbRegSize64) + 1;
@@ -1552,6 +1559,6 @@
                 {
                     uint32_t cbRegSize32;
-                    ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
-                    cbRegSize32 = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 4);
+                    ich9pciBiosInitWriteConfig(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
+                    cbRegSize32 = ich9pciBiosInitReadConfig(pGlobals, uBus, uDevFn, u32Address, 4);
 
                     /* Clear resource information depending on resource type. */
@@ -1596,5 +1603,5 @@
                             uNew = (uNew + cbRegSize64 - 1) & ~(cbRegSize64 - 1);
                             LogFunc(("Start address of 64-bit MMIO region %u/%u is %#llx\n", iRegion, iRegion + 1, uNew));
-                            ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, iRegion, uNew);
+                            ich9pciBiosInitSetRegionAddress(pGlobals, uBus, uDevFn, iRegion, uNew);
                             fActiveMemRegion = true;
                             pGlobals->uPciBiosMmio64 = uNew + cbRegSize64;
@@ -1606,5 +1613,5 @@
                                     iRegion, uBus, uDevFn >> 3, uDevFn & 7, uVendor, uDevice)); /** @todo make this a VM start failure later. */
                             /* Undo the mapping mess caused by the size probing. */
-                            ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0), 4);
+                            ich9pciBiosInitWriteConfig(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0), 4);
                         }
                     }
@@ -1612,5 +1619,5 @@
                     {
                         LogFunc(("Start address of %s region %u is %#x\n", (fIsPio ? "I/O" : "MMIO"), iRegion, uNew));
-                        ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, iRegion, uNew);
+                        ich9pciBiosInitSetRegionAddress(pGlobals, uBus, uDevFn, iRegion, uNew);
                         if (fIsPio)
                             fActiveIORegion = true;
@@ -1627,10 +1634,10 @@
 
             /* Update the command word appropriately. */
-            uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 2);
+            uCmd = ich9pciBiosInitReadConfig(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 2);
             if (fActiveMemRegion)
                 uCmd |= PCI_COMMAND_MEMACCESS; /* Enable MMIO access. */
             if (fActiveIORegion)
                 uCmd |= PCI_COMMAND_IOACCESS; /* Enable I/O space access. */
-            ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, uCmd, 2);
+            ich9pciBiosInitWriteConfig(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, uCmd, 2);
             break;
         }
@@ -1638,5 +1645,5 @@
 
     /* map the interrupt */
-    uint32_t iPin = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_PIN, 1);
+    uint32_t iPin = ich9pciBiosInitReadConfig(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_PIN, 1);
     if (iPin != 0)
     {
@@ -1677,5 +1684,5 @@
         Log(("Using pin %d and IRQ %d for device %02x:%02x.%d\n",
              iPin, iIrq, uBus, uDevFn>>3, uDevFn&7));
-        ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_LINE, iIrq, 1);
+        ich9pciBiosInitWriteConfig(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_LINE, iIrq, 1);
     }
 }
