Changeset 64476 in vbox for trunk/src/VBox

Timestamp:

Oct 28, 2016 3:40:12 PM (8 years ago)

Author:

vboxsync

Message:

DevPci: Cleaning up (fake) pci bios init.

File:

• trunk/src/VBox/Devices/Bus/DevPciIch9.cpp (modified) (6 diffs)

trunk/src/VBox/Devices/Bus/DevPciIch9.cpp

@@ -1697 +1697 @@
  * @param   uBusSecondary    The secondary bus number, i.e. the bus number behind the bridge.
  */
-static void ich9pciInitBridgeTopology(PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus, unsigned uBusPrimary,
-                                      unsigned uBusSecondary)
+static void ich9pciBiosInitBridgeTopology(PDEVPCIROOT pPciRoot, PDEVPCIBUS pBus, unsigned uBusPrimary, unsigned uBusSecondary)
 {
     PPDMPCIDEV pBridgeDev = &pBus->PciDev;
@@ -1716 +1715 @@
         PDEVPCIBUS pChildBus = PDMINS_2_DATA(pBridge->Int.s.CTX_SUFF(pDevIns), PDEVPCIBUS);
         pPciRoot->uPciBiosBus++;
-        ich9pciInitBridgeTopology(pPciRoot, pChildBus, uBusSecondary, pPciRoot->uPciBiosBus);
+        ich9pciBiosInitBridgeTopology(pPciRoot, pChildBus, uBusSecondary, pPciRoot->uPciBiosBus);
     }
     PCIDevSetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS, pPciRoot->uPciBiosBus);
-    Log2(("ich9pciInitBridgeTopology: for bus %p: primary=%d secondary=%d subordinate=%d\n",
+    Log2(("ich9pciBiosInitBridgeTopology: for bus %p: primary=%d secondary=%d subordinate=%d\n",
           pBus,
           PDMPciDevGetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS),
@@ -1728 +1727 @@
 
 
+/**
+ * @interface_method_impl{PDMPCIBUSREG,pfnFakePCIBIOSR3}
+ */
 static DECLCALLBACK(int) ich9pciFakePCIBIOS(PPDMDEVINS pDevIns)
 {
-    PDEVPCIROOT pPciRoot   = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
+    PDEVPCIROOT     pPciRoot   = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
     PVM             pVM        = PDMDevHlpGetVM(pDevIns);
     uint32_t const  cbBelow4GB = MMR3PhysGetRamSizeBelow4GB(pVM);
@@ -1743 +1745 @@
     pPciRoot->uPciBiosMmio64 = cbAbove4GB + _4G;
 
-    /* NB: Assume that if MMIO range is enabled, it is at the bottom of the memory hole. */
+    /* NB: Assume that if PCI controller MMIO range is enabled, it is at the bottom of the memory hole. */
     if (pPciRoot->u64PciConfigMMioAddress)
     {
@@ -1749 +1751 @@
         pPciRoot->uPciBiosMmio = pPciRoot->u64PciConfigMMioAddress + pPciRoot->u64PciConfigMMioLength;
     }
-    Log(("cbBelow4GB: %lX, uPciBiosMmio: %lX, cbAbove4GB: %llX\n", cbBelow4GB, pPciRoot->uPciBiosMmio, cbAbove4GB));
+    Log(("cbBelow4GB: %#RX32, uPciBiosMmio: %#RX64, cbAbove4GB: %#RX64, uPciBiosMmio64=%#RX64\n",
+         cbBelow4GB, pPciRoot->uPciBiosMmio, cbAbove4GB, pPciRoot->uPciBiosMmio64));
 
     /*
@@ -1755 +1758 @@
      */
     PDEVPCIBUS pBus = &pPciRoot->PciBus;
-    ich9pciInitBridgeTopology(pPciRoot, pBus, 0, 0);
+    ich9pciBiosInitBridgeTopology(pPciRoot, pBus, 0, 0);
 
     /*
      * Init the devices.
      */
-    for (int i = 0; i < 256; i++)
+    for (uint32_t i = 0; i < 256; i++)
         ich9pciBiosInitDevice(pPciRoot, 0, i);