VirtualBox

Changeset 64655 in vbox for trunk/src/VBox


Ignore:
Timestamp:
Nov 14, 2016 10:46:07 AM (8 years ago)
Author:
vboxsync
Message:

VMM,recompiler: Get rid of PDM APIC interfaces reducing one level of indirection, cleaned up some unused stuff in recompiler.

Location:
trunk/src/VBox/VMM
Files:
22 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/VMMAll/APICAll.cpp

    r64596 r64655  
    228228        /* 7 */     { "write reserved bits of MSR",    "",                            VINF_CPUM_R3_MSR_WRITE },
    229229        /* 8 */     { "write an invalid value to MSR", "",                            VINF_CPUM_R3_MSR_WRITE },
    230         /* 9 */     { "write MSR",                     "disallowed by configuration", VINF_CPUM_R3_MSR_WRITE }
     230        /* 9 */     { "write MSR",                     "disallowed by configuration", VINF_CPUM_R3_MSR_WRITE },
     231        /* 10 */    { "read MSR",                      "disallowed by configuration", VINF_CPUM_R3_MSR_READ }
    231232    };
    232233    AssertCompile(RT_ELEMENTS(s_aAccess) == APICMSRACCESS_COUNT);
    … …  
    18581859
    18591860/**
    1860  * @interface_method_impl{PDMAPICREG,pfnReadMsrR3}
    1861  */
    1862 APICBOTHCBDECL(VBOXSTRICTRC) apicReadMsr(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint32_t u32Reg, uint64_t *pu64Value)
     1861 * Reads an APIC MSR.
     1862 *
     1863 * @returns Strict VBox status code.
     1864 * @param   pVCpu           The cross context virtual CPU structure.
     1865 * @param   u32Reg          The MSR being read.
     1866 * @param   pu64Value       Where to store the read value.
     1867 */
     1868VMM_INT_DECL(VBOXSTRICTRC) APICReadMsr(PVMCPU pVCpu, uint32_t u32Reg, uint64_t *pu64Value)
    18631869{
    18641870    /*
    … …  
    18681874    Assert(u32Reg >= MSR_IA32_X2APIC_ID && u32Reg <= MSR_IA32_X2APIC_SELF_IPI);
    18691875    Assert(pu64Value);
    1870     RT_NOREF_PV(pDevIns);
    1871 
     1876
     1877    /*
     1878     * Is the APIC enabled?
     1879     */
    18721880    PCAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
     1881    if (apicIsEnabled(pVCpu))
     1882    { /* likely */ }
     1883    else
     1884    {
     1885        return apicMsrAccessError(pVCpu, u32Reg, pApic->enmMaxMode == PDMAPICMODE_NONE ?
     1886                                                 APICMSRACCESS_READ_DISALLOWED_CONFIG : APICMSRACCESS_READ_RSVD_OR_UNKNOWN);
     1887    }
     1888
    18731889#ifndef IN_RING3
    18741890    if (pApic->fRZEnabled)
    … …  
    19621978
    19631979/**
    1964  * @interface_method_impl{PDMAPICREG,pfnWriteMsrR3}
    1965  */
    1966 APICBOTHCBDECL(VBOXSTRICTRC) apicWriteMsr(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint32_t u32Reg, uint64_t u64Value)
     1980 * Writes an APIC MSR.
     1981 *
     1982 * @returns Strict VBox status code.
     1983 * @param   pVCpu           The cross context virtual CPU structure.
     1984 * @param   u32Reg          The MSR being written.
     1985 * @param   pu64Value       The value to write.
     1986 */
     1987VMM_INT_DECL(VBOXSTRICTRC) APICWriteMsr(PVMCPU pVCpu, uint32_t u32Reg, uint64_t u64Value)
    19671988{
    19681989    /*
    … …  
    19711992    VMCPU_ASSERT_EMT(pVCpu);
    19721993    Assert(u32Reg >= MSR_IA32_X2APIC_ID && u32Reg <= MSR_IA32_X2APIC_SELF_IPI);
    1973     RT_NOREF_PV(pDevIns);
    1974 
     1994
     1995    /*
     1996     * Is the APIC enabled?
     1997     */
    19751998    PCAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
     1999    if (apicIsEnabled(pVCpu))
     2000    { /* likely */ }
     2001    else
     2002    {
     2003        return apicMsrAccessError(pVCpu, u32Reg, pApic->enmMaxMode == PDMAPICMODE_NONE ?
     2004                                                 APICMSRACCESS_WRITE_DISALLOWED_CONFIG : APICMSRACCESS_WRITE_RSVD_OR_UNKNOWN);
     2005    }
     2006
    19762007#ifndef IN_RING3
    19772008    if (pApic->fRZEnabled)
    … …  
    21232154
    21242155/**
    2125  * @interface_method_impl{PDMAPICREG,pfnSetBaseMsrR3}
    2126  */
    2127 APICBOTHCBDECL(VBOXSTRICTRC) apicSetBaseMsr(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint64_t u64BaseMsr)
     2156 * Sets the APIC base MSR.
     2157 *
     2158 * @returns Strict VBox status code.
     2159 * @param   pVCpu       The cross context virtual CPU structure.
     2160 * @param   u64BaseMsr  The value to set.
     2161 */
     2162VMM_INT_DECL(VBOXSTRICTRC) APICSetBaseMsr(PVMCPU pVCpu, uint64_t u64BaseMsr)
    21282163{
    21292164    Assert(pVCpu);
    2130     NOREF(pDevIns);
    21312165
    21322166#ifdef IN_RING3
    … …  
    22552289
    22562290#else  /* !IN_RING3 */
    2257     RT_NOREF_PV(pDevIns);
    22582291    RT_NOREF_PV(pVCpu);
    22592292    RT_NOREF_PV(u64BaseMsr);
    … …  
    22642297
    22652298/**
    2266  * @interface_method_impl{PDMAPICREG,pfnGetBaseMsrR3}
    2267  */
    2268 APICBOTHCBDECL(uint64_t) apicGetBaseMsr(PPDMDEVINS pDevIns, PVMCPU pVCpu)
    2269 {
    2270     RT_NOREF_PV(pDevIns);
     2299 * Gets the APIC base MSR (no checks are performed wrt APIC hardware or its
     2300 * state).
     2301 *
     2302 * @returns The base MSR value.
     2303 * @param   pVCpu       The cross context virtual CPU structure.
     2304 */
     2305VMM_INT_DECL(uint64_t) APICGetBaseMsrNoCheck(PVMCPU pVCpu)
     2306{
    22712307    VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
    2272 
    22732308    PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
    22742309    return pApicCpu->uApicBaseMsr;
    … …  
    22772312
    22782313/**
    2279  * @interface_method_impl{PDMAPICREG,pfnSetTprR3}
    2280  */
    2281 APICBOTHCBDECL(void) apicSetTpr(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint8_t u8Tpr)
    2282 {
    2283     RT_NOREF_PV(pDevIns);
    2284     apicSetTprEx(pVCpu, u8Tpr, false /* fForceX2ApicBehaviour */);
     2314 * Gets the APIC base MSR.
     2315 *
     2316 * @returns Strict VBox status code.
     2317 * @param   pVCpu       The cross context virtual CPU structure.
     2318 * @param   pu64Value   Where to store the MSR value.
     2319 */
     2320VMM_INT_DECL(VBOXSTRICTRC) APICGetBaseMsr(PVMCPU pVCpu, uint64_t *pu64Value)
     2321{
     2322    VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
     2323
     2324    PCAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
     2325    if (pApic->enmMaxMode != PDMAPICMODE_NONE)
     2326    {
     2327        *pu64Value = APICGetBaseMsrNoCheck(pVCpu);
     2328        return VINF_SUCCESS;
     2329    }
     2330
     2331#ifdef IN_RING3
     2332    LogRelMax(5, ("APIC%u: Reading APIC base MSR (%#x) when there is no APIC -> #GP(0)\n", pVCpu->idCpu, MSR_IA32_APICBASE));
     2333    return VERR_CPUM_RAISE_GP_0;
     2334#else
     2335    return VINF_CPUM_R3_MSR_WRITE;
     2336#endif
     2337}
     2338
     2339
     2340/**
     2341 * Sets the TPR (Task Priority Register).
     2342 *
     2343 * @returns VBox status code.
     2344 * @param   pVCpu       The cross context virtual CPU structure.
     2345 * @param   u8Tpr       The TPR value to set.
     2346 */
     2347VMMDECL(int) APICSetTpr(PVMCPU pVCpu, uint8_t u8Tpr)
     2348{
     2349    if (apicIsEnabled(pVCpu))
     2350        return VBOXSTRICTRC_VAL(apicSetTprEx(pVCpu, u8Tpr, false /* fForceX2ApicBehaviour */));
     2351    return VERR_PDM_NO_APIC_INSTANCE;
    22852352}
    22862353
    … …  
    23102377
    23112378/**
    2312  * @interface_method_impl{PDMAPICREG,pfnGetTprR3}
    2313  */
    2314 APICBOTHCBDECL(uint8_t) apicGetTpr(PPDMDEVINS pDevIns, PVMCPU pVCpu, bool *pfPending, uint8_t *pu8PendingIntr)
    2315 {
    2316     RT_NOREF_PV(pDevIns);
     2379 * Gets the APIC TPR (Task Priority Register).
     2380 *
     2381 * @returns VBox status code.
     2382 * @param   pVCpu           The cross context virtual CPU structure.
     2383 * @param   pu8Tpr          Where to store the TPR.
     2384 * @param   pfPending       Where to store whether there is a pending interrupt
     2385 *                          (optional, can be NULL).
     2386 * @param   pu8PendingIntr  Where to store the highest-priority pending
     2387 *                          interrupt (optional, can be NULL).
     2388 */
     2389VMMDECL(int) APICGetTpr(PVMCPU pVCpu, uint8_t *pu8Tpr, bool *pfPending, uint8_t *pu8PendingIntr)
     2390{
    23172391    VMCPU_ASSERT_EMT(pVCpu);
    2318     PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
    2319 
    2320     if (pfPending)
    2321     {
    2322         /*
    2323          * Just return whatever the highest pending interrupt is in the IRR.
    2324          * The caller is responsible for figuring out if it's masked by the TPR etc.
    2325          */
    2326         *pfPending = apicGetHighestPendingInterrupt(pVCpu, pu8PendingIntr);
    2327     }
    2328 
    2329     return pXApicPage->tpr.u8Tpr;
    2330 }
    2331 
    2332 
    2333 /**
    2334  * @interface_method_impl{PDMAPICREG,pfnGetTimerFreqR3}
    2335  */
    2336 APICBOTHCBDECL(uint64_t) apicGetTimerFreq(PPDMDEVINS pDevIns)
    2337 {
    2338     PVM      pVM      = PDMDevHlpGetVM(pDevIns);
    2339     PVMCPU   pVCpu    = &pVM->aCpus[0];
    2340     PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
    2341     uint64_t uTimer   = TMTimerGetFreq(pApicCpu->CTX_SUFF(pTimer));
    2342     return uTimer;
    2343 }
    2344 
    2345 
    2346 /**
    2347  * @interface_method_impl{PDMAPICREG,pfnBusDeliverR3}
    2348  * @remarks This is a private interface between the IOAPIC and the APIC.
    2349  */
    2350 APICBOTHCBDECL(int) apicBusDeliver(PPDMDEVINS pDevIns, uint8_t uDest, uint8_t uDestMode, uint8_t uDeliveryMode, uint8_t uVector,
    2351                             uint8_t uPolarity, uint8_t uTriggerMode, uint32_t uTagSrc)
     2392    if (apicIsEnabled(pVCpu))
     2393    {
     2394        PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
     2395        if (pfPending)
     2396        {
     2397            /*
     2398             * Just return whatever the highest pending interrupt is in the IRR.
     2399             * The caller is responsible for figuring out if it's masked by the TPR etc.
     2400             */
     2401            *pfPending = apicGetHighestPendingInterrupt(pVCpu, pu8PendingIntr);
     2402        }
     2403
     2404        *pu8Tpr = pXApicPage->tpr.u8Tpr;
     2405        return VINF_SUCCESS;
     2406    }
     2407
     2408    *pu8Tpr = 0;
     2409    return VERR_PDM_NO_APIC_INSTANCE;
     2410}
     2411
     2412
     2413/**
     2414 * Gets the APIC timer frequency.
     2415 *
     2416 * @returns Strict VBox status code.
     2417 * @param
     2418 */
     2419VMM_INT_DECL(int) APICGetTimerFreq(PVM pVM, uint64_t *pu64Value)
     2420{
     2421    /*
     2422     * Validate.
     2423     */
     2424    Assert(pVM);
     2425    AssertPtrReturn(pu64Value, VERR_INVALID_PARAMETER);
     2426
     2427    PVMCPU pVCpu = &pVM->aCpus[0];
     2428    if (apicIsEnabled(pVCpu))
     2429    {
     2430        PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
     2431        *pu64Value = TMTimerGetFreq(pApicCpu->CTX_SUFF(pTimer));
     2432        return VINF_SUCCESS;
     2433    }
     2434    return VERR_PDM_NO_APIC_INSTANCE;
     2435}
     2436
     2437
     2438/**
     2439 * Delivers an interrupt message via the system bus.
     2440 *
     2441 * @returns VBox status code.
     2442 * @param   pVM             The cross context VM structure.
     2443 * @param   uDest           The destination mask.
     2444 * @param   uDestMode       The destination mode.
     2445 * @param   uDeliveryMode   The delivery mode.
     2446 * @param   uVector         The interrupt vector.
     2447 * @param   uPolarity       The interrupt line polarity.
     2448 * @param   uTriggerMode    The trigger mode.
     2449 * @param   uTagSrc         The interrupt tag (debugging).
     2450 */
     2451VMM_INT_DECL(int) APICBusDeliver(PVM pVM, uint8_t uDest, uint8_t uDestMode, uint8_t uDeliveryMode, uint8_t uVector,
     2452                                 uint8_t uPolarity, uint8_t uTriggerMode, uint32_t uTagSrc)
    23522453{
    23532454    NOREF(uPolarity);
    23542455    NOREF(uTagSrc);
    2355     PVM pVM = PDMDevHlpGetVM(pDevIns);
     2456
     2457    /*
     2458     * If the APIC isn't enabled, do nothing and pretend success.
     2459     */
     2460    if (apicIsEnabled(&pVM->aCpus[0]))
     2461    { /* likely */ }
     2462    else
     2463        return VINF_SUCCESS;
    23562464
    23572465    /*
    … …  
    23822490
    23832491/**
    2384  * @interface_method_impl{PDMAPICREG,pfnLocalInterruptR3}
    2385  * @remarks This is a private interface between the PIC and the APIC.
    2386  */
    2387 APICBOTHCBDECL(VBOXSTRICTRC) apicLocalInterrupt(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint8_t u8Pin, uint8_t u8Level, int rcRZ)
    2388 {
    2389     NOREF(pDevIns);
     2492 * Assert/de-assert the local APIC's LINT0/LINT1 interrupt pins.
     2493 *
     2494 * @returns Strict VBox status code.
     2495 * @param   pVCpu       The cross context virtual CPU structure.
     2496 * @param   u8Pin       The interrupt pin (0 for LINT0 or 1 for LINT1).
     2497 * @param   u8Level     The level (0 for low or 1 for high).
     2498 * @param   rcRZ        The return code if the operation cannot be performed in
     2499 *                      the current context.
     2500 */
     2501VMM_INT_DECL(VBOXSTRICTRC) APICLocalInterrupt(PVMCPU pVCpu, uint8_t u8Pin, uint8_t u8Level, int rcRZ)
     2502{
    23902503    AssertReturn(u8Pin <= 1, VERR_INVALID_PARAMETER);
    23912504    AssertReturn(u8Level <= 1, VERR_INVALID_PARAMETER);
    … …  
    25442657
    25452658/**
    2546  * @interface_method_impl{PDMAPICREG,pfnGetInterruptR3}
    2547  */
    2548 APICBOTHCBDECL(int) apicGetInterrupt(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint8_t *pu8Vector, uint32_t *pu32TagSrc)
    2549 {
    2550     RT_NOREF_PV(pDevIns);
     2659 * Gets the next highest-priority interrupt from the APIC, marking it as an
     2660 * "in-service" interrupt.
     2661 *
     2662 * @returns VBox status code.
     2663 * @param   pVCpu       The cross context virtual CPU structure.
     2664 * @param   pu8Vector   Where to store the vector.
     2665 * @param   pu32TagSrc  The source tag (debugging).
     2666 */
     2667VMM_INT_DECL(int) APICGetInterrupt(PVMCPU pVCpu, uint8_t *pu8Vector, uint32_t *pu32TagSrc)
     2668{
    25512669    VMCPU_ASSERT_EMT(pVCpu);
    25522670    Assert(pu8Vector);
    … …  
    29053023 *          interrupt shadow etc.)
    29063024 */
    2907 VMMDECL(bool) APICQueueInterruptToService(PVMCPU pVCpu, uint8_t u8PendingIntr)
     3025VMM_INT_DECL(bool) APICQueueInterruptToService(PVMCPU pVCpu, uint8_t u8PendingIntr)
    29083026{
    29093027    VMCPU_ASSERT_EMT(pVCpu);
    … …  
    29373055 *                              in-service.
    29383056 */
    2939 VMMDECL(void) APICDequeueInterruptFromService(PVMCPU pVCpu, uint8_t u8PendingIntr)
     3057VMM_INT_DECL(void) APICDequeueInterruptFromService(PVMCPU pVCpu, uint8_t u8PendingIntr)
    29403058{
    29413059    VMCPU_ASSERT_EMT(pVCpu);
    … …  
    30443162 *                              interrupt is pending.
    30453163 */
    3046 VMMDECL(bool) APICGetHighestPendingInterrupt(PVMCPU pVCpu, uint8_t *pu8PendingIntr)
     3164VMM_INT_DECL(bool) APICGetHighestPendingInterrupt(PVMCPU pVCpu, uint8_t *pu8PendingIntr)
    30473165{
    30483166    VMCPU_ASSERT_EMT(pVCpu);

  • trunk/src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp

    r62606 r64655  
    2222#define LOG_GROUP LOG_GROUP_CPUM
    2323#include <VBox/vmm/cpum.h>
    24 #include <VBox/vmm/pdmapi.h>
     24#include <VBox/vmm/apic.h>
    2525#include <VBox/vmm/hm.h>
    2626#include <VBox/vmm/tm.h>
    … …  
    217217{
    218218    RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
    219     return PDMApicGetBaseMsr(pVCpu, puValue, false /* fIgnoreErrors */);
     219    return APICGetBaseMsr(pVCpu, puValue);
    220220}
    221221
    … …  
    225225{
    226226    RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
    227     return PDMApicSetBaseMsr(pVCpu, uValue);
     227    return APICSetBaseMsr(pVCpu, uValue);
    228228}
    229229
    … …  
    12151215{
    12161216    RT_NOREF_PV(pRange);
    1217     return PDMApicReadMsr(pVCpu, idMsr, puValue);
     1217    return APICReadMsr(pVCpu, idMsr, puValue);
    12181218}
    12191219
    … …  
    12231223{
    12241224    RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
    1225     return PDMApicWriteMsr(pVCpu, idMsr, uValue);
     1225    return APICWriteMsr(pVCpu, idMsr, uValue);
    12261226}
    12271227

  • trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp

    r62601 r64655  
    2424#include <VBox/vmm/patm.h>
    2525#include <VBox/vmm/dbgf.h>
    26 #include <VBox/vmm/pdm.h>
     26#include <VBox/vmm/apic.h>
    2727#include <VBox/vmm/pgm.h>
    2828#include <VBox/vmm/mm.h>
    … …  
    10591059        {
    10601060            uint8_t u8Tpr;
    1061             int rc = PDMApicGetTPR(pVCpu, &u8Tpr, NULL /* pfPending */, NULL /* pu8PendingIrq */);
     1061            int rc = APICGetTpr(pVCpu, &u8Tpr, NULL /* pfPending */, NULL /* pu8PendingIrq */);
    10621062            if (RT_FAILURE(rc))
    10631063            {
    … …  
    10661066                return rc;
    10671067            }
    1068             *pValue = u8Tpr >> 4; /* bits 7-4 contain the task priority that go in cr8, bits 3-0*/
     1068            *pValue = u8Tpr >> 4; /* bits 7-4 contain the task priority that go in cr8, bits 3-0 */
    10691069            break;
    10701070        }

  • trunk/src/VBox/VMM/VMMAll/EMAll.cpp

    r63560 r64655  
    32503250
    32513251    case DISCREG_CR8:
    3252         return PDMApicSetTPR(pVCpu, val << 4);  /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
     3252        return APICSetTpr(pVCpu, val << 4);  /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
    32533253
    32543254    default:

  • trunk/src/VBox/VMM/VMMAll/GIMAllHv.cpp

    r63651 r64655  
    560560        case MSR_GIM_HV_APIC_FREQ:
    561561        {
    562             int rc = PDMApicGetTimerFreq(pVM, puValue);
     562            int rc = APICGetTimerFreq(pVM, puValue);
    563563            if (RT_FAILURE(rc))
    564564                return VERR_CPUM_RAISE_GP_0;

  • trunk/src/VBox/VMM/VMMAll/IEMAll.cpp

    r64545 r64655  
    9696#include <VBox/vmm/iem.h>
    9797#include <VBox/vmm/cpum.h>
     98#include <VBox/vmm/apic.h>
    9899#include <VBox/vmm/pdm.h>
    99100#include <VBox/vmm/pgm.h>

  • trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp.h

    r64033 r64655  
    49584958        {
    49594959            uint8_t uTpr;
    4960             int rc = PDMApicGetTPR(pVCpu, &uTpr, NULL, NULL);
     4960            int rc = APICGetTpr(pVCpu, &uTpr, NULL, NULL);
    49614961            if (RT_SUCCESS(rc))
    49624962                crX = uTpr >> 4;
    … …  
    52715271
    52725272            if (!IEM_FULL_VERIFICATION_ENABLED(pVCpu))
    5273                 PDMApicSetTPR(pVCpu, (uint8_t)uNewCrX << 4);
     5273                APICSetTpr(pVCpu, (uint8_t)uNewCrX << 4);
    52745274            rcStrict = VINF_SUCCESS;
    52755275            break;

  • trunk/src/VBox/VMM/VMMAll/PDMAll.cpp

    r64626 r64655  
    6262    {
    6363        VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
    64         Assert(pVM->pdm.s.Apic.CTX_SUFF(pDevIns));
    65         Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnGetInterrupt));
    6664        uint32_t uTagSrc;
    6765        uint8_t  uVector;
    68         rc = pVM->pdm.s.Apic.CTX_SUFF(pfnGetInterrupt)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu, &uVector, &uTagSrc);
     66        rc = APICGetInterrupt(pVCpu, &uVector, &uTagSrc);
    6967        if (RT_SUCCESS(rc))
    7068        {
    … …  
    260258
    261259/**
    262  * Returns the presence of a Local APIC.
    263  *
    264  * @returns VBox true if a Local APIC is present.
    265  * @param   pVM         The cross context VM structure.
    266  */
    267 VMM_INT_DECL(bool) PDMHasApic(PVM pVM)
    268 {
    269     return pVM->pdm.s.Apic.CTX_SUFF(pDevIns) != NULL;
    270 }
    271 
    272 
    273 /**
    274  * Set the APIC base.
    275  *
    276  * @returns Strict VBox status code.
    277  * @param   pVCpu       The cross context virtual CPU structure.
    278  * @param   u64Base     The new base.
    279  */
    280 VMMDECL(VBOXSTRICTRC) PDMApicSetBaseMsr(PVMCPU pVCpu, uint64_t u64Base)
    281 {
    282     PVM pVM = pVCpu->CTX_SUFF(pVM);
    283     if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
    284     {
    285         Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnSetBaseMsr));
    286         VBOXSTRICTRC rcStrict = pVM->pdm.s.Apic.CTX_SUFF(pfnSetBaseMsr)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu, u64Base);
    287 
    288         /* Update CPUM's copy of the APIC base. */
    289         PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
    290         Assert(pCtx);
    291         pCtx->msrApicBase = pVM->pdm.s.Apic.CTX_SUFF(pfnGetBaseMsr)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu);
    292 
    293         return rcStrict;
    294     }
    295 
    296 #ifdef IN_RING3
    297     LogRelMax(5, ("PDM: APIC%U: Writing APIC base MSR (%#x) invalid since there isn't an APIC -> #GP(0)\n", pVCpu->idCpu,
    298                   MSR_IA32_APICBASE));
    299     return VERR_CPUM_RAISE_GP_0;
    300 #else
    301     return VINF_CPUM_R3_MSR_WRITE;
    302 #endif
    303 }
    304 
    305 
    306 /**
    307  * Get the APIC base MSR from the APIC device.
    308  *
    309  * @returns Strict VBox status code.
    310  * @param   pVCpu           The cross context virtual CPU structure.
    311  * @param   pu64Base        Where to store the APIC base.
    312  * @param   fIgnoreErrors   Whether to ignore errors (i.e. not a real guest MSR
    313  *                          access).
    314  */
    315 VMMDECL(VBOXSTRICTRC) PDMApicGetBaseMsr(PVMCPU pVCpu, uint64_t *pu64Base, bool fIgnoreErrors)
    316 {
    317     PVM pVM = pVCpu->CTX_SUFF(pVM);
    318     if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
    319     {
    320         Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnGetBaseMsr));
    321         VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
    322         *pu64Base = pVM->pdm.s.Apic.CTX_SUFF(pfnGetBaseMsr)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu);
    323         return VINF_SUCCESS;
    324     }
    325 
    326     *pu64Base = 0;
    327     if (fIgnoreErrors)
    328         return VINF_SUCCESS;
    329 
    330 #ifdef IN_RING3
    331     LogRelMax(5, ("PDM: APIC%u: Reading APIC base MSR (%#x) invalid without an APIC instance -> #GP(0)\n", pVCpu->idCpu,
    332                   MSR_IA32_APICBASE));
    333     return VERR_CPUM_RAISE_GP_0;
    334 #else
    335     return VINF_CPUM_R3_MSR_WRITE;
    336 #endif
    337 }
    338 
    339 
    340 /**
    341  * Set the TPR (Task Priority Register).
    342  *
    343  * @returns VBox status code.
    344  * @param   pVCpu           The cross context virtual CPU structure.
    345  * @param   u8TPR           The new TPR.
    346  */
    347 VMMDECL(int) PDMApicSetTPR(PVMCPU pVCpu, uint8_t u8TPR)
    348 {
    349     PVM pVM = pVCpu->CTX_SUFF(pVM);
    350     if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
    351     {
    352         Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnSetTpr));
    353         pVM->pdm.s.Apic.CTX_SUFF(pfnSetTpr)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu, u8TPR);
    354         return VINF_SUCCESS;
    355     }
    356     return VERR_PDM_NO_APIC_INSTANCE;
    357 }
    358 
    359 
    360 /**
    361  * Get the TPR (Task Priority Register).
    362  *
    363  * @returns VINF_SUCCESS or VERR_PDM_NO_APIC_INSTANCE.
    364  * @param   pVCpu           The cross context virtual CPU structure.
    365  * @param   pu8TPR          Where to store the TRP.
    366  * @param   pfPending       Where to store whether there is a pending interrupt
    367  *                          (out, optional).
    368  * @param   pu8PendingIntr  Where to store the highest-priority pending
    369  *                          interrupt (out, optional).
    370  *
    371  * @remarks No-long-jump zone!!!
    372  */
    373 VMMDECL(int) PDMApicGetTPR(PVMCPU pVCpu, uint8_t *pu8TPR, bool *pfPending, uint8_t *pu8PendingIntr)
    374 {
    375     PVM        pVM      = pVCpu->CTX_SUFF(pVM);
    376     PPDMDEVINS pApicIns = pVM->pdm.s.Apic.CTX_SUFF(pDevIns);
    377     if (pApicIns)
    378     {
    379         /*
    380          * Note! We don't acquire the PDM lock here as we're just reading
    381          *       information. Doing so causes massive contention as this
    382          *       function is called very often by each and every VCPU.
    383          */
    384         Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnGetTpr));
    385         *pu8TPR = pVM->pdm.s.Apic.CTX_SUFF(pfnGetTpr)(pApicIns, pVCpu, pfPending, pu8PendingIntr);
    386         return VINF_SUCCESS;
    387     }
    388     *pu8TPR = 0;
    389     return VERR_PDM_NO_APIC_INSTANCE;
    390 }
    391 
    392 
    393 /**
    394  * Write a MSR in APIC range.
    395  *
    396  * @returns Strict VBox status code.
    397  * @param   pVCpu           The cross context virtual CPU structure.
    398  * @param   u32Reg          MSR to write.
    399  * @param   u64Value        Value to write.
    400  */
    401 VMM_INT_DECL(VBOXSTRICTRC) PDMApicWriteMsr(PVMCPU pVCpu, uint32_t u32Reg, uint64_t u64Value)
    402 {
    403     PVM pVM = pVCpu->CTX_SUFF(pVM);
    404     if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
    405     {
    406         AssertPtr(pVM->pdm.s.Apic.CTX_SUFF(pfnWriteMsr));
    407         return pVM->pdm.s.Apic.CTX_SUFF(pfnWriteMsr)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu, u32Reg, u64Value);
    408     }
    409     return VERR_CPUM_RAISE_GP_0;
    410 }
    411 
    412 
    413 /**
    414  * Read a MSR in APIC range.
    415  *
    416  * @returns Strict VBox status code.
    417  * @param   pVCpu           The cross context virtual CPU structure.
    418  * @param   u32Reg          MSR to read.
    419  * @param   pu64Value       Where to store the value read.
    420  */
    421 VMM_INT_DECL(VBOXSTRICTRC) PDMApicReadMsr(PVMCPU pVCpu, uint32_t u32Reg, uint64_t *pu64Value)
    422 {
    423     PVM pVM = pVCpu->CTX_SUFF(pVM);
    424     if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
    425     {
    426         AssertPtr(pVM->pdm.s.Apic.CTX_SUFF(pfnReadMsr));
    427         return pVM->pdm.s.Apic.CTX_SUFF(pfnReadMsr)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu, u32Reg, pu64Value);
    428     }
    429     return VERR_CPUM_RAISE_GP_0;
    430 }
    431 
    432 
    433 /**
    434  * Gets the frequency of the APIC timer.
    435  *
    436  * @returns VBox status code.
    437  * @param   pVM             The cross context VM structure.
    438  * @param   pu64Value       Where to store the frequency.
    439  */
    440 VMM_INT_DECL(int) PDMApicGetTimerFreq(PVM pVM, uint64_t *pu64Value)
    441 {
    442     if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
    443     {
    444         AssertPtr(pVM->pdm.s.Apic.CTX_SUFF(pfnGetTimerFreq));
    445         *pu64Value = pVM->pdm.s.Apic.CTX_SUFF(pfnGetTimerFreq)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns));
    446         return VINF_SUCCESS;
    447     }
    448     return VERR_PDM_NO_APIC_INSTANCE;
    449 }
    450 
    451 
    452 /**
    453260 * Locks PDM.
    454261 * This might call back to Ring-3 in order to deal with lock contention in GC and R3.

  • trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp

    r64626 r64655  
    16101610    bool    fPendingIntr;
    16111611    uint8_t u8Tpr;
    1612     int rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPendingIntr, NULL /* pu8PendingIrq */);
     1612    int rc = APICGetTpr(pVCpu, &u8Tpr, &fPendingIntr, NULL /* pu8PendingIrq */);
    16131613    AssertRCReturn(rc, rc);
    16141614
    … …  
    32903290                && (pMixedCtx->msrLSTAR & 0xff) != pSvmTransient->u8GuestTpr)
    32913291            {
    3292                 int rc = PDMApicSetTPR(pVCpu, pMixedCtx->msrLSTAR & 0xff);
     3292                int rc = APICSetTpr(pVCpu, pMixedCtx->msrLSTAR & 0xff);
    32933293                AssertRC(rc);
    32943294                HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
    … …  
    32963296            else if (pSvmTransient->u8GuestTpr != pVmcb->ctrl.IntCtrl.n.u8VTPR)
    32973297            {
    3298                 int rc = PDMApicSetTPR(pVCpu, pVmcb->ctrl.IntCtrl.n.u8VTPR << 4);
     3298                int rc = APICSetTpr(pVCpu, pVmcb->ctrl.IntCtrl.n.u8VTPR << 4);
    32993299                AssertRC(rc);
    33003300                HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
    … …  
    40044004            case HMTPRINSTR_READ:
    40054005            {
    4006                 int rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPending, NULL /* pu8PendingIrq */);
     4006                int rc = APICGetTpr(pVCpu, &u8Tpr, &fPending, NULL /* pu8PendingIrq */);
    40074007                AssertRC(rc);
    40084008
    … …  
    40264026                    u8Tpr = (uint8_t)pPatch->uSrcOperand;
    40274027
    4028                 int rc2 = PDMApicSetTPR(pVCpu, u8Tpr);
     4028                int rc2 = APICSetTpr(pVCpu, u8Tpr);
    40294029                AssertRC(rc2);
    40304030                HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
    … …  
    46574657            {
    46584658                /* Our patch code uses LSTAR for TPR caching for 32-bit guests. */
    4659                 int rc2 = PDMApicSetTPR(pVCpu, pCtx->eax & 0xff);
     4659                int rc2 = APICSetTpr(pVCpu, pCtx->eax & 0xff);
    46604660                AssertRC(rc2);
    46614661                HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);

  • trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp

    r64626 r64655  
    34173417            uint8_t u8Tpr         = 0;
    34183418            uint8_t u8PendingIntr = 0;
    3419             rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPendingIntr, &u8PendingIntr);
     3419            rc = APICGetTpr(pVCpu, &u8Tpr, &fPendingIntr, &u8PendingIntr);
    34203420            AssertRCReturn(rc, rc);
    34213421
    … …  
    89628962        /*
    89638963         * If the TPR was raised by the guest, it wouldn't cause a VM-exit immediately. Instead we sync the TPR lazily whenever
    8964          * we eventually get a VM-exit for any reason. This maybe expensive as PDMApicSetTPR() can longjmp to ring-3 and which is
    8965          * why it's done here as it's easier and no less efficient to deal with it here than making hmR0VmxSaveGuestState()
    8966          * cope with longjmps safely (see VMCPU_FF_HM_UPDATE_CR3 handling).
     8964         * we eventually get a VM-exit for any reason.
     8965         *
     8966         * This maybe expensive as PDMApicSetTPR() can longjmp to ring-3 and which is why it's done here as it's easier and
     8967         * no less efficient to deal with it here than making hmR0VmxSaveGuestState() cope with longjmps safely
     8968         * (see VMCPU_FF_HM_UPDATE_CR3 handling).
    89678969         */
     8970        /** @todo r=ramshankar: The 2nd para in the above comment is
     8971         *        outdated, we no longer longjmp to ring-3 on setting
     8972         *        the TPR, but regardless we can probably rework this
     8973         *        portion of the code a bit. */
    89688974        if (   (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW)
    89698975            && pVmxTransient->u8GuestTpr != pVCpu->hm.s.vmx.pbVirtApic[0x80])
    89708976        {
    8971             rc = PDMApicSetTPR(pVCpu, pVCpu->hm.s.vmx.pbVirtApic[0x80]);
     8977            rc = APICSetTpr(pVCpu, pVCpu->hm.s.vmx.pbVirtApic[0x80]);
    89728978            AssertRC(rc);
    89738979            HMCPU_CF_SET(pVCpu, HM_CHANGED_VMX_GUEST_APIC_STATE);

  • trunk/src/VBox/VMM/VMMR0/PDMR0Device.cpp

    r64596 r64655  
    3030#include <VBox/vmm/patm.h>
    3131#include <VBox/vmm/hm.h>
     32#include <VBox/vmm/apic.h>
    3233
    3334#include <VBox/log.h>
    … …  
    447448    PVM    pVM   = pDevIns->Internal.s.pVMR0;
    448449    PVMCPU pVCpu = &pVM->aCpus[0];      /* for PIC we always deliver to CPU 0, MP use APIC */
    449 
    450     if (pVM->pdm.s.Apic.pfnLocalInterruptR0)
    451     {
    452         LogFlow(("pdmR0PicHlp_SetInterruptFF: caller='%p'/%d: Setting local interrupt on LAPIC\n",
    453                  pDevIns, pDevIns->iInstance));
    454         /* Raise the LAPIC's LINT0 line instead of signaling the CPU directly. */
    455         /** @todo rcRZ propagation to pfnLocalInterrupt from caller. */
    456         pVM->pdm.s.Apic.pfnLocalInterruptR0(pVM->pdm.s.Apic.pDevInsR0, pVCpu, 0 /* u8Pin */, 1 /* u8Level */,
    457                                             VINF_SUCCESS /* rcRZ */);
    458         return;
    459     }
    460 
    461     LogFlow(("pdmR0PicHlp_SetInterruptFF: caller=%p/%d: VMCPU_FF_INTERRUPT_PIC %d -> 1\n",
    462              pDevIns, pDevIns->iInstance, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC)));
    463 
    464     VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC);
     450    /** @todo r=ramshankar: Propagating rcRZ and make all callers handle it? */
     451    APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 1 /* u8Level */, VINF_SUCCESS /* rcRZ */);
    465452}
    466453
    … …  
    472459    PVM    pVM   = pDevIns->Internal.s.pVMR0;
    473460    PVMCPU pVCpu = &pVM->aCpus[0];      /* for PIC we always deliver to CPU 0, MP use APIC */
    474 
    475     if (pVM->pdm.s.Apic.pfnLocalInterruptR0)
    476     {
    477         /* Raise the LAPIC's LINT0 line instead of signaling the CPU directly. */
    478         LogFlow(("pdmR0PicHlp_ClearInterruptFF: caller='%s'/%d: Clearing local interrupt on LAPIC\n",
    479                  pDevIns, pDevIns->iInstance));
    480         /* Lower the LAPIC's LINT0 line instead of signaling the CPU directly. */
    481         /** @todo rcRZ propagation to pfnLocalInterrupt from caller. */
    482         pVM->pdm.s.Apic.pfnLocalInterruptR0(pVM->pdm.s.Apic.pDevInsR0, pVCpu, 0 /* u8Pin */, 0 /* u8Level */,
    483                                             VINF_SUCCESS /* rcRZ */);
    484         return;
    485     }
    486 
    487     LogFlow(("pdmR0PicHlp_ClearInterruptFF: caller=%p/%d: VMCPU_FF_INTERRUPT_PIC %d -> 0\n",
    488              pDevIns, pDevIns->iInstance, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC)));
    489 
    490     VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
     461    /** @todo r=ramshankar: Propagating rcRZ and make all callers handle it? */
     462    APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 0 /* u8Level */, VINF_SUCCESS /* rcRZ */);
    491463}
    492464
    … …  
    529501
    530502/** @interface_method_impl{PDMIOAPICHLPR0,pfnApicBusDeliver} */
    531 static DECLCALLBACK(int) pdmR0IoApicHlp_ApicBusDeliver(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
    532                                                        uint8_t iVector, uint8_t u8Polarity, uint8_t u8TriggerMode, uint32_t uTagSrc)
     503static DECLCALLBACK(int) pdmR0IoApicHlp_ApicBusDeliver(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
     504                                                       uint8_t u8DeliveryMode, uint8_t uVector, uint8_t u8Polarity,
     505                                                       uint8_t u8TriggerMode, uint32_t uTagSrc)
    533506{
    534507    PDMDEV_ASSERT_DEVINS(pDevIns);
    535508    PVM pVM = pDevIns->Internal.s.pVMR0;
    536     LogFlow(("pdmR0IoApicHlp_ApicBusDeliver: caller=%p/%d: u8Dest=%RX8 u8DestMode=%RX8 u8DeliveryMode=%RX8 iVector=%RX8 u8Polarity=%RX8 u8TriggerMode=%RX8 uTagSrc=%#x\n",
    537              pDevIns, pDevIns->iInstance, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode, uTagSrc));
    538     Assert(pVM->pdm.s.Apic.pDevInsR0);
    539     if (pVM->pdm.s.Apic.pfnBusDeliverR0)
    540         return pVM->pdm.s.Apic.pfnBusDeliverR0(pVM->pdm.s.Apic.pDevInsR0, u8Dest, u8DestMode, u8DeliveryMode, iVector,
    541                                                u8Polarity, u8TriggerMode, uTagSrc);
    542     return VINF_SUCCESS;
     509    LogFlow(("pdmR0IoApicHlp_ApicBusDeliver: caller=%p/%d: u8Dest=%RX8 u8DestMode=%RX8 u8DeliveryMode=%RX8 uVector=%RX8 u8Polarity=%RX8 u8TriggerMode=%RX8 uTagSrc=%#x\n",
     510             pDevIns, pDevIns->iInstance, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc));
     511    return APICBusDeliver(pVM, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc);
    543512}
    544513

  • trunk/src/VBox/VMM/VMMR3/APIC.cpp

    r64596 r64655  
    16871687     * Register the APIC with PDM.
    16881688     */
    1689     PDMAPICREG ApicReg;
    1690     RT_ZERO(ApicReg);
    1691     ApicReg.u32Version              = PDM_APICREG_VERSION;
    1692     ApicReg.pfnGetInterruptR3       = apicGetInterrupt;
    1693     ApicReg.pfnSetBaseMsrR3         = apicSetBaseMsr;
    1694     ApicReg.pfnGetBaseMsrR3         = apicGetBaseMsr;
    1695     ApicReg.pfnSetTprR3             = apicSetTpr;
    1696     ApicReg.pfnGetTprR3             = apicGetTpr;
    1697     ApicReg.pfnWriteMsrR3           = apicWriteMsr;
    1698     ApicReg.pfnReadMsrR3            = apicReadMsr;
    1699     ApicReg.pfnBusDeliverR3         = apicBusDeliver;
    1700     ApicReg.pfnLocalInterruptR3     = apicLocalInterrupt;
    1701     ApicReg.pfnGetTimerFreqR3       = apicGetTimerFreq;
    1702 
    1703     /*
    1704      * We always require R0 functionality (e.g. apicGetTpr() called by HMR0 VT-x/AMD-V code).
    1705      * Hence, 'fRZEnabled' strictly only applies to MMIO and MSR read/write handlers returning
    1706      * to ring-3. We still need other handlers like apicGetTpr() in ring-0 for now.
    1707      */
    1708     {
    1709         ApicReg.pszGetInterruptRC   = "apicGetInterrupt";
    1710         ApicReg.pszSetBaseMsrRC     = "apicSetBaseMsr";
    1711         ApicReg.pszGetBaseMsrRC     = "apicGetBaseMsr";
    1712         ApicReg.pszSetTprRC         = "apicSetTpr";
    1713         ApicReg.pszGetTprRC         = "apicGetTpr";
    1714         ApicReg.pszWriteMsrRC       = "apicWriteMsr";
    1715         ApicReg.pszReadMsrRC        = "apicReadMsr";
    1716         ApicReg.pszBusDeliverRC     = "apicBusDeliver";
    1717         ApicReg.pszLocalInterruptRC = "apicLocalInterrupt";
    1718         ApicReg.pszGetTimerFreqRC   = "apicGetTimerFreq";
    1719 
    1720         ApicReg.pszGetInterruptR0   = "apicGetInterrupt";
    1721         ApicReg.pszSetBaseMsrR0     = "apicSetBaseMsr";
    1722         ApicReg.pszGetBaseMsrR0     = "apicGetBaseMsr";
    1723         ApicReg.pszSetTprR0         = "apicSetTpr";
    1724         ApicReg.pszGetTprR0         = "apicGetTpr";
    1725         ApicReg.pszWriteMsrR0       = "apicWriteMsr";
    1726         ApicReg.pszReadMsrR0        = "apicReadMsr";
    1727         ApicReg.pszBusDeliverR0     = "apicBusDeliver";
    1728         ApicReg.pszLocalInterruptR0 = "apicLocalInterrupt";
    1729         ApicReg.pszGetTimerFreqR0   = "apicGetTimerFreq";
    1730     }
    1731 
    1732     rc = PDMDevHlpAPICRegister(pDevIns, &ApicReg);
     1689    rc = PDMDevHlpAPICRegister(pDevIns);
    17331690    AssertLogRelRCReturn(rc, rc);
    17341691
    … …  
    17361693     * Initialize the APIC state.
    17371694     */
    1738     /* First insert/remove the MSR range of the x2APIC. */
    17391695    if (pApic->enmMaxMode == PDMAPICMODE_X2APIC)
    17401696    {
    … …  
    17511707    /* Tell CPUM about the APIC feature level so it can adjust APICBASE MSR GP mask and CPUID bits. */
    17521708    apicR3SetCpuIdFeatureLevel(pVM, pApic->enmMaxMode);
    1753 
    1754     /* Initialize the state. */
     1709    /* Finally, initialize the state. */
    17551710    rc = apicR3InitState(pVM);
    17561711    AssertRCReturn(rc, rc);

  • trunk/src/VBox/VMM/VMMR3/CPUM.cpp

    r64626 r64655  
    111111#include <VBox/vmm/cpumctx-v1_6.h>
    112112#include <VBox/vmm/pgm.h>
    113 #include <VBox/vmm/pdmapi.h>
     113#include <VBox/vmm/apic.h>
    114114#include <VBox/vmm/mm.h>
    115115#include <VBox/vmm/em.h>
    … …  
    11581158     * continues to reside in the APIC device and we cache it here in the VCPU for all further accesses.
    11591159     */
    1160     PDMApicGetBaseMsr(pVCpu, &pCtx->msrApicBase, true /* fIgnoreErrors */);
     1160    pCtx->msrApicBase = APICGetBaseMsrNoCheck(pVCpu);
    11611161    LogRel(("CPUM%u: Cached APIC base MSR = %#RX64\n", pVCpu->idCpu, pVCpu->cpum.s.Guest.msrApicBase));
    11621162}
    … …  
    16081608
    16091609        /* Cache the local APIC base from the APIC device. During init. this is done in CPUMR3ResetCpu(). */
    1610         PDMApicGetBaseMsr(pVCpu, &pVCpu->cpum.s.Guest.msrApicBase, true /* fIgnoreErrors */);
     1610        pVCpu->cpum.s.Guest.msrApicBase = APICGetBaseMsrNoCheck(pVCpu);
    16111611        LogRel(("CPUM%u: Cached APIC base MSR = %#RX64\n", idCpu, pVCpu->cpum.s.Guest.msrApicBase));
    16121612
    … …  
    25302530            {
    25312531                PVMCPU pVCpu = &pVM->aCpus[i];
    2532                 PDMApicGetBaseMsr(pVCpu, &pVCpu->cpum.s.Guest.msrApicBase, true /* fIgnoreErrors */);
     2532                pVCpu->cpum.s.Guest.msrApicBase = APICGetBaseMsrNoCheck(pVCpu);
    25332533                LogRel(("CPUM%u: Cached APIC base MSR = %#RX64\n", i, pVCpu->cpum.s.Guest.msrApicBase));
    25342534            }

  • trunk/src/VBox/VMM/VMMR3/CPUMDbg.cpp

    r63465 r64655  
    2323#include <VBox/vmm/cpum.h>
    2424#include <VBox/vmm/dbgf.h>
    25 #include <VBox/vmm/pdmapi.h>
     25#include <VBox/vmm/apic.h>
    2626#include "CPUMInternal.h"
    2727#include <VBox/vmm/vm.h>
    … …  
    422422        case 3: rc = CPUMSetGuestCR3(pVCpu, u64Value); break;
    423423        case 4: rc = CPUMSetGuestCR4(pVCpu, u64Value); break;
    424         case 8: rc = PDMApicSetTPR(pVCpu, (uint8_t)(u64Value << 4)); break;
     424        case 8: rc = APICSetTpr(pVCpu, (uint8_t)(u64Value << 4)); break;
    425425        default:
    426426            AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);

  • trunk/src/VBox/VMM/VMMR3/GIMMinimal.cpp

    r62591 r64655  
    2424#include <VBox/vmm/cpum.h>
    2525#include <VBox/vmm/tm.h>
    26 #include <VBox/vmm/pdmapi.h>
     26#include <VBox/vmm/apic.h>
    2727#include "GIMInternal.h"
    2828#include <VBox/vmm/vm.h>
    … …  
    9797     *
    9898     * This is done in the init. completed routine as we need PDM to be
    99      * initialized (otherwise PDMApicGetTimerFreq() would fail).
     99     * initialized (otherwise APICGetTimerFreq() would fail).
    100100     */
    101101    CPUMCPUIDLEAF HyperLeaf;
    … …  
    114114         */
    115115        uint64_t uApicFreq;
    116         rc = PDMApicGetTimerFreq(pVM, &uApicFreq);
     116        rc = APICGetTimerFreq(pVM, &uApicFreq);
    117117        AssertLogRelRCReturn(rc, rc);
    118118

  • trunk/src/VBox/VMM/VMMR3/PDM.cpp

    r64397 r64655  
    530530     */
    531531    if (pVM->pdm.s.Apic.pDevInsRC)
    532     {
    533532        pVM->pdm.s.Apic.pDevInsRC           += offDelta;
    534         pVM->pdm.s.Apic.pfnGetInterruptRC   += offDelta;
    535         pVM->pdm.s.Apic.pfnSetBaseMsrRC     += offDelta;
    536         pVM->pdm.s.Apic.pfnGetBaseMsrRC     += offDelta;
    537         pVM->pdm.s.Apic.pfnSetTprRC         += offDelta;
    538         pVM->pdm.s.Apic.pfnGetTprRC         += offDelta;
    539         pVM->pdm.s.Apic.pfnWriteMsrRC       += offDelta;
    540         pVM->pdm.s.Apic.pfnReadMsrRC        += offDelta;
    541         pVM->pdm.s.Apic.pfnBusDeliverRC     += offDelta;
    542         if (pVM->pdm.s.Apic.pfnLocalInterruptRC)
    543             pVM->pdm.s.Apic.pfnLocalInterruptRC += offDelta;
    544         pVM->pdm.s.Apic.pfnGetTimerFreqRC   += offDelta;
    545     }
    546533
    547534    /*

  • trunk/src/VBox/VMM/VMMR3/PDMDevHlp.cpp

    r64596 r64655  
    28452845
    28462846/** @interface_method_impl{PDMDEVHLPR3,pfnAPICRegister} */
    2847 static DECLCALLBACK(int) pdmR3DevHlp_APICRegister(PPDMDEVINS pDevIns, PPDMAPICREG pApicReg)
     2847static DECLCALLBACK(int) pdmR3DevHlp_APICRegister(PPDMDEVINS pDevIns)
    28482848{
    28492849    PDMDEV_ASSERT_DEVINS(pDevIns);
    28502850    VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
    2851     LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: pApicReg=%p:{.u32Version=%#x, .pfnGetInterruptR3=%p, .pfnSetBaseMsrR3=%p, .pfnGetBaseMsrR3=%p, "
    2852              ".pfnSetTprR3=%p, .pfnGetTprR3=%p, .pfnWriteMsr3=%p, .pfnReadMsr3=%p, .pfnBusDeliverR3=%p, .pfnLocalInterruptR3=%p .pfnGetTimerFreqR3=%p, pszGetInterruptRC=%p:{%s}, pszSetBaseMsrRC=%p:{%s}, pszGetBaseMsrRC=%p:{%s}, "
    2853              ".pszSetTprRC=%p:{%s}, .pszGetTprRC=%p:{%s}, .pszWriteMsrRC=%p:{%s}, .pszReadMsrRC=%p:{%s}, .pszBusDeliverRC=%p:{%s}, .pszLocalInterruptRC=%p:{%s}, .pszGetTimerFreqRC=%p:{%s}}\n",
    2854              pDevIns->pReg->szName, pDevIns->iInstance, pApicReg, pApicReg->u32Version, pApicReg->pfnGetInterruptR3, pApicReg->pfnSetBaseMsrR3,
    2855              pApicReg->pfnGetBaseMsrR3, pApicReg->pfnSetTprR3, pApicReg->pfnGetTprR3, pApicReg->pfnWriteMsrR3, pApicReg->pfnReadMsrR3, pApicReg->pfnBusDeliverR3, pApicReg->pfnLocalInterruptR3, pApicReg->pfnGetTimerFreqR3, pApicReg->pszGetInterruptRC,
    2856              pApicReg->pszGetInterruptRC, pApicReg->pszSetBaseMsrRC, pApicReg->pszSetBaseMsrRC, pApicReg->pszGetBaseMsrRC, pApicReg->pszGetBaseMsrRC,
    2857              pApicReg->pszSetTprRC, pApicReg->pszSetTprRC, pApicReg->pszGetTprRC, pApicReg->pszGetTprRC, pApicReg->pszWriteMsrRC, pApicReg->pszWriteMsrRC, pApicReg->pszReadMsrRC, pApicReg->pszReadMsrRC, pApicReg->pszBusDeliverRC,
    2858              pApicReg->pszBusDeliverRC, pApicReg->pszLocalInterruptRC, pApicReg->pszLocalInterruptRC, pApicReg->pszGetTimerFreqRC, pApicReg->pszGetTimerFreqRC));
    2859 
    2860     /*
    2861      * Validate input.
    2862      */
    2863     if (pApicReg->u32Version != PDM_APICREG_VERSION)
    2864     {
    2865         AssertMsgFailed(("u32Version=%#x expected %#x\n", pApicReg->u32Version, PDM_APICREG_VERSION));
    2866         LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: returns %Rrc (version)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
    2867         return VERR_INVALID_PARAMETER;
    2868     }
    2869     if (    !pApicReg->pfnGetInterruptR3
    2870         ||  !pApicReg->pfnSetBaseMsrR3
    2871         ||  !pApicReg->pfnGetBaseMsrR3
    2872         ||  !pApicReg->pfnSetTprR3
    2873         ||  !pApicReg->pfnGetTprR3
    2874         ||  !pApicReg->pfnWriteMsrR3
    2875         ||  !pApicReg->pfnReadMsrR3
    2876         ||  !pApicReg->pfnBusDeliverR3
    2877         ||  !pApicReg->pfnLocalInterruptR3
    2878         ||  !pApicReg->pfnGetTimerFreqR3)
    2879     {
    2880         Assert(pApicReg->pfnGetInterruptR3);
    2881         Assert(pApicReg->pfnSetBaseMsrR3);
    2882         Assert(pApicReg->pfnGetBaseMsrR3);
    2883         Assert(pApicReg->pfnSetTprR3);
    2884         Assert(pApicReg->pfnGetTprR3);
    2885         Assert(pApicReg->pfnWriteMsrR3);
    2886         Assert(pApicReg->pfnReadMsrR3);
    2887         Assert(pApicReg->pfnBusDeliverR3);
    2888         Assert(pApicReg->pfnLocalInterruptR3);
    2889         Assert(pApicReg->pfnGetTimerFreqR3);
    2890         LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: returns %Rrc (R3 callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
    2891         return VERR_INVALID_PARAMETER;
    2892     }
    2893     if (   (    pApicReg->pszGetInterruptRC
    2894             ||  pApicReg->pszSetBaseMsrRC
    2895             ||  pApicReg->pszGetBaseMsrRC
    2896             ||  pApicReg->pszSetTprRC
    2897             ||  pApicReg->pszGetTprRC
    2898             ||  pApicReg->pszWriteMsrRC
    2899             ||  pApicReg->pszReadMsrRC
    2900             ||  pApicReg->pszBusDeliverRC
    2901             ||  pApicReg->pszLocalInterruptRC
    2902             ||  pApicReg->pszGetTimerFreqRC)
    2903         &&  (   !VALID_PTR(pApicReg->pszGetInterruptRC)
    2904             ||  !VALID_PTR(pApicReg->pszSetBaseMsrRC)
    2905             ||  !VALID_PTR(pApicReg->pszGetBaseMsrRC)
    2906             ||  !VALID_PTR(pApicReg->pszSetTprRC)
    2907             ||  !VALID_PTR(pApicReg->pszGetTprRC)
    2908             ||  !VALID_PTR(pApicReg->pszWriteMsrRC)
    2909             ||  !VALID_PTR(pApicReg->pszReadMsrRC)
    2910             ||  !VALID_PTR(pApicReg->pszBusDeliverRC)
    2911             ||  !VALID_PTR(pApicReg->pszLocalInterruptRC)
    2912             ||  !VALID_PTR(pApicReg->pszGetTimerFreqRC))
    2913        )
    2914     {
    2915         Assert(VALID_PTR(pApicReg->pszGetInterruptRC));
    2916         Assert(VALID_PTR(pApicReg->pszSetBaseMsrRC));
    2917         Assert(VALID_PTR(pApicReg->pszGetBaseMsrRC));
    2918         Assert(VALID_PTR(pApicReg->pszSetTprRC));
    2919         Assert(VALID_PTR(pApicReg->pszGetTprRC));
    2920         Assert(VALID_PTR(pApicReg->pszReadMsrRC));
    2921         Assert(VALID_PTR(pApicReg->pszWriteMsrRC));
    2922         Assert(VALID_PTR(pApicReg->pszBusDeliverRC));
    2923         Assert(VALID_PTR(pApicReg->pszLocalInterruptRC));
    2924         Assert(VALID_PTR(pApicReg->pszGetTimerFreqRC));
    2925         LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: returns %Rrc (RC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
    2926         return VERR_INVALID_PARAMETER;
    2927     }
    2928     if (   (    pApicReg->pszGetInterruptR0
    2929             ||  pApicReg->pszSetBaseMsrR0
    2930             ||  pApicReg->pszGetBaseMsrR0
    2931             ||  pApicReg->pszSetTprR0
    2932             ||  pApicReg->pszGetTprR0
    2933             ||  pApicReg->pszWriteMsrR0
    2934             ||  pApicReg->pszReadMsrR0
    2935             ||  pApicReg->pszBusDeliverR0
    2936             ||  pApicReg->pszLocalInterruptR0
    2937             ||  pApicReg->pszGetTimerFreqR0)
    2938         &&  (   !VALID_PTR(pApicReg->pszGetInterruptR0)
    2939             ||  !VALID_PTR(pApicReg->pszSetBaseMsrR0)
    2940             ||  !VALID_PTR(pApicReg->pszGetBaseMsrR0)
    2941             ||  !VALID_PTR(pApicReg->pszSetTprR0)
    2942             ||  !VALID_PTR(pApicReg->pszGetTprR0)
    2943             ||  !VALID_PTR(pApicReg->pszReadMsrR0)
    2944             ||  !VALID_PTR(pApicReg->pszWriteMsrR0)
    2945             ||  !VALID_PTR(pApicReg->pszBusDeliverR0)
    2946             ||  !VALID_PTR(pApicReg->pszLocalInterruptR0)
    2947             ||  !VALID_PTR(pApicReg->pszGetTimerFreqR0))
    2948        )
    2949     {
    2950         Assert(VALID_PTR(pApicReg->pszGetInterruptR0));
    2951         Assert(VALID_PTR(pApicReg->pszSetBaseMsrR0));
    2952         Assert(VALID_PTR(pApicReg->pszGetBaseMsrR0));
    2953         Assert(VALID_PTR(pApicReg->pszSetTprR0));
    2954         Assert(VALID_PTR(pApicReg->pszGetTprR0));
    2955         Assert(VALID_PTR(pApicReg->pszReadMsrR0));
    2956         Assert(VALID_PTR(pApicReg->pszWriteMsrR0));
    2957         Assert(VALID_PTR(pApicReg->pszBusDeliverR0));
    2958         Assert(VALID_PTR(pApicReg->pszLocalInterruptR0));
    2959         Assert(VALID_PTR(pApicReg->pszGetTimerFreqR0));
    2960         LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: returns %Rrc (R0 callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
    2961         return VERR_INVALID_PARAMETER;
    2962     }
    29632851
    29642852    /*
    … …  
    29692857    if (pVM->pdm.s.Apic.pDevInsR3)
    29702858    {
    2971         AssertMsgFailed(("Only one apic device is supported!\n"));
     2859        AssertMsgFailed(("Only one APIC device is supported!\n"));
    29722860        LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
    29732861        return VERR_INVALID_PARAMETER;
    … …  
    29752863
    29762864    /*
    2977      * Resolve & initialize the RC bits.
    2978      */
    2979     if (pApicReg->pszGetInterruptRC)
    2980     {
    2981         int rc = pdmR3DevGetSymbolRCLazy(pDevIns, pApicReg->pszGetInterruptRC, &pVM->pdm.s.Apic.pfnGetInterruptRC);
    2982         AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pApicReg->pszGetInterruptRC, rc));
    2983         if (RT_SUCCESS(rc))
    2984         {
    2985             rc = pdmR3DevGetSymbolRCLazy(pDevIns, pApicReg->pszSetBaseMsrRC, &pVM->pdm.s.Apic.pfnSetBaseMsrRC);
    2986             AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pApicReg->pszSetBaseMsrRC, rc));
    2987         }
    2988         if (RT_SUCCESS(rc))
    2989         {
    2990             rc = pdmR3DevGetSymbolRCLazy(pDevIns, pApicReg->pszGetBaseMsrRC, &pVM->pdm.s.Apic.pfnGetBaseMsrRC);
    2991             AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pApicReg->pszGetBaseMsrRC, rc));
    2992         }
    2993         if (RT_SUCCESS(rc))
    2994         {
    2995             rc = pdmR3DevGetSymbolRCLazy(pDevIns, pApicReg->pszSetTprRC, &pVM->pdm.s.Apic.pfnSetTprRC);
    2996             AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pApicReg->pszSetTprRC, rc));
    2997         }
    2998         if (RT_SUCCESS(rc))
    2999         {
    3000             rc = pdmR3DevGetSymbolRCLazy(pDevIns, pApicReg->pszGetTprRC, &pVM->pdm.s.Apic.pfnGetTprRC);
    3001             AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pApicReg->pszGetTprRC, rc));
    3002         }
    3003         if (RT_SUCCESS(rc))
    3004         {
    3005             rc = pdmR3DevGetSymbolRCLazy(pDevIns, pApicReg->pszWriteMsrRC, &pVM->pdm.s.Apic.pfnWriteMsrRC);
    3006             AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pApicReg->pszWriteMsrRC, rc));
    3007         }
    3008         if (RT_SUCCESS(rc))
    3009         {
    3010             rc = pdmR3DevGetSymbolRCLazy(pDevIns, pApicReg->pszReadMsrRC, &pVM->pdm.s.Apic.pfnReadMsrRC);
    3011             AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pApicReg->pszReadMsrRC, rc));
    3012         }
    3013         if (RT_SUCCESS(rc))
    3014         {
    3015             rc = pdmR3DevGetSymbolRCLazy(pDevIns, pApicReg->pszBusDeliverRC, &pVM->pdm.s.Apic.pfnBusDeliverRC);
    3016             AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pApicReg->pszBusDeliverRC, rc));
    3017         }
    3018         if (RT_SUCCESS(rc))
    3019         {
    3020             rc = pdmR3DevGetSymbolRCLazy(pDevIns, pApicReg->pszLocalInterruptRC, &pVM->pdm.s.Apic.pfnLocalInterruptRC);
    3021             AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pApicReg->pszLocalInterruptRC, rc));
    3022         }
    3023         if (RT_SUCCESS(rc))
    3024         {
    3025             rc = pdmR3DevGetSymbolRCLazy(pDevIns, pApicReg->pszGetTimerFreqRC, &pVM->pdm.s.Apic.pfnGetTimerFreqRC);
    3026             AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pApicReg->pszGetTimerFreqRC, rc));
    3027         }
    3028         if (RT_FAILURE(rc))
    3029         {
    3030             LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
    3031             return rc;
    3032         }
    3033         pVM->pdm.s.Apic.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
    3034     }
    3035     else
    3036     {
    3037         pVM->pdm.s.Apic.pDevInsRC           = 0;
    3038         pVM->pdm.s.Apic.pfnGetInterruptRC   = 0;
    3039         pVM->pdm.s.Apic.pfnSetBaseMsrRC     = 0;
    3040         pVM->pdm.s.Apic.pfnGetBaseMsrRC     = 0;
    3041         pVM->pdm.s.Apic.pfnSetTprRC         = 0;
    3042         pVM->pdm.s.Apic.pfnGetTprRC         = 0;
    3043         pVM->pdm.s.Apic.pfnWriteMsrRC       = 0;
    3044         pVM->pdm.s.Apic.pfnReadMsrRC        = 0;
    3045         pVM->pdm.s.Apic.pfnBusDeliverRC     = 0;
    3046         pVM->pdm.s.Apic.pfnLocalInterruptRC = 0;
    3047         pVM->pdm.s.Apic.pfnGetTimerFreqRC   = 0;
    3048     }
    3049 
    3050     /*
    3051      * Resolve & initialize the R0 bits.
    3052      */
    3053     if (pApicReg->pszGetInterruptR0)
    3054     {
    3055         int rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pApicReg->pszGetInterruptR0, &pVM->pdm.s.Apic.pfnGetInterruptR0);
    3056         AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pApicReg->pszGetInterruptR0, rc));
    3057         if (RT_SUCCESS(rc))
    3058         {
    3059             rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pApicReg->pszSetBaseMsrR0, &pVM->pdm.s.Apic.pfnSetBaseMsrR0);
    3060             AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pApicReg->pszSetBaseMsrR0, rc));
    3061         }
    3062         if (RT_SUCCESS(rc))
    3063         {
    3064             rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pApicReg->pszGetBaseMsrR0, &pVM->pdm.s.Apic.pfnGetBaseMsrR0);
    3065             AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pApicReg->pszGetBaseMsrR0, rc));
    3066         }
    3067         if (RT_SUCCESS(rc))
    3068         {
    3069             rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pApicReg->pszSetTprR0, &pVM->pdm.s.Apic.pfnSetTprR0);
    3070             AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pApicReg->pszSetTprR0, rc));
    3071         }
    3072         if (RT_SUCCESS(rc))
    3073         {
    3074             rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pApicReg->pszGetTprR0, &pVM->pdm.s.Apic.pfnGetTprR0);
    3075             AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pApicReg->pszGetTprR0, rc));
    3076         }
    3077         if (RT_SUCCESS(rc))
    3078         {
    3079             rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pApicReg->pszWriteMsrR0, &pVM->pdm.s.Apic.pfnWriteMsrR0);
    3080             AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pApicReg->pszWriteMsrR0, rc));
    3081         }
    3082         if (RT_SUCCESS(rc))
    3083         {
    3084             rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pApicReg->pszReadMsrR0, &pVM->pdm.s.Apic.pfnReadMsrR0);
    3085             AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pApicReg->pszReadMsrR0, rc));
    3086         }
    3087         if (RT_SUCCESS(rc))
    3088         {
    3089             rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pApicReg->pszBusDeliverR0, &pVM->pdm.s.Apic.pfnBusDeliverR0);
    3090             AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pApicReg->pszBusDeliverR0, rc));
    3091         }
    3092         if (RT_SUCCESS(rc))
    3093         {
    3094             rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pApicReg->pszLocalInterruptR0, &pVM->pdm.s.Apic.pfnLocalInterruptR0);
    3095             AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pApicReg->pszLocalInterruptR0, rc));
    3096         }
    3097         if (RT_SUCCESS(rc))
    3098         {
    3099             rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pApicReg->pszGetTimerFreqR0, &pVM->pdm.s.Apic.pfnGetTimerFreqR0);
    3100             AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pApicReg->pszGetTimerFreqR0, rc));
    3101         }
    3102         if (RT_FAILURE(rc))
    3103         {
    3104             LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
    3105             return rc;
    3106         }
    3107         pVM->pdm.s.Apic.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
    3108         Assert(pVM->pdm.s.Apic.pDevInsR0);
    3109     }
    3110     else
    3111     {
    3112         pVM->pdm.s.Apic.pfnGetInterruptR0   = 0;
    3113         pVM->pdm.s.Apic.pfnSetBaseMsrR0     = 0;
    3114         pVM->pdm.s.Apic.pfnGetBaseMsrR0     = 0;
    3115         pVM->pdm.s.Apic.pfnSetTprR0         = 0;
    3116         pVM->pdm.s.Apic.pfnGetTprR0         = 0;
    3117         pVM->pdm.s.Apic.pfnWriteMsrR0       = 0;
    3118         pVM->pdm.s.Apic.pfnReadMsrR0        = 0;
    3119         pVM->pdm.s.Apic.pfnBusDeliverR0     = 0;
    3120         pVM->pdm.s.Apic.pfnLocalInterruptR0 = 0;
    3121         pVM->pdm.s.Apic.pfnGetTimerFreqR0   = 0;
    3122         pVM->pdm.s.Apic.pDevInsR0           = 0;
    3123     }
    3124 
    3125     /*
    3126      * Initialize the HC bits.
    3127      */
    3128     pVM->pdm.s.Apic.pDevInsR3           = pDevIns;
    3129     pVM->pdm.s.Apic.pfnGetInterruptR3   = pApicReg->pfnGetInterruptR3;
    3130     pVM->pdm.s.Apic.pfnSetBaseMsrR3     = pApicReg->pfnSetBaseMsrR3;
    3131     pVM->pdm.s.Apic.pfnGetBaseMsrR3     = pApicReg->pfnGetBaseMsrR3;
    3132     pVM->pdm.s.Apic.pfnSetTprR3         = pApicReg->pfnSetTprR3;
    3133     pVM->pdm.s.Apic.pfnGetTprR3         = pApicReg->pfnGetTprR3;
    3134     pVM->pdm.s.Apic.pfnWriteMsrR3       = pApicReg->pfnWriteMsrR3;
    3135     pVM->pdm.s.Apic.pfnReadMsrR3        = pApicReg->pfnReadMsrR3;
    3136     pVM->pdm.s.Apic.pfnBusDeliverR3     = pApicReg->pfnBusDeliverR3;
    3137     pVM->pdm.s.Apic.pfnLocalInterruptR3 = pApicReg->pfnLocalInterruptR3;
    3138     pVM->pdm.s.Apic.pfnGetTimerFreqR3   = pApicReg->pfnGetTimerFreqR3;
    3139     Log(("PDM: Registered APIC device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
    3140 
     2865     * Initialize the RC, R0 and HC bits.
     2866     */
     2867    pVM->pdm.s.Apic.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
     2868    Assert(pVM->pdm.s.Apic.pDevInsRC);
     2869
     2870    pVM->pdm.s.Apic.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
     2871    Assert(pVM->pdm.s.Apic.pDevInsR0);
     2872
     2873    pVM->pdm.s.Apic.pDevInsR3 = pDevIns;
    31412874    LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
    31422875    return VINF_SUCCESS;

  • trunk/src/VBox/VMM/VMMR3/PDMDevMiscHlp.cpp

    r64596 r64655  
    2525#include <VBox/vmm/pgm.h>
    2626#include <VBox/vmm/hm.h>
     27#include <VBox/vmm/apic.h>
    2728#ifdef VBOX_WITH_REM
    2829# include <VBox/vmm/rem.h>
    … …  
    5152{
    5253    PDMDEV_ASSERT_DEVINS(pDevIns);
    53     PVM pVM = pDevIns->Internal.s.pVMR3;
     54    PVM    pVM = pDevIns->Internal.s.pVMR3;
    5455    PVMCPU pVCpu = &pVM->aCpus[0];  /* for PIC we always deliver to CPU 0, MP use APIC */
    55 
    56     if (pVM->pdm.s.Apic.pfnLocalInterruptR3)
    57     {
    58         LogFlow(("pdmR3PicHlp_SetInterruptFF: caller='%s'/%d: Setting local interrupt on LAPIC\n",
    59                  pDevIns->pReg->szName, pDevIns->iInstance));
    60 
    61         /* Raise the LAPIC's LINT0 line instead of signaling the CPU directly. */
    62         /** @todo 'rcRZ' propagation to pfnLocalInterrupt from caller. */
    63         pVM->pdm.s.Apic.pfnLocalInterruptR3(pVM->pdm.s.Apic.pDevInsR3, pVCpu, 0 /* u8Pin */, 1 /* u8Level */,
    64                                             VINF_SUCCESS /* rcRZ */);
    65         return;
    66     }
    67 
    68     LogFlow(("pdmR3PicHlp_SetInterruptFF: caller='%s'/%d: VMCPU_FF_INTERRUPT_PIC %d -> 1\n",
    69              pDevIns->pReg->szName, pDevIns->iInstance, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC)));
    70 
    71     VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC);
    72 #ifdef VBOX_WITH_REM
    73     REMR3NotifyInterruptSet(pVM, pVCpu);
    74 #endif
    75     VMR3NotifyCpuFFU(pVCpu->pUVCpu, VMNOTIFYFF_FLAGS_DONE_REM | VMNOTIFYFF_FLAGS_POKE);
     56    APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 1 /* u8Level */, VINF_SUCCESS /* rcRZ */);
    7657}
    7758
    … …  
    8364    PVM pVM = pDevIns->Internal.s.pVMR3;
    8465    PVMCPU pVCpu = &pVM->aCpus[0];  /* for PIC we always deliver to CPU 0, MP use APIC */
    85 
    86     if (pVM->pdm.s.Apic.pfnLocalInterruptR3)
    87     {
    88         /* Raise the LAPIC's LINT0 line instead of signaling the CPU directly. */
    89         LogFlow(("pdmR3PicHlp_ClearInterruptFF: caller='%s'/%d: Clearing local interrupt on LAPIC\n",
    90                  pDevIns->pReg->szName, pDevIns->iInstance));
    91 
    92         /* Lower the LAPIC's LINT0 line instead of signaling the CPU directly. */
    93         /** @todo 'rcRZ' propagation to pfnLocalInterrupt from caller. */
    94         pVM->pdm.s.Apic.pfnLocalInterruptR3(pVM->pdm.s.Apic.pDevInsR3, pVCpu, 0 /* u8Pin */, 0 /* u8Level */,
    95                                             VINF_SUCCESS /* rcRZ */);
    96         return;
    97     }
    98 
    99     LogFlow(("pdmR3PicHlp_ClearInterruptFF: caller='%s'/%d: VMCPU_FF_INTERRUPT_PIC %d -> 0\n",
    100              pDevIns->pReg->szName, pDevIns->iInstance, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC)));
    101 
    102     VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
    103 #ifdef VBOX_WITH_REM
    104     REMR3NotifyInterruptClear(pVM, pVCpu);
    105 #endif
     66    APICLocalInterrupt(pVCpu, 0 /* u8Pin */,  0 /* u8Level */, VINF_SUCCESS /* rcRZ */);
    10667}
    10768
    … …  
    183144
    184145/** @interface_method_impl{PDMIOAPICHLPR3,pfnApicBusDeliver} */
    185 static DECLCALLBACK(int) pdmR3IoApicHlp_ApicBusDeliver(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
    186                                                         uint8_t iVector, uint8_t u8Polarity, uint8_t u8TriggerMode, uint32_t uTagSrc)
    187 {
    188     PDMDEV_ASSERT_DEVINS(pDevIns);
    189     PVM pVM = pDevIns->Internal.s.pVMR3;
    190     LogFlow(("pdmR3IoApicHlp_ApicBusDeliver: caller='%s'/%d: u8Dest=%RX8 u8DestMode=%RX8 u8DeliveryMode=%RX8 iVector=%RX8 u8Polarity=%RX8 u8TriggerMode=%RX8 uTagSrc=%#x\n",
    191              pDevIns->pReg->szName, pDevIns->iInstance, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode, uTagSrc));
    192     if (pVM->pdm.s.Apic.pfnBusDeliverR3)
    193         return pVM->pdm.s.Apic.pfnBusDeliverR3(pVM->pdm.s.Apic.pDevInsR3, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode, uTagSrc);
    194     return VINF_SUCCESS;
     146static DECLCALLBACK(int) pdmR3IoApicHlp_ApicBusDeliver(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
     147                                                       uint8_t u8DeliveryMode, uint8_t uVector, uint8_t u8Polarity,
     148                                                       uint8_t u8TriggerMode, uint32_t uTagSrc)
     149{
     150    PDMDEV_ASSERT_DEVINS(pDevIns);
     151    PVM pVM = pDevIns->Internal.s.pVMR3;
     152    LogFlow(("pdmR3IoApicHlp_ApicBusDeliver: caller='%s'/%d: u8Dest=%RX8 u8DestMode=%RX8 u8DeliveryMode=%RX8 uVector=%RX8 u8Polarity=%RX8 u8TriggerMode=%RX8 uTagSrc=%#x\n",
     153             pDevIns->pReg->szName, pDevIns->iInstance, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc));
     154    return APICBusDeliver(pVM, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc);
    195155}
    196156

  • trunk/src/VBox/VMM/VMMRC/PDMRCDevice.cpp

    r64596 r64655  
    2929#include <VBox/vmm/vmm.h>
    3030#include <VBox/vmm/patm.h>
     31#include <VBox/vmm/apic.h>
    3132
    3233#include <VBox/log.h>
    … …  
    432433    PVM pVM = pDevIns->Internal.s.pVMRC;
    433434    PVMCPU pVCpu = &pVM->aCpus[0];  /* for PIC we always deliver to CPU 0, MP use APIC */
    434 
    435     if (pVM->pdm.s.Apic.pfnLocalInterruptRC)
    436     {
    437         LogFlow(("pdmRCPicHlp_SetInterruptFF: caller='%p'/%d: Setting local interrupt on LAPIC\n",
    438                  pDevIns, pDevIns->iInstance));
    439         /* Raise the LAPIC's LINT0 line instead of signaling the CPU directly. */
    440         /** @todo 'rcRZ' propagation to pfnLocalInterrupt from caller. */
    441         pVM->pdm.s.Apic.pfnLocalInterruptRC(pVM->pdm.s.Apic.pDevInsRC, pVCpu, 0 /* u8Pin */, 1 /* u8Level*/,
    442                                             VINF_SUCCESS /*rcRZ*/);
    443         return;
    444     }
    445 
    446     LogFlow(("pdmRCPicHlp_SetInterruptFF: caller=%p/%d: VMMCPU_FF_INTERRUPT_PIC %d -> 1\n",
    447              pDevIns, pDevIns->iInstance, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC)));
    448 
    449     VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC);
     435    /** @todo r=ramshankar: Propagating rcRZ and make all callers handle it? */
     436    APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 1 /* u8Level */, VINF_SUCCESS /* rcRZ */);
    450437}
    451438
    … …  
    457444    PVM pVM = pDevIns->Internal.s.CTX_SUFF(pVM);
    458445    PVMCPU pVCpu = &pVM->aCpus[0];  /* for PIC we always deliver to CPU 0, MP use APIC */
    459 
    460     if (pVM->pdm.s.Apic.pfnLocalInterruptRC)
    461     {
    462         /* Raise the LAPIC's LINT0 line instead of signaling the CPU directly. */
    463         LogFlow(("pdmRCPicHlp_ClearInterruptFF: caller='%s'/%d: Clearing local interrupt on LAPIC\n",
    464                  pDevIns, pDevIns->iInstance));
    465         /* Lower the LAPIC's LINT0 line instead of signaling the CPU directly. */
    466         /** @todo 'rcRZ' propagation to pfnLocalInterrupt from caller. */
    467         pVM->pdm.s.Apic.pfnLocalInterruptRC(pVM->pdm.s.Apic.pDevInsRC, pVCpu, 0 /* u8Pin */, 0 /* u8Level */,
    468                                             VINF_SUCCESS /* rcRZ */);
    469         return;
    470     }
    471 
    472     LogFlow(("pdmRCPicHlp_ClearInterruptFF: caller=%p/%d: VMCPU_FF_INTERRUPT_PIC %d -> 0\n",
    473              pDevIns, pDevIns->iInstance, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC)));
    474 
    475     VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
     446    /** @todo r=ramshankar: Propagating rcRZ and make all callers handle it? */
     447    APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 0 /* u8Level */, VINF_SUCCESS /* rcRZ */);
    476448}
    477449
    … …  
    514486
    515487/** @interface_method_impl{PDMIOAPICHLPRC,pfnApicBusDeliver} */
    516 static DECLCALLBACK(int) pdmRCIoApicHlp_ApicBusDeliver(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
    517                                                        uint8_t iVector, uint8_t u8Polarity, uint8_t u8TriggerMode, uint32_t uTagSrc)
     488static DECLCALLBACK(int) pdmRCIoApicHlp_ApicBusDeliver(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
     489                                                       uint8_t u8DeliveryMode, uint8_t uVector, uint8_t u8Polarity,
     490                                                       uint8_t u8TriggerMode, uint32_t uTagSrc)
    518491{
    519492    PDMDEV_ASSERT_DEVINS(pDevIns);
    520493    PVM pVM = pDevIns->Internal.s.pVMRC;
    521     LogFlow(("pdmRCIoApicHlp_ApicBusDeliver: caller=%p/%d: u8Dest=%RX8 u8DestMode=%RX8 u8DeliveryMode=%RX8 iVector=%RX8 u8Polarity=%RX8 u8TriggerMode=%RX8 uTagSrc=%#x\n",
    522              pDevIns, pDevIns->iInstance, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode, uTagSrc));
    523     Assert(pVM->pdm.s.Apic.pDevInsRC);
    524     if (pVM->pdm.s.Apic.pfnBusDeliverRC)
    525         return pVM->pdm.s.Apic.pfnBusDeliverRC(pVM->pdm.s.Apic.pDevInsRC, u8Dest, u8DestMode, u8DeliveryMode, iVector,
    526                                                u8Polarity, u8TriggerMode, uTagSrc);
    527     return VINF_SUCCESS;
     494    LogFlow(("pdmRCIoApicHlp_ApicBusDeliver: caller=%p/%d: u8Dest=%RX8 u8DestMode=%RX8 u8DeliveryMode=%RX8 uVector=%RX8 u8Polarity=%RX8 u8TriggerMode=%RX8 uTagSrc=%#x\n",
     495             pDevIns, pDevIns->iInstance, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc));
     496    return APICBusDeliver(pVM, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc);
    528497}
    529498

  • trunk/src/VBox/VMM/include/APICInternal.h

    r64596 r64655  
    10421042    /** MSR write disallowed due to incompatible config. */
    10431043    APICMSRACCESS_WRITE_DISALLOWED_CONFIG,
     1044    /** MSR read disallowed due to incompatible config. */
     1045    APICMSRACCESS_READ_DISALLOWED_CONFIG,
    10441046    /* Count of enum members (don't use). */
    10451047    APICMSRACCESS_COUNT

  • trunk/src/VBox/VMM/include/PDMInternal.h

    r64596 r64655  
    556556    /** Pointer to the APIC device instance - R3 Ptr. */
    557557    PPDMDEVINSR3                       pDevInsR3;
    558     /** @copydoc PDMAPICREG::pfnGetInterruptR3 */
    559     DECLR3CALLBACKMEMBER(int,          pfnGetInterruptR3,(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint8_t *pu8Vector,
    560                                                           uint32_t *pu32TagSrc));
    561     /** @copydoc PDMAPICREG::pfnSetBaseMsrR3 */
    562     DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnSetBaseMsrR3,(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint64_t u64Base));
    563     /** @copydoc PDMAPICREG::pfnGetBaseMsrR3 */
    564     DECLR3CALLBACKMEMBER(uint64_t,     pfnGetBaseMsrR3,(PPDMDEVINS pDevIns, PVMCPU pVCpu));
    565     /** @copydoc PDMAPICREG::pfnSetTprR3 */
    566     DECLR3CALLBACKMEMBER(void,         pfnSetTprR3,(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint8_t u8Tpr));
    567     /** @copydoc PDMAPICREG::pfnGetTprR3 */
    568     DECLR3CALLBACKMEMBER(uint8_t,      pfnGetTprR3,(PPDMDEVINS pDevIns, PVMCPU pVCpu, bool *pfPending, uint8_t *pu8PendingIntr));
    569     /** @copydoc PDMAPICREG::pfnWriteMsrR3 */
    570     DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnWriteMsrR3,(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint32_t u32Reg, uint64_t u64Value));
    571     /** @copydoc PDMAPICREG::pfnReadMsrR3 */
    572     DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnReadMsrR3,(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint32_t u32Reg, uint64_t *pu64Value));
    573     /** @copydoc PDMAPICREG::pfnBusDeliverR3 */
    574     DECLR3CALLBACKMEMBER(int,          pfnBusDeliverR3,(PPDMDEVINS pDevIns, uint8_t uDest, uint8_t uDestMode,
    575                                                         uint8_t uDeliveryMode, uint8_t uVector, uint8_t uPolarity,
    576                                                         uint8_t uTriggerMode, uint32_t uTagSrc));
    577     /** @copydoc PDMAPICREG::pfnLocalInterruptR3 */
    578     DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnLocalInterruptR3,(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint8_t u8Pin, uint8_t u8Level,
    579                                                             int rcRZ));
    580     /** @copydoc PDMAPICREG::pfnGetTimerFreqR3 */
    581     DECLR3CALLBACKMEMBER(uint64_t,     pfnGetTimerFreqR3,(PPDMDEVINS pDevIns));
    582 
    583558    /** Pointer to the APIC device instance - R0 Ptr. */
    584559    PPDMDEVINSR0                       pDevInsR0;
    585     /** @copydoc PDMAPICREG::pfnGetInterruptR3 */
    586     DECLR0CALLBACKMEMBER(int,          pfnGetInterruptR0,(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint8_t *pu8Vector,
    587                                                           uint32_t *pu32TagSrc));
    588     /** @copydoc PDMAPICREG::pfnSetBaseMsrR3 */
    589     DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnSetBaseMsrR0,(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint64_t u64Base));
    590     /** @copydoc PDMAPICREG::pfnGetBaseMsrR3 */
    591     DECLR0CALLBACKMEMBER(uint64_t,     pfnGetBaseMsrR0,(PPDMDEVINS pDevIns, PVMCPU pVCpu));
    592     /** @copydoc PDMAPICREG::pfnSetTprR3 */
    593     DECLR0CALLBACKMEMBER(void,         pfnSetTprR0,(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint8_t u8Tpr));
    594     /** @copydoc PDMAPICREG::pfnGetTprR3 */
    595     DECLR0CALLBACKMEMBER(uint8_t,      pfnGetTprR0,(PPDMDEVINS pDevIns, PVMCPU pVCpu, bool *pfPending, uint8_t *pu8PendingIntr));
    596      /** @copydoc PDMAPICREG::pfnWriteMsrR3 */
    597     DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnWriteMsrR0,(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint32_t u32Reg, uint64_t u64Value));
    598     /** @copydoc PDMAPICREG::pfnReadMsrR3 */
    599     DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnReadMsrR0,(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint32_t u32Reg, uint64_t *pu64Value));
    600     /** @copydoc PDMAPICREG::pfnBusDeliverR3 */
    601     DECLR0CALLBACKMEMBER(int,          pfnBusDeliverR0,(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
    602                                                         uint8_t u8DeliveryMode, uint8_t iVector, uint8_t u8Polarity,
    603                                                         uint8_t u8TriggerMode, uint32_t uTagSrc));
    604     /** @copydoc PDMAPICREG::pfnLocalInterruptR3 */
    605     DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnLocalInterruptR0,(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint8_t u8Pin, uint8_t u8Level,
    606                                                             int rcRZ));
    607     /** @copydoc PDMAPICREG::pfnGetTimerFreqR3 */
    608     DECLR0CALLBACKMEMBER(uint64_t,     pfnGetTimerFreqR0,(PPDMDEVINS pDevIns));
    609 
    610560    /** Pointer to the APIC device instance - RC Ptr. */
    611561    PPDMDEVINSRC                       pDevInsRC;
    612     /** @copydoc PDMAPICREG::pfnGetInterruptR3 */
    613     DECLRCCALLBACKMEMBER(int,          pfnGetInterruptRC,(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint8_t *pu8Vector,
    614                                                           uint32_t *pu32TagSrc));
    615     /** @copydoc PDMAPICREG::pfnSetBaseMsrR3 */
    616     DECLRCCALLBACKMEMBER(VBOXSTRICTRC, pfnSetBaseMsrRC,(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint64_t u64Base));
    617     /** @copydoc PDMAPICREG::pfnGetBaseMsrR3 */
    618     DECLRCCALLBACKMEMBER(uint64_t,     pfnGetBaseMsrRC,(PPDMDEVINS pDevIns, PVMCPU pVCpu));
    619     /** @copydoc PDMAPICREG::pfnSetTprR3 */
    620     DECLRCCALLBACKMEMBER(void,         pfnSetTprRC,(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint8_t u8Tpr));
    621     /** @copydoc PDMAPICREG::pfnGetTprR3 */
    622     DECLRCCALLBACKMEMBER(uint8_t,      pfnGetTprRC,(PPDMDEVINS pDevIns, PVMCPU pVCpu, bool *pfPending, uint8_t *pu8PendingIntr));
    623     /** @copydoc PDMAPICREG::pfnWriteMsrR3 */
    624     DECLRCCALLBACKMEMBER(VBOXSTRICTRC, pfnWriteMsrRC,(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint32_t u32Reg, uint64_t u64Value));
    625     /** @copydoc PDMAPICREG::pfnReadMsrR3 */
    626     DECLRCCALLBACKMEMBER(VBOXSTRICTRC, pfnReadMsrRC,(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint32_t u32Reg, uint64_t *pu64Value));
    627     /** @copydoc PDMAPICREG::pfnBusDeliverR3 */
    628     DECLRCCALLBACKMEMBER(int,          pfnBusDeliverRC,(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
    629                                                         uint8_t u8DeliveryMode, uint8_t iVector, uint8_t u8Polarity,
    630                                                         uint8_t u8TriggerMode, uint32_t uTagSrc));
    631     /** @copydoc PDMAPICREG::pfnLocalInterruptR3 */
    632     DECLRCCALLBACKMEMBER(VBOXSTRICTRC, pfnLocalInterruptRC,(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint8_t u8Pin, uint8_t u8Level,
    633                                                             int rcRZ));
    634     /** @copydoc PDMAPICREG::pfnGetTimerFreqR3 */
    635     DECLRCCALLBACKMEMBER(uint64_t,     pfnGetTimerFreqRC,(PPDMDEVINS pDevIns));
    636 
    637562    uint8_t                            Alignment[4];
    638563} PDMAPIC;

  • trunk/src/VBox/VMM/testcase/tstVMStruct.h

    r64626 r64655  
    446446    GEN_CHECK_OFF(PDM, Apic);
    447447    GEN_CHECK_OFF_DOT(PDM, Apic.pDevInsR3);
    448     GEN_CHECK_OFF_DOT(PDM, Apic.pfnGetInterruptR3);
    449     GEN_CHECK_OFF_DOT(PDM, Apic.pfnSetBaseMsrR3);
    450     GEN_CHECK_OFF_DOT(PDM, Apic.pfnGetBaseMsrR3);
    451     GEN_CHECK_OFF_DOT(PDM, Apic.pfnSetTprR3);
    452     GEN_CHECK_OFF_DOT(PDM, Apic.pfnWriteMsrR3);
    453     GEN_CHECK_OFF_DOT(PDM, Apic.pfnReadMsrR3);
    454     GEN_CHECK_OFF_DOT(PDM, Apic.pfnGetTprR3);
    455     GEN_CHECK_OFF_DOT(PDM, Apic.pfnBusDeliverR3);
    456448    GEN_CHECK_OFF_DOT(PDM, Apic.pDevInsR0);
    457     GEN_CHECK_OFF_DOT(PDM, Apic.pfnGetInterruptR0);
    458     GEN_CHECK_OFF_DOT(PDM, Apic.pfnSetBaseMsrR0);
    459     GEN_CHECK_OFF_DOT(PDM, Apic.pfnGetBaseMsrR0);
    460     GEN_CHECK_OFF_DOT(PDM, Apic.pfnSetTprR0);
    461     GEN_CHECK_OFF_DOT(PDM, Apic.pfnGetTprR0);
    462     GEN_CHECK_OFF_DOT(PDM, Apic.pfnWriteMsrR0);
    463     GEN_CHECK_OFF_DOT(PDM, Apic.pfnReadMsrR0);
    464     GEN_CHECK_OFF_DOT(PDM, Apic.pfnBusDeliverR0);
    465449    GEN_CHECK_OFF_DOT(PDM, Apic.pDevInsRC);
    466     GEN_CHECK_OFF_DOT(PDM, Apic.pfnGetInterruptRC);
    467     GEN_CHECK_OFF_DOT(PDM, Apic.pfnSetBaseMsrRC);
    468     GEN_CHECK_OFF_DOT(PDM, Apic.pfnGetBaseMsrRC);
    469     GEN_CHECK_OFF_DOT(PDM, Apic.pfnSetTprRC);
    470     GEN_CHECK_OFF_DOT(PDM, Apic.pfnGetTprRC);
    471     GEN_CHECK_OFF_DOT(PDM, Apic.pfnWriteMsrRC);
    472     GEN_CHECK_OFF_DOT(PDM, Apic.pfnReadMsrRC);
    473     GEN_CHECK_OFF_DOT(PDM, Apic.pfnBusDeliverRC);
    474450    GEN_CHECK_OFF(PDM, IoApic);
    475451    GEN_CHECK_OFF_DOT(PDM, IoApic.pDevInsR3);
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