Changeset 64663 in vbox for trunk/src/VBox/VMM/VMMAll

Timestamp:

Nov 14, 2016 3:46:35 PM (8 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

111915

Message:

VMM/APIC: Get rid of msrApicBase cache from CPUMCTX, make APIC work with configured as mode disabled as well.

Location:

trunk/src/VBox/VMM/VMMAll

Files:

• APICAll.cpp (modified) (12 diffs)
• PDMAll.cpp (modified) (2 diffs)

trunk/src/VBox/VMM/VMMAll/APICAll.cpp

@@ -412 +412 @@
  *
  * @returns true if enabled, false otherwise.
- */
-DECLINLINE(bool) apicIsEnabled(PVMCPU pVCpu)
+ * @param   pVCpu           The cross context virtual CPU structure.
+ */
+VMM_INT_DECL(bool) APICIsEnabled(PVMCPU pVCpu)
 {
     PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
@@ -616 +617 @@
             {
                 if (   VMCPUSET_IS_PRESENT(pDestCpuSet, idCpu)
-                    && apicIsEnabled(&pVM->aCpus[idCpu]))
+                    && APICIsEnabled(&pVM->aCpus[idCpu]))
                     fAccepted = apicPostInterrupt(&pVM->aCpus[idCpu], uVector, enmTriggerMode);
             }
@@ -626 +627 @@
             VMCPUID const idCpu = VMCPUSET_FIND_FIRST_PRESENT(pDestCpuSet);
             if (   idCpu < pVM->cCpus
-                && apicIsEnabled(&pVM->aCpus[idCpu]))
+                && APICIsEnabled(&pVM->aCpus[idCpu]))
                 fAccepted = apicPostInterrupt(&pVM->aCpus[idCpu], uVector, enmTriggerMode);
             else
@@ -652 +653 @@
             {
                 if (   VMCPUSET_IS_PRESENT(pDestCpuSet, idCpu)
-                    && apicIsEnabled(&pVM->aCpus[idCpu]))
+                    && APICIsEnabled(&pVM->aCpus[idCpu]))
                 {
                     Log2(("APIC: apicSendIntr: Raising NMI on VCPU%u\n", idCpu));
@@ -1879 +1880 @@
      */
     PCAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
-    if (apicIsEnabled(pVCpu))
+    if (APICIsEnabled(pVCpu))
     { /* likely */ }
     else
@@ -1997 +1998 @@
      */
     PCAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
-    if (apicIsEnabled(pVCpu))
+    if (APICIsEnabled(pVCpu))
     { /* likely */ }
     else
@@ -2347 +2348 @@
 VMMDECL(int) APICSetTpr(PVMCPU pVCpu, uint8_t u8Tpr)
 {
-    if (apicIsEnabled(pVCpu))
+    if (APICIsEnabled(pVCpu))
         return VBOXSTRICTRC_VAL(apicSetTprEx(pVCpu, u8Tpr, false /* fForceX2ApicBehaviour */));
     return VERR_PDM_NO_APIC_INSTANCE;
@@ -2390 +2391 @@
 {
     VMCPU_ASSERT_EMT(pVCpu);
-    if (apicIsEnabled(pVCpu))
+    if (APICIsEnabled(pVCpu))
     {
         PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
@@ -2427 +2428 @@
 
     PVMCPU pVCpu = &pVM->aCpus[0];
-    if (apicIsEnabled(pVCpu))
+    if (APICIsEnabled(pVCpu))
     {
         PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
@@ -2459 +2460 @@
      * If the APIC isn't enabled, do nothing and pretend success.
      */
-    if (apicIsEnabled(&pVM->aCpus[0]))
+    if (APICIsEnabled(&pVM->aCpus[0]))
     { /* likely */ }
     else
@@ -2508 +2509 @@
 
     /* If the APIC is enabled, the interrupt is subject to LVT programming. */
-    if (apicIsEnabled(pVCpu))
+    if (APICIsEnabled(pVCpu))
     {
         PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
@@ -2675 +2676 @@
 
     PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
-    bool const fApicHwEnabled = apicIsEnabled(pVCpu);
+    bool const fApicHwEnabled = APICIsEnabled(pVCpu);
     if (   fApicHwEnabled
         && pXApicPage->svr.u.fApicSoftwareEnable)

trunk/src/VBox/VMM/VMMAll/PDMAll.cpp

@@ -248 +248 @@
  * Returns the presence of an IO-APIC.
  *
- * @returns VBox true if an IO-APIC is present.
+ * @returns true if an IO-APIC is present.
  * @param   pVM         The cross context VM structure.
  */
@@ -254 +254 @@
 {
     return pVM->pdm.s.IoApic.CTX_SUFF(pDevIns) != NULL;
+}
+
+
+/**
+ * Returns the presence of an APIC.
+ *
+ * @returns true if an APIC is present.
+ * @param   pVM         The cross context VM structure.
+ */
+VMM_INT_DECL(bool) PDMHasApic(PVM pVM)
+{
+    return pVM->pdm.s.Apic.CTX_SUFF(pDevIns) != NULL;
 }