VirtualBox

Changeset 65059 in vbox for trunk/src


Ignore:
Timestamp:
Jan 3, 2017 10:41:55 AM (8 years ago)
Author:
vboxsync
Message:

Audio/DevHDA.cpp: Implemented register descriptor flags to check if a register can be written while the stream's RUN bit is set. This also should make most of the register write locks obsolete.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/Devices/Audio/DevHDA.cpp

    r65038 r65059  
    10861086#define HDA_REG_IDX_LOCAL(abbrev)   0, #abbrev
    10871087
     1088/** No register description (RD) flags defined. */
     1089#define HDA_RD_FLAG_NONE           UINT32_C(0)
     1090/** Writes to SD are allowed while RUN bit is set. */
     1091#define HDA_RD_FLAG_SD_WRITE_RUN   RT_BIT(0)
     1092
    10881093/** Emits a single audio stream register set (e.g. OSD0) at a specified offset. */
    10891094#define HDA_REG_MAP_STRM(offset, name) \
    1090     /* offset        size     read mask   write mask  read callback   write callback     index + abbrev                  description */ \
    1091     /* -------       -------  ----------  ----------  --------------  -----------------  ------------------------------  ----------- */ \
     1095    /* offset        size     read mask   write mask  flags                     read callback   write callback     index + abbrev                 description */ \
     1096    /* -------       -------  ----------  ----------  ------------------------- --------------  -----------------  -----------------------------  ----------- */ \
    10921097    /* Offset 0x80 (SD0) */ \
    1093     { offset,        0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , HDA_REG_IDX_STRM(name, CTL)  , #name " Stream Descriptor Control" }, \
     1098    { offset,        0x00003, 0x00FF001F, 0x00F0001F, HDA_RD_FLAG_SD_WRITE_RUN, hdaRegReadU24 , hdaRegWriteSDCTL , HDA_REG_IDX_STRM(name, CTL)  , #name " Stream Descriptor Control" }, \
    10941099    /* Offset 0x83 (SD0) */ \
    1095     { offset + 0x3,  0x00001, 0x0000003C, 0x0000001C, hdaRegReadU8  , hdaRegWriteSDSTS , HDA_REG_IDX_STRM(name, STS)  , #name " Status" }, \
     1100    { offset + 0x3,  0x00001, 0x0000003C, 0x0000001C, HDA_RD_FLAG_SD_WRITE_RUN, hdaRegReadU8  , hdaRegWriteSDSTS , HDA_REG_IDX_STRM(name, STS)  , #name " Status" }, \
    10961101    /* Offset 0x84 (SD0) */ \
    1097     { offset + 0x4,  0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadLPIB, hdaRegWriteU32   , HDA_REG_IDX_STRM(name, LPIB) , #name " Link Position In Buffer" }, \
     1102    { offset + 0x4,  0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE,         hdaRegReadLPIB, hdaRegWriteU32    , HDA_REG_IDX_STRM(name, LPIB) , #name " Link Position In Buffer" }, \
    10981103    /* Offset 0x88 (SD0) */ \
    1099     { offset + 0x8,  0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32, hdaRegWriteSDCBL  , HDA_REG_IDX_STRM(name, CBL)  , #name " Cyclic Buffer Length" }, \
     1104    { offset + 0x8,  0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE,         hdaRegReadU32 , hdaRegWriteSDCBL  , HDA_REG_IDX_STRM(name, CBL)  , #name " Cyclic Buffer Length" }, \
    11001105    /* Offset 0x8C (SD0) */ \
    1101     { offset + 0xC,  0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16, hdaRegWriteSDLVI  , HDA_REG_IDX_STRM(name, LVI)  , #name " Last Valid Index" }, \
     1106    { offset + 0xC,  0x00002, 0x0000FFFF, 0x0000FFFF, HDA_RD_FLAG_NONE,         hdaRegReadU16 , hdaRegWriteSDLVI  , HDA_REG_IDX_STRM(name, LVI)  , #name " Last Valid Index" }, \
    11021107    /* Reserved: FIFO Watermark. ** @todo Document this! */ \
    1103     { offset + 0xE,  0x00002, 0x00000007, 0x00000007, hdaRegReadU16, hdaRegWriteSDFIFOW, HDA_REG_IDX_STRM(name, FIFOW), #name " FIFO Watermark" }, \
     1108    { offset + 0xE,  0x00002, 0x00000007, 0x00000007, HDA_RD_FLAG_NONE,         hdaRegReadU16 , hdaRegWriteSDFIFOW, HDA_REG_IDX_STRM(name, FIFOW), #name " FIFO Watermark" }, \
    11041109    /* Offset 0x90 (SD0) */ \
    1105     { offset + 0x10, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16, hdaRegWriteSDFIFOS, HDA_REG_IDX_STRM(name, FIFOS), #name " FIFO Size" }, \
     1110    { offset + 0x10, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE,         hdaRegReadU16 , hdaRegWriteSDFIFOS, HDA_REG_IDX_STRM(name, FIFOS), #name " FIFO Size" }, \
    11061111    /* Offset 0x92 (SD0) */ \
    1107     { offset + 0x12, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16, hdaRegWriteSDFMT  , HDA_REG_IDX_STRM(name, FMT)  , #name " Stream Format" }, \
     1112    { offset + 0x12, 0x00002, 0x00007F7F, 0x00007F7F, HDA_RD_FLAG_NONE,         hdaRegReadU16 , hdaRegWriteSDFMT  , HDA_REG_IDX_STRM(name, FMT)  , #name " Stream Format" }, \
    11081113    /* Reserved: 0x94 - 0x98. */ \
    11091114    /* Offset 0x98 (SD0) */ \
    1110     { offset + 0x18, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32, hdaRegWriteSDBDPL , HDA_REG_IDX_STRM(name, BDPL) , #name " Buffer Descriptor List Pointer-Lower Base Address" }, \
     1115    { offset + 0x18, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE,         hdaRegReadU32 , hdaRegWriteSDBDPL , HDA_REG_IDX_STRM(name, BDPL) , #name " Buffer Descriptor List Pointer-Lower Base Address" }, \
    11111116    /* Offset 0x9C (SD0) */ \
    1112     { offset + 0x1C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32, hdaRegWriteSDBDPU , HDA_REG_IDX_STRM(name, BDPU) , #name " Buffer Descriptor List Pointer-Upper Base Address" }
     1117    { offset + 0x1C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE,         hdaRegReadU32 , hdaRegWriteSDBDPU , HDA_REG_IDX_STRM(name, BDPU) , #name " Buffer Descriptor List Pointer-Upper Base Address" }
    11131118
    11141119/** Defines a single audio stream register set (e.g. OSD0). */
    … …  
    11271132    /** Writable bits. */
    11281133    uint32_t    writable;
     1134    /** Register descriptor (RD) flags of type HDA_RD_FLAG_.
     1135     *  These are used to specify the handling (read/write)
     1136     *  policy of the register. */
     1137    uint32_t    fFlags;
    11291138    /** Read callback. */
    11301139    int       (*pfnRead)(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
    … …  
    11401149
    11411150{
    1142     /* offset  size     read mask   write mask  read callback            write callback         index + abbrev   */
    1143     /*-------  -------  ----------  ----------  -----------------------  ---------------------- ---------------- */
    1144     { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadU16          , hdaRegWriteUnimpl     , HDA_REG_IDX(GCAP)         }, /* Global Capabilities */
    1145     { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8           , hdaRegWriteUnimpl     , HDA_REG_IDX(VMIN)         }, /* Minor Version */
    1146     { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8           , hdaRegWriteUnimpl     , HDA_REG_IDX(VMAJ)         }, /* Major Version */
    1147     { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16          , hdaRegWriteU16        , HDA_REG_IDX(OUTPAY)       }, /* Output Payload Capabilities */
    1148     { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16          , hdaRegWriteUnimpl     , HDA_REG_IDX(INPAY)        }, /* Input Payload Capabilities */
    1149     { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadU32          , hdaRegWriteGCTL       , HDA_REG_IDX(GCTL)         }, /* Global Control */
    1150     { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16          , hdaRegWriteU16        , HDA_REG_IDX(WAKEEN)       }, /* Wake Enable */
    1151     { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8           , hdaRegWriteSTATESTS   , HDA_REG_IDX(STATESTS)     }, /* State Change Status */
    1152     { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimpl       , hdaRegWriteUnimpl     , HDA_REG_IDX(GSTS)         }, /* Global Status */
    1153     { 0x00018, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16          , hdaRegWriteU16        , HDA_REG_IDX(OUTSTRMPAY)   }, /* Output Stream Payload Capability */
    1154     { 0x0001A, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16          , hdaRegWriteUnimpl     , HDA_REG_IDX(INSTRMPAY)    }, /* Input Stream Payload Capability */
    1155     { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32          , hdaRegWriteINTCTL     , HDA_REG_IDX(INTCTL)       }, /* Interrupt Control */
    1156     { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadU32          , hdaRegWriteUnimpl     , HDA_REG_IDX(INTSTS)       }, /* Interrupt Status */
    1157     { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadWALCLK       , hdaRegWriteUnimpl     , HDA_REG_IDX_LOCAL(WALCLK) }, /* Wall Clock Counter */
    1158     { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32          , hdaRegWriteU32        , HDA_REG_IDX(SSYNC)        }, /* Stream Synchronization */
    1159     { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32          , hdaRegWriteBase       , HDA_REG_IDX(CORBLBASE)    }, /* CORB Lower Base Address */
    1160     { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32          , hdaRegWriteBase       , HDA_REG_IDX(CORBUBASE)    }, /* CORB Upper Base Address */
    1161     { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16          , hdaRegWriteCORBWP     , HDA_REG_IDX(CORBWP)       }, /* CORB Write Pointer */
    1162     { 0x0004A, 0x00002, 0x000080FF, 0x000080FF, hdaRegReadU16          , hdaRegWriteCORBRP     , HDA_REG_IDX(CORBRP)       }, /* CORB Read Pointer */
    1163     { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8           , hdaRegWriteCORBCTL    , HDA_REG_IDX(CORBCTL)      }, /* CORB Control */
    1164     { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8           , hdaRegWriteCORBSTS    , HDA_REG_IDX(CORBSTS)      }, /* CORB Status */
    1165     { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8           , hdaRegWriteUnimpl     , HDA_REG_IDX(CORBSIZE)     }, /* CORB Size */
    1166     { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32          , hdaRegWriteBase       , HDA_REG_IDX(RIRBLBASE)    }, /* RIRB Lower Base Address */
    1167     { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32          , hdaRegWriteBase       , HDA_REG_IDX(RIRBUBASE)    }, /* RIRB Upper Base Address */
    1168     { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8           , hdaRegWriteRIRBWP     , HDA_REG_IDX(RIRBWP)       }, /* RIRB Write Pointer */
    1169     { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16          , hdaRegWriteU16        , HDA_REG_IDX(RINTCNT)      }, /* Response Interrupt Count */
    1170     { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8           , hdaRegWriteU8         , HDA_REG_IDX(RIRBCTL)      }, /* RIRB Control */
    1171     { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8           , hdaRegWriteRIRBSTS    , HDA_REG_IDX(RIRBSTS)      }, /* RIRB Status */
    1172     { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8           , hdaRegWriteUnimpl     , HDA_REG_IDX(RIRBSIZE)     }, /* RIRB Size */
    1173     { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32          , hdaRegWriteU32        , HDA_REG_IDX(IC)           }, /* Immediate Command */
    1174     { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32          , hdaRegWriteUnimpl     , HDA_REG_IDX(IR)           }, /* Immediate Response */
    1175     { 0x00068, 0x00002, 0x00000002, 0x00000002, hdaRegReadIRS          , hdaRegWriteIRS        , HDA_REG_IDX(IRS)          }, /* Immediate Command Status */
    1176     { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32          , hdaRegWriteBase       , HDA_REG_IDX(DPLBASE)      }, /* DMA Position Lower Base */
    1177     { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32          , hdaRegWriteBase       , HDA_REG_IDX(DPUBASE)      }, /* DMA Position Upper Base */
     1151    /* offset  size     read mask   write mask  flags             read callback     write callback       index + abbrev              */
     1152    /*-------  -------  ----------  ----------  ----------------- ----------------  -------------------     ------------------------ */
     1153    { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16   , hdaRegWriteUnimpl  , HDA_REG_IDX(GCAP)         }, /* Global Capabilities */
     1154    { 0x00002, 0x00001, 0x000000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8    , hdaRegWriteUnimpl  , HDA_REG_IDX(VMIN)         }, /* Minor Version */
     1155    { 0x00003, 0x00001, 0x000000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8    , hdaRegWriteUnimpl  , HDA_REG_IDX(VMAJ)         }, /* Major Version */
     1156    { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16   , hdaRegWriteU16     , HDA_REG_IDX(OUTPAY)       }, /* Output Payload Capabilities */
     1157    { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16   , hdaRegWriteUnimpl  , HDA_REG_IDX(INPAY)        }, /* Input Payload Capabilities */
     1158    { 0x00008, 0x00004, 0x00000103, 0x00000103, HDA_RD_FLAG_NONE, hdaRegReadU32   , hdaRegWriteGCTL    , HDA_REG_IDX(GCTL)         }, /* Global Control */
     1159    { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, HDA_RD_FLAG_NONE, hdaRegReadU16   , hdaRegWriteU16     , HDA_REG_IDX(WAKEEN)       }, /* Wake Enable */
     1160    { 0x0000e, 0x00002, 0x00000007, 0x00000007, HDA_RD_FLAG_NONE, hdaRegReadU8    , hdaRegWriteSTATESTS, HDA_REG_IDX(STATESTS)     }, /* State Change Status */
     1161    { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadUnimpl, hdaRegWriteUnimpl  , HDA_REG_IDX(GSTS)         }, /* Global Status */
     1162    { 0x00018, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16   , hdaRegWriteU16     , HDA_REG_IDX(OUTSTRMPAY)   }, /* Output Stream Payload Capability */
     1163    { 0x0001A, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16   , hdaRegWriteUnimpl  , HDA_REG_IDX(INSTRMPAY)    }, /* Input Stream Payload Capability */
     1164    { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, HDA_RD_FLAG_NONE, hdaRegReadU32   , hdaRegWriteINTCTL  , HDA_REG_IDX(INTCTL)       }, /* Interrupt Control */
     1165    { 0x00024, 0x00004, 0xC00000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU32   , hdaRegWriteUnimpl  , HDA_REG_IDX(INTSTS)       }, /* Interrupt Status */
     1166    { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadWALCLK, hdaRegWriteUnimpl  , HDA_REG_IDX_LOCAL(WALCLK) }, /* Wall Clock Counter */
     1167    { 0x00034, 0x00004, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU32   , hdaRegWriteU32     , HDA_REG_IDX(SSYNC)        }, /* Stream Synchronization */
     1168    { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE, hdaRegReadU32   , hdaRegWriteBase    , HDA_REG_IDX(CORBLBASE)    }, /* CORB Lower Base Address */
     1169    { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32   , hdaRegWriteBase    , HDA_REG_IDX(CORBUBASE)    }, /* CORB Upper Base Address */
     1170    { 0x00048, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU16   , hdaRegWriteCORBWP  , HDA_REG_IDX(CORBWP)       }, /* CORB Write Pointer */
     1171    { 0x0004A, 0x00002, 0x000080FF, 0x000080FF, HDA_RD_FLAG_NONE, hdaRegReadU16   , hdaRegWriteCORBRP  , HDA_REG_IDX(CORBRP)       }, /* CORB Read Pointer */
     1172    { 0x0004C, 0x00001, 0x00000003, 0x00000003, HDA_RD_FLAG_NONE, hdaRegReadU8    , hdaRegWriteCORBCTL , HDA_REG_IDX(CORBCTL)      }, /* CORB Control */
     1173    { 0x0004D, 0x00001, 0x00000001, 0x00000001, HDA_RD_FLAG_NONE, hdaRegReadU8    , hdaRegWriteCORBSTS , HDA_REG_IDX(CORBSTS)      }, /* CORB Status */
     1174    { 0x0004E, 0x00001, 0x000000F3, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8    , hdaRegWriteUnimpl  , HDA_REG_IDX(CORBSIZE)     }, /* CORB Size */
     1175    { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE, hdaRegReadU32   , hdaRegWriteBase    , HDA_REG_IDX(RIRBLBASE)    }, /* RIRB Lower Base Address */
     1176    { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32   , hdaRegWriteBase    , HDA_REG_IDX(RIRBUBASE)    }, /* RIRB Upper Base Address */
     1177    { 0x00058, 0x00002, 0x000000FF, 0x00008000, HDA_RD_FLAG_NONE, hdaRegReadU8    , hdaRegWriteRIRBWP  , HDA_REG_IDX(RIRBWP)       }, /* RIRB Write Pointer */
     1178    { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU16   , hdaRegWriteU16     , HDA_REG_IDX(RINTCNT)      }, /* Response Interrupt Count */
     1179    { 0x0005C, 0x00001, 0x00000007, 0x00000007, HDA_RD_FLAG_NONE, hdaRegReadU8    , hdaRegWriteU8      , HDA_REG_IDX(RIRBCTL)      }, /* RIRB Control */
     1180    { 0x0005D, 0x00001, 0x00000005, 0x00000005, HDA_RD_FLAG_NONE, hdaRegReadU8    , hdaRegWriteRIRBSTS , HDA_REG_IDX(RIRBSTS)      }, /* RIRB Status */
     1181    { 0x0005E, 0x00001, 0x000000F3, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8    , hdaRegWriteUnimpl  , HDA_REG_IDX(RIRBSIZE)     }, /* RIRB Size */
     1182    { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32   , hdaRegWriteU32     , HDA_REG_IDX(IC)           }, /* Immediate Command */
     1183    { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32   , hdaRegWriteUnimpl  , HDA_REG_IDX(IR)           }, /* Immediate Response */
     1184    { 0x00068, 0x00002, 0x00000002, 0x00000002, HDA_RD_FLAG_NONE, hdaRegReadIRS   , hdaRegWriteIRS     , HDA_REG_IDX(IRS)          }, /* Immediate Command Status */
     1185    { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, HDA_RD_FLAG_NONE, hdaRegReadU32   , hdaRegWriteBase    , HDA_REG_IDX(DPLBASE)      }, /* DMA Position Lower Base */
     1186    { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32   , hdaRegWriteBase    , HDA_REG_IDX(DPUBASE)      }, /* DMA Position Upper Base */
    11781187    /* 4 Serial Data In (SDI). */
    11791188    HDA_REG_MAP_DEF_STREAM(0, SD0),
    … …  
    12511260
    12521261
    1253 #ifdef IN_RING3
    12541262/**
    12551263 * Retrieves the number of bytes of a FIFOW register.
    … …  
    12731281
    12741282
     1283#ifdef IN_RING3
    12751284DECLINLINE(uint32_t) hdaStreamUpdateLPIB(PHDASTATE pThis, PHDASTREAM pStream, uint32_t u32LPIB)
    12761285{
    … …  
    13531362    return rc;
    13541363}
     1364#endif /* IN_RING3 */
    13551365
    13561366
    … …  
    13601370 * @return  Pointer to HDA stream, or NULL if none found.
    13611371 */
    1362 DECLINLINE(PHDASTREAM) hdaStreamFromSD(PHDASTATE pThis, uint8_t uSD)
     1372DECLINLINE(PHDASTREAM) hdaStreamGetFromSD(PHDASTATE pThis, uint8_t uSD)
    13631373{
    13641374    AssertPtrReturn(pThis, NULL);
    … …  
    13661376
    13671377    if (uSD >= HDA_MAX_STREAMS)
     1378    {
     1379        AssertMsgFailed(("Invalid / non-handled SD%RU8\n", uSD));
    13681380        return NULL;
     1381    }
    13691382
    13701383    return &pThis->aStreams[uSD];
    … …  
    13831396
    13841397    /** @todo Do something with the channel mapping here? */
    1385     return hdaStreamFromSD(pThis, pSink->uSD);
     1398    return hdaStreamGetFromSD(pThis, pSink->uSD);
    13861399}
    13871400
    … …  
    14081421    return PDMAUDIODIR_OUT;
    14091422}
    1410 #endif /* IN_RING3 */
    14111423
    14121424
    … …  
    18031815    LogFunc(("[SD%RU8]: Reset\n", uSD));
    18041816
    1805     /*
    1806      * Enter reset state.
    1807      */
    1808     Assert(ASMAtomicReadBool(&pStream->State.fInReset) == false); /* No nested calls. */
    1809     ASMAtomicXchgBool(&pStream->State.fInReset, true);
    1810 
    18111817    int rc2;
    18121818#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
    … …  
    18561862    rc2 = hdaStreamInit(pThis, pStream, uSD);
    18571863    AssertRC(rc2);
    1858 
    1859     /* Exit reset state. */
    1860     ASMAtomicXchgBool(&pStream->State.fInReset, false);
    18611864}
    18621865
    … …  
    22982301        return VINF_SUCCESS;
    22992302
    2300     PHDASTREAM pStream = hdaStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, CBL, iReg));
     2303    PHDASTREAM pStream = hdaStreamGetFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, CBL, iReg));
    23012304    if (!pStream)
    23022305    {
    2303         LogFunc(("[SD%RU8]: Warning: Changing SDCBL on non-attached stream (0x%x)\n", HDA_SD_NUM_FROM_REG(pThis, CTL, iReg), u32Value));
     2306        LogFunc(("[SD%RU8]: Warning: Changing SDCBL on non-attached stream (0x%x)\n",
     2307                 HDA_SD_NUM_FROM_REG(pThis, CTL, iReg), u32Value));
    23042308        return hdaRegWriteU32(pThis, iReg, u32Value);
    23052309    }
    2306 
    2307     int rc2 = hdaRegWriteSDLock(pThis, pStream, iReg, u32Value);
    2308     AssertRC(rc2);
    23092310
    23102311    pStream->u32CBL = u32Value;
    … …  
    23142315    pStream->State.uCurBDLE = 0;
    23152316
    2316     rc2 = hdaRegWriteU32(pThis, iReg, u32Value);
     2317    int rc2 = hdaRegWriteU32(pThis, iReg, u32Value);
    23172318    AssertRC(rc2);
    23182319
    23192320    LogFlowFunc(("[SD%RU8]: CBL=%RU32\n", pStream->u8SD, u32Value));
    2320     hdaRegWriteSDUnlock(pStream);
    23212321
    23222322    return VINF_SUCCESS; /* Always return success to the MMIO handler. */
    … …  
    23722372    /* Assign new values. */
    23732373    pTag->uTag  = uTag;
    2374     pTag->pStrm = hdaStreamFromSD(pThis, uSD);
     2374    pTag->pStrm = hdaStreamGetFromSD(pThis, uSD);
    23752375
    23762376    PHDASTREAM pStream = pTag->pStrm;
    … …  
    23862386        Assert(!fInRun && !fRun);
    23872387
     2388        /* Exit reset state. */
     2389        ASMAtomicXchgBool(&pStream->State.fInReset, false);
     2390
    23882391        /* Report that we're done resetting this stream by clearing SRST. */
    23892392        HDA_STREAM_REG(pThis, CTL, uSD) &= ~HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST);
    23902393
    2391         LogFunc(("[SD%RU8]: Guest initiated exit of stream reset\n", uSD));
     2394        LogFunc(("[SD%RU8]: Reset exit\n", uSD));
    23922395    }
    23932396    else if (fReset)
    … …  
    23962399        Assert(!fInRun && !fRun);
    23972400
    2398         LogFunc(("[SD%RU8]: Guest initiated enter to stream reset\n", pStream->u8SD));
     2401        LogFunc(("[SD%RU8]: Reset enter\n", pStream->u8SD));
     2402
     2403        /* Enter reset state. */
     2404        Assert(ASMAtomicReadBool(&pStream->State.fInReset) == false); /* No nested calls. */
     2405        ASMAtomicXchgBool(&pStream->State.fInReset, true);
    23992406
    24002407        hdaStreamReset(pThis, pStream);
    … …  
    24102417            LogFunc(("[SD%RU8]: State changed (fRun=%RTbool)\n", pStream->u8SD, fRun));
    24112418
    2412             hdaStreamEnable(pThis, pStream, fRun /* fEnable */);
    2413 
    24142419            if (fRun)
    24152420            {
    2416                 /* (Re-)Fetch the current BDLE entry. */
     2421                /* Make sure to first fetch the current BDLE before enabling the stream below. */
    24172422                rc2 = hdaBDLEFetch(pThis, &pStream->State.BDLE, pStream->u64BDLBase, pStream->State.uCurBDLE);
    24182423                AssertRC(rc2);
    24192424            }
     2425
     2426            hdaStreamEnable(pThis, pStream, fRun /* fEnable */);
    24202427        }
    24212428    }
    … …  
    24562463    uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, LVI, iReg);
    24572464
    2458     PHDASTREAM pStream = hdaStreamFromSD(pThis, uSD);
     2465    PHDASTREAM pStream = hdaStreamGetFromSD(pThis, uSD);
    24592466    if (!pStream)
    24602467    {
    … …  
    24632470    }
    24642471
    2465     int rc2 = hdaRegWriteSDLock(pThis, pStream, iReg, u32Value);
    2466     if (RT_SUCCESS(rc2))
    2467     {
    2468         /** @todo Validate LVI. */
    2469         pStream->u16LVI = u32Value;
    2470         LogFunc(("[SD%RU8]: Updating LVI to %RU32\n", uSD, pStream->u16LVI));
    2471 
    2472         /* Reset BDLE state. */
    2473         RT_ZERO(pStream->State.BDLE);
    2474         pStream->State.uCurBDLE = 0;
    2475 
    2476         rc2 = hdaRegWriteU16(pThis, iReg, u32Value);
    2477         AssertRC(rc2);
    2478 
    2479         hdaRegWriteSDUnlock(pStream);
    2480     }
    2481     else
    2482         LogRel(("HDA: Warning: Guest tried to write LVI to running stream #%RU8, ignoring\n", uSD));
    2483 
    2484     return VINF_SUCCESS; /* Always return success to the MMIO handler. */
    2485 
    2486 #else  /* !IN_RING3 */
    2487     RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
    2488     return VINF_IOM_R3_MMIO_WRITE;
    2489 #endif /* IN_RING3 */
    2490 }
    2491 
    2492 static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
    2493 {
    2494 #ifdef IN_RING3
    2495     uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, FIFOW, iReg);
    2496 
    2497     if (hdaGetDirFromSD(uSD) != PDMAUDIODIR_IN) /* FIFOW for input streams only. */
    2498     {
    2499         LogRel(("HDA: Warning: Guest tried to write read-only FIFOW to output stream #%RU8, ignoring\n", uSD));
    2500         return VINF_SUCCESS;
    2501     }
    2502 
    2503     PHDASTREAM pStream = hdaStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, FIFOW, iReg));
    2504     if (!pStream)
    2505     {
    2506         AssertMsgFailed(("[SD%RU8]: Warning: Changing FIFOW on non-attached stream (0x%x)\n", uSD, u32Value));
    2507         return hdaRegWriteU16(pThis, iReg, u32Value);
    2508     }
    2509 
    2510     int rc2 = hdaRegWriteSDLock(pThis, pStream, iReg, u32Value);
    2511     if (RT_SUCCESS(rc2))
    2512     {
    2513         uint32_t u32FIFOW = 0;
    2514 
    2515         switch (u32Value)
    2516         {
    2517             case HDA_SDFIFOW_8B:
    2518             case HDA_SDFIFOW_16B:
    2519             case HDA_SDFIFOW_32B:
    2520                 u32FIFOW = u32Value;
    2521                 break;
    2522             default:
    2523                 LogRel(("HDA: Warning: Guest tried write unsupported FIFOW (0x%x) to stream #%RU8, defaulting to 32 bytes\n",
    2524                         u32Value, uSD));
    2525                 AssertFailed();
    2526                 u32FIFOW = HDA_SDFIFOW_32B;
    2527                 break;
    2528         }
    2529 
    2530         if (u32FIFOW)
    2531         {
    2532             pStream->u16FIFOW = hdaSDFIFOWToBytes(u32FIFOW);
    2533             LogFunc(("[SD%RU8]: Updating FIFOW to %RU32 bytes\n", uSD, pStream->u16FIFOW));
    2534 
    2535             rc2 = hdaRegWriteU16(pThis, iReg, u32FIFOW);
    2536             AssertRC(rc2);
    2537         }
    2538 
    2539         hdaRegWriteSDUnlock(pStream);
    2540     }
    2541     else
    2542         LogRel(("HDA: Warning: Guest tried to write FIFOW to running stream #%RU8, ignoring\n", uSD));
     2472    /** @todo Validate LVI. */
     2473    pStream->u16LVI = u32Value;
     2474    LogFunc(("[SD%RU8]: Updating LVI to %RU16\n", uSD, pStream->u16LVI));
     2475
     2476    /* Reset BDLE state. */
     2477    RT_ZERO(pStream->State.BDLE);
     2478    pStream->State.uCurBDLE = 0;
     2479
     2480    int rc2 = hdaRegWriteU16(pThis, iReg, u32Value);
     2481    AssertRC(rc2);
    25432482
    25442483    return VINF_SUCCESS; /* Always return success to the MMIO handler. */
    … …  
    25492488}
    25502489
     2490static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
     2491{
     2492#ifdef IN_RING3
     2493    uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, FIFOW, iReg);
     2494
     2495    if (hdaGetDirFromSD(uSD) != PDMAUDIODIR_IN) /* FIFOW for input streams only. */
     2496    {
     2497        LogRel(("HDA: Warning: Guest tried to write read-only FIFOW to output stream #%RU8, ignoring\n", uSD));
     2498        return VINF_SUCCESS;
     2499    }
     2500
     2501    PHDASTREAM pStream = hdaStreamGetFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, FIFOW, iReg));
     2502    if (!pStream)
     2503    {
     2504        AssertMsgFailed(("[SD%RU8]: Warning: Changing FIFOW on non-attached stream (0x%x)\n", uSD, u32Value));
     2505        return hdaRegWriteU16(pThis, iReg, u32Value);
     2506    }
     2507
     2508    uint32_t u32FIFOW = 0;
     2509
     2510    switch (u32Value)
     2511    {
     2512        case HDA_SDFIFOW_8B:
     2513        case HDA_SDFIFOW_16B:
     2514        case HDA_SDFIFOW_32B:
     2515            u32FIFOW = u32Value;
     2516            break;
     2517        default:
     2518            LogRel(("HDA: Warning: Guest tried write unsupported FIFOW (0x%x) to stream #%RU8, defaulting to 32 bytes\n",
     2519                    u32Value, uSD));
     2520            AssertFailed();
     2521            u32FIFOW = HDA_SDFIFOW_32B;
     2522            break;
     2523    }
     2524
     2525    if (u32FIFOW)
     2526    {
     2527        pStream->u16FIFOW = hdaSDFIFOWToBytes(u32FIFOW);
     2528        LogFunc(("[SD%RU8]: Updating FIFOW to %RU32 bytes\n", uSD, pStream->u16FIFOW));
     2529
     2530        int rc2 = hdaRegWriteU16(pThis, iReg, u32FIFOW);
     2531        AssertRC(rc2);
     2532    }
     2533
     2534    return VINF_SUCCESS; /* Always return success to the MMIO handler. */
     2535#else  /* !IN_RING3 */
     2536    RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
     2537    return VINF_IOM_R3_MMIO_WRITE;
     2538#endif /* IN_RING3 */
     2539}
     2540
    25512541/**
    25522542 * @note This method could be called for changing value on Output Streams only (ICH6 datasheet 18.2.39).
    … …  
    25632553    }
    25642554
    2565     PHDASTREAM pStream = hdaStreamFromSD(pThis, uSD);
     2555    PHDASTREAM pStream = hdaStreamGetFromSD(pThis, uSD);
    25662556    if (!pStream)
    25672557    {
    … …  
    25702560    }
    25712561
    2572     int rc2 = hdaRegWriteSDLock(pThis, pStream, iReg, u32Value);
    2573     if (RT_SUCCESS(rc2))
    2574     {
    2575         uint32_t u32FIFOS = 0;
    2576 
    2577         switch(u32Value)
    2578         {
    2579             case HDA_SDOFIFO_16B:
    2580             case HDA_SDOFIFO_32B:
    2581             case HDA_SDOFIFO_64B:
    2582             case HDA_SDOFIFO_128B:
    2583             case HDA_SDOFIFO_192B:
    2584             case HDA_SDOFIFO_256B:
    2585                 u32FIFOS = u32Value;
    2586                 break;
    2587 
    2588             default:
    2589                 LogRel(("HDA: Warning: Guest tried write unsupported FIFOS (0x%x) to stream #%RU8, defaulting to 192 bytes\n",
    2590                         u32Value, uSD));
    2591                 AssertFailed();
    2592                 u32FIFOS = HDA_SDOFIFO_192B;
    2593                 break;
    2594         }
    2595 
    2596         if (u32FIFOS)
    2597         {
    2598             pStream->u16FIFOS = u32FIFOS + 1;
    2599             LogFunc(("[SD%RU8]: Updating FIFOS to %RU32 bytes\n", uSD, pStream->u16FIFOS));
    2600 
    2601             rc2 = hdaRegWriteU16(pThis, iReg, u32FIFOS);
    2602             AssertRC(rc2);
    2603         }
    2604 
    2605         hdaRegWriteSDUnlock(pStream);
    2606     }
    2607     else
    2608         LogRel(("HDA: Warning: Guest tried to write FIFOS to running stream #%RU8, ignoring\n", uSD));
    2609 
    2610      return VINF_SUCCESS; /* Always return success to the MMIO handler. */
     2562    uint32_t u32FIFOS = 0;
     2563
     2564    switch(u32Value)
     2565    {
     2566        case HDA_SDOFIFO_16B:
     2567        case HDA_SDOFIFO_32B:
     2568        case HDA_SDOFIFO_64B:
     2569        case HDA_SDOFIFO_128B:
     2570        case HDA_SDOFIFO_192B:
     2571        case HDA_SDOFIFO_256B:
     2572            u32FIFOS = u32Value;
     2573            break;
     2574
     2575        default:
     2576            LogRel(("HDA: Warning: Guest tried write unsupported FIFOS (0x%x) to stream #%RU8, defaulting to 192 bytes\n",
     2577                    u32Value, uSD));
     2578            AssertFailed();
     2579            u32FIFOS = HDA_SDOFIFO_192B;
     2580            break;
     2581    }
     2582
     2583    if (u32FIFOS)
     2584    {
     2585        pStream->u16FIFOS = u32FIFOS + 1;
     2586        LogFunc(("[SD%RU8]: Updating FIFOS to %RU32 bytes\n", uSD, pStream->u16FIFOS));
     2587
     2588        int rc2 = hdaRegWriteU16(pThis, iReg, u32FIFOS);
     2589        AssertRC(rc2);
     2590    }
     2591
     2592    return VINF_SUCCESS; /* Always return success to the MMIO handler. */
    26112593#else  /* !IN_RING3 */
    26122594    RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
    … …  
    28632845        return VINF_SUCCESS; /* Always return success to the MMIO handler. */
    28642846
    2865     PHDASTREAM pStream = hdaStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, FMT, iReg));
     2847    PHDASTREAM pStream = hdaStreamGetFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, FMT, iReg));
    28662848    if (!pStream)
    28672849    {
    … …  
    28702852        return hdaRegWriteU16(pThis, iReg, u32Value);
    28712853    }
    2872 
    2873     int rcSem = hdaRegWriteSDLock(pThis, pStream, iReg, u32Value);
    2874     AssertRC(rcSem);
    28752854
    28762855    LogFunc(("[SD%RU8]: Hz=%RU32, Channels=%RU8, enmFmt=%RU32\n",
    … …  
    29642943    }
    29652944
    2966     if (RT_SUCCESS(rcSem))
    2967         hdaRegWriteSDUnlock(pStream);
    2968 
    29692945    return VINF_SUCCESS; /* Never return failure. */
    29702946#else /* !IN_RING3 */
    … …  
    29752951
    29762952/* Note: Will be called for both, BDPL and BDPU, registers. */
    2977 DECLINLINE(int) hdaRegWriteSDBDPX(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value, uint8_t u8Strm)
     2953DECLINLINE(int) hdaRegWriteSDBDPX(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value, uint8_t uSD)
    29782954{
    29792955#ifdef IN_RING3
    … …  
    29812957        return VINF_SUCCESS;
    29822958
    2983     PHDASTREAM pStream = hdaStreamFromSD(pThis, u8Strm);
     2959    int rc2 = hdaRegWriteU32(pThis, iReg, u32Value);
     2960    AssertRC(rc2);
     2961
     2962    PHDASTREAM pStream = hdaStreamGetFromSD(pThis, uSD);
    29842963    if (!pStream)
    2985     {
    2986         LogFunc(("[SD%RU8]: Warning: Changing SDBPL/SDBPU on non-attached stream (0x%x)\n", HDA_SD_NUM_FROM_REG(pThis, CTL, iReg), u32Value));
    2987         return hdaRegWriteU32(pThis, iReg, u32Value);
    2988     }
    2989 
    2990     int rc2 = hdaRegWriteSDLock(pThis, pStream, iReg, u32Value);
    2991     AssertRC(rc2);
    2992 
    2993     rc2 = hdaRegWriteU32(pThis, iReg, u32Value);
    2994     AssertRC(rc2);
     2964        return VINF_SUCCESS;
    29952965
    29962966    /* Update BDL base. */
    2997     pStream->u64BDLBase = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, u8Strm),
    2998                                       HDA_STREAM_REG(pThis, BDPU, u8Strm));
     2967    pStream->u64BDLBase = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, uSD),
     2968                                      HDA_STREAM_REG(pThis, BDPU, uSD));
     2969    AssertMsg(pStream->u64BDLBase, ("BDL base invalid\n"));
     2970
    29992971    /* Reset BDLE state. */
    30002972    RT_ZERO(pStream->State.BDLE);
    … …  
    30022974
    30032975    LogFlowFunc(("[SD%RU8]: BDLBase=0x%x\n", pStream->u8SD, pStream->u64BDLBase));
    3004     hdaRegWriteSDUnlock(pStream);
    30052976
    30062977    return VINF_SUCCESS; /* Always return success to the MMIO handler. */
    30072978#else  /* !IN_RING3 */
    3008     RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value); RT_NOREF_PV(u8Strm);
     2979    RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value); RT_NOREF_PV(uSD);
    30092980    return VINF_IOM_R3_MMIO_WRITE;
    30102981#endif /* IN_RING3 */
    … …  
    38443815        Assert(uSD < HDA_MAX_STREAMS);
    38453816
    3846         PHDASTREAM pStream = hdaStreamFromSD(pThis, uSD);
     3817        PHDASTREAM pStream = hdaStreamGetFromSD(pThis, uSD);
    38473818        if (pStream)
    38483819        {
    … …  
    49154886    if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
    49164887    {
    4917         LogRel2(("HDA: Warning: Access to register 0x%x is blocked while reset\n", idxRegDsc));
     4888        Log(("hdaWriteReg: Warning: Access to %s is blocked while controller is in reset mode\n", g_aHdaRegMap[idxRegDsc].abbrev));
     4889        LogRel2(("HDA: Warning: Access to register %s is blocked while controller is in reset mode\n",
     4890                 g_aHdaRegMap[idxRegDsc].abbrev));
    49184891        return VINF_SUCCESS;
     4892    }
     4893
     4894    /*
     4895     * Handle RD (register description) flags.
     4896     */
     4897
     4898    /* For SDI / SDO: Check if writes to those registers are allowed while SDCTL's RUN bit is set. */
     4899    if (idxRegDsc >= HDA_NUM_GENERAL_REGS)
     4900    {
     4901        const uint32_t uSDCTL = HDA_STREAM_REG(pThis, CTL, HDA_SD_NUM_FROM_REG(pThis, CTL, idxRegDsc));
     4902
     4903#ifdef LOG_ENABLED
     4904        PHDASTREAM pStream = hdaStreamGetFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, CTL, idxRegDsc));
     4905        Log3(("hdaWriteReg: %s: fInReset=%RTbool, %R[sdctl]\n",
     4906              g_aHdaRegMap[idxRegDsc].abbrev, pStream ? ASMAtomicReadBool(&pStream->State.fInReset) : false, uSDCTL));
     4907#endif
     4908        /*
     4909         * Some OSes (like Win 10 AU) violate the spec by writing stuff to registers which are not supposed to be be touched
     4910         * while SDCTL's RUN bit is set. So just ignore those values.
     4911         */
     4912
     4913            /* Is the RUN bit currently set? */
     4914        if (   RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))
     4915            /* Are writes to the register denied if RUN bit is set? */
     4916            && !(g_aHdaRegMap[idxRegDsc].fFlags & HDA_RD_FLAG_SD_WRITE_RUN))
     4917        {
     4918            Log(("hdaWriteReg: Warning: Access to %s is blocked! %R[sdctl]\n", g_aHdaRegMap[idxRegDsc].abbrev, uSDCTL));
     4919            LogRel2(("HDA: Warning: Access to register %s is blocked while the stream's RUN bit is set\n",
     4920                     g_aHdaRegMap[idxRegDsc].abbrev));
     4921            return VINF_SUCCESS;
     4922        }
    49194923    }
    49204924
    49214925#ifdef LOG_ENABLED
    49224926    uint32_t const idxRegMem   = g_aHdaRegMap[idxRegDsc].mem_idx;
    4923     uint32_t const u32CurValue = pThis->au32Regs[idxRegMem];
     4927    uint32_t const u32OldValue = pThis->au32Regs[idxRegMem];
    49244928#endif
    49254929    int rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32Value);
    49264930    Log3Func(("Written value %#x to %s[%d byte]; %x => %x%s\n", u32Value, g_aHdaRegMap[idxRegDsc].abbrev,
    4927               g_aHdaRegMap[idxRegDsc].size, u32CurValue, pThis->au32Regs[idxRegMem], pszLog));
    4928     RT_NOREF1(pszLog);
     4931              g_aHdaRegMap[idxRegDsc].size, u32OldValue, pThis->au32Regs[idxRegMem], pszLog));
     4932    RT_NOREF(pszLog);
    49294933    return rc;
    49304934}
    … …  
    53675371                    break;
    53685372
    5369                 PHDASTREAM pStrm = hdaStreamFromSD(pThis, uSD);
     5373                PHDASTREAM pStrm = hdaStreamGetFromSD(pThis, uSD);
    53705374                HDASTREAM  StreamDummy;
    53715375
    … …  
    54715475        for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
    54725476        {
    5473             PHDASTREAM pStream = hdaStreamFromSD(pThis, i);
     5477            PHDASTREAM pStream = hdaStreamGetFromSD(pThis, i);
    54745478            if (pStream)
    54755479            {
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