Changeset 6546 in vbox

Timestamp:

Jan 28, 2008 9:58:59 PM (17 years ago)

Author:

vboxsync

Message:

VBOX_WITH_NEW_PHYS_CODE changes mostly realted to REM. Killed a warning in cpu-exec.c.

Location:

trunk

Files:

• include/VBox/mm.h (modified) (4 diffs)
• include/VBox/pgm.h (modified) (4 diffs)
• include/VBox/rem.h (modified) (3 diffs)
• src/VBox/VMM/MM.cpp (modified) (1 diff)
• src/VBox/VMM/MMPhys.cpp (modified) (4 diffs)
• src/VBox/VMM/PGMPhys.cpp (modified) (2 diffs)
• src/VBox/VMM/REMInternal.h (modified) (1 diff)
• src/recompiler/VBoxREMWrapper.cpp (modified) (4 diffs)
• src/recompiler/VBoxRecompiler.c (modified) (23 diffs)
• src/recompiler/cpu-all.h (modified) (2 diffs)
• src/recompiler/cpu-exec.c (modified) (79 diffs)
• src/recompiler/exec.c (modified) (3 diffs)

trunk/include/VBox/mm.h

@@ -114 +114 @@
 /** @} */
 
+#ifndef VBOX_WITH_NEW_PHYS_CODE
 /** @name MMR3PhysRegisterEx registration type
  * @{
@@ -127 +128 @@
 } MMPHYSREG;
 /** @} */
+#endif
 
 /**
@@ -881 +883 @@
  * @param   pszDesc     Description of the memory.
  * @thread  The Emulation Thread.
+ *
+ * @todo    This will only be used for registering MMIO2 memory from devices. So, rename it.
  */
 MMR3DECL(int) MMR3PhysRegister(PVM pVM, void *pvRam, RTGCPHYS GCPhys, unsigned cb, unsigned fFlags, const char *pszDesc);
 
+#ifndef VBOX_WITH_NEW_PHYS_CODE
 /**
  * Register externally allocated RAM for the virtual machine.
@@ -900 +905 @@
  * @thread  The Emulation Thread.
  * @todo update this description.
+ * @deprecated  For the old dynamic allocation code only. Will be removed with VBOX_WITH_NEW_PHYS_CODE.
  */
 MMR3DECL(int) MMR3PhysRegisterEx(PVM pVM, void *pvRam, RTGCPHYS GCPhys, unsigned cb, unsigned fFlags, MMPHYSREG enmType, const char *pszDesc);
+#endif /* !VBOX_WITH_NEW_PHYS_CODE */
 
 /**

trunk/include/VBox/pgm.h

@@ -1414 +1414 @@
 PGMR3DECL(int) PGMR3ChangeShwPDMappings(PVM pVM, bool fEnable);
 
+#ifndef VBOX_WITH_NEW_PHYS_CODE
 /**
  * Allocate missing physical pages for an existing guest RAM range.
@@ -1422 +1423 @@
  */
 PGMR3DECL(int) PGM3PhysGrowRange(PVM pVM, RTGCPHYS GCPhys);
+#endif /* !VBOX_WITH_NEW_PHYS_CODE */
 
 /**
@@ -1442 +1444 @@
 PGMR3DECL(int) PGMR3PhysRegister(PVM pVM, void *pvRam, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, const SUPPAGE *paPages, const char *pszDesc);
 
+#ifndef VBOX_WITH_NEW_PHYS_CODE
 /**
  * Register a chunk of a the physical memory range with PGM. MM is responsible
@@ -1457 +1460 @@
  */
 PGMR3DECL(int) PGMR3PhysRegisterChunk(PVM pVM, void *pvRam, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, const SUPPAGE *paPages, const char *pszDesc);
+#endif /* !VBOX_WITH_NEW_PHYS_CODE */
 
 /**

trunk/include/VBox/rem.h

@@ -284 +284 @@
  * @param   cb          Size of the memory.
  * @param   fFlags      Flags of the MM_RAM_FLAGS_* defines.
- * @param   pvRam       The HC address of the RAM.
- */
-REMR3DECL(void) REMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTUINT cb, void *pvRam, unsigned fFlags);
-
+ */
+REMR3DECL(void) REMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTUINT cb, unsigned fFlags);
+
+#ifndef VBOX_WITH_NEW_PHYS_CODE
 /**
  * Notification about a successful PGMR3PhysRegisterChunk() call.
@@ -298 +298 @@
  */
 REMR3DECL(void) REMR3NotifyPhysRamChunkRegister(PVM pVM, RTGCPHYS GCPhys, RTUINT cb, RTHCUINTPTR pvRam, unsigned fFlags);
+#endif
 
 /**
@@ -307 +308 @@
  * @param   pvCopy      Pointer to the ROM copy.
  * @param   fShadow     Whether it's currently writable shadow ROM or normal readonly ROM.
- *                      This function will be called when ever the protection of the 
+ *                      This function will be called when ever the protection of the
  *                      shadow ROM changes (at reset and end of POST).
  */

trunk/src/VBox/VMM/MM.cpp

@@ -216 +216 @@
         Log(("MM: %llu bytes of RAM%s\n", cbRam, fPreAlloc ? " (PreAlloc)" : ""));
         pVM->mm.s.cbRamBase = cbRam & X86_PTE_PAE_PG_MASK;
-        rc = MMR3PhysRegister(pVM, NULL, 0, pVM->mm.s.cbRamBase, MM_RAM_FLAGS_DYNAMIC_ALLOC, "Main Memory");
+        rc = MMR3PhysRegisterEx(pVM, NULL, 0, pVM->mm.s.cbRamBase, MM_RAM_FLAGS_DYNAMIC_ALLOC, MM_PHYS_TYPE_NORMAL, "Main Memory");
         if (RT_SUCCESS(rc))
         {

trunk/src/VBox/VMM/MMPhys.cpp

@@ -70 +70 @@
  * @param   pszDesc     Description of the memory.
  * @thread  The Emulation Thread.
+ *
+ * @deprecated  For the old dynamic allocation code only. Will be removed with VBOX_WITH_NEW_PHYS_CODE.
  */
 /** @todo this function description is not longer up-to-date */
@@ -134 +136 @@
                 pVM->mm.s.cbRamRegistered += cb;
 
-            REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, pvRam, fFlags);
+            REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, fFlags);
             return rc;
         }
@@ -167 +169 @@
                         pVM->mm.s.cbRamRegistered += cb;
 
-                    REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, pvRam, fFlags);
+                    REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, fFlags);
                     return rc;
                 }
@@ -253 +255 @@
         /// @todo one day provide a proper MMIO relocation operation
         REMR3NotifyPhysReserve(pVM, GCPhysOld, cb);
-        REMR3NotifyPhysRamRegister(pVM, GCPhysNew, cb, pCur->pv,
-                pCur->aPhysPages[0].Phys & (MM_RAM_FLAGS_RESERVED | MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO | MM_RAM_FLAGS_MMIO2));
+        REMR3NotifyPhysRamRegister(pVM, GCPhysNew, cb,
+                                   pCur->aPhysPages[0].Phys & (MM_RAM_FLAGS_RESERVED | MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO | MM_RAM_FLAGS_MMIO2));
     }
 

trunk/src/VBox/VMM/PGMPhys.cpp

@@ -252 +252 @@
 }
 
+#ifndef VBOX_WITH_NEW_PHYS_CODE
 
 /**
@@ -369 +370 @@
 }
 
-#ifndef VBOX_WITH_NEW_PHYS_CODE
 
 /**

trunk/src/VBox/VMM/REMInternal.h

@@ -251 +251 @@
 
 #ifdef REM_INCLUDE_CPU_H
-bool    remR3CanExecuteRaw(CPUState *env, RTGCPTR eip, unsigned fFlags, uint32_t *pExceptionIndex);
+bool    remR3CanExecuteRaw(CPUState *env, RTGCPTR eip, unsigned fFlags, int *piException);
 void    remR3CSAMCheckEIP(CPUState *env, RTGCPTR GCPtrCode);
 bool    remR3GetOpcode(CPUState *env, RTGCPTR GCPtrInstr, uint8_t *pu8Byte);

trunk/src/recompiler/VBoxREMWrapper.cpp

@@ -335 +335 @@
 static DECLCALLBACKPTR(void, pfnREMR3ReplayInvalidatedPages)(PVM);
 static DECLCALLBACKPTR(void, pfnREMR3ReplayHandlerNotifications)(PVM pVM);
-static DECLCALLBACKPTR(void, pfnREMR3NotifyPhysRamRegister)(PVM, RTGCPHYS, RTUINT, void *, unsigned);
+static DECLCALLBACKPTR(void, pfnREMR3NotifyPhysRamRegister)(PVM, RTGCPHYS, RTUINT, unsigned);
 static DECLCALLBACKPTR(void, pfnREMR3NotifyPhysRamChunkRegister)(PVM, RTGCPHYS, RTUINT, RTHCUINTPTR, unsigned);
 static DECLCALLBACKPTR(void, pfnREMR3NotifyPhysReserve)(PVM, RTGCPHYS, RTUINT);
@@ -1034 +1034 @@
     { "PGMPhysGCPhys2HCPtr",                    (void *)(uintptr_t)&PGMPhysGCPhys2HCPtr,            &g_aArgsPGMPhysGCPhys2HCPtr[0],             ELEMENTS(g_aArgsPGMPhysGCPhys2HCPtr),               REMFNDESC_FLAGS_RET_INT,    sizeof(int),        NULL },
     { "PGMPhysGCPtr2HCPtrByGstCR3",             (void *)(uintptr_t)&PGMPhysGCPtr2HCPtrByGstCR3,     &g_aArgsPGMPhysGCPtr2HCPtrByGstCR3[0],      ELEMENTS(g_aArgsPGMPhysGCPtr2HCPtrByGstCR3),        REMFNDESC_FLAGS_RET_INT,    sizeof(int),        NULL },
+#ifndef VBOX_WITH_NEW_PHYS_CODE
     { "PGM3PhysGrowRange",                      (void *)(uintptr_t)&PGM3PhysGrowRange,              &g_aArgsPGM3PhysGrowRange[0],               ELEMENTS(g_aArgsPGM3PhysGrowRange),                 REMFNDESC_FLAGS_RET_INT,    sizeof(int),        NULL },
+#endif
     { "PGMPhysIsGCPhysValid",                   (void *)(uintptr_t)&PGMPhysIsGCPhysValid,           &g_aArgsPGMPhysIsGCPhysValid[0],            ELEMENTS(g_aArgsPGMPhysIsGCPhysValid),              REMFNDESC_FLAGS_RET_INT,    sizeof(bool),       NULL },
     { "PGMPhysIsA20Enabled",                    (void *)(uintptr_t)&PGMPhysIsA20Enabled,            &g_aArgsVM[0],                              ELEMENTS(g_aArgsVM),                                REMFNDESC_FLAGS_RET_INT,    sizeof(bool),       NULL },
@@ -1981 +1983 @@
 }
 
-REMR3DECL(void) REMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTUINT cb, void *pvRam, unsigned fFlags)
+REMR3DECL(void) REMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTUINT cb, unsigned fFlags)
 {
 #ifndef USE_REM_STUBS
     Assert(VALID_PTR(pfnREMR3NotifyPhysRamRegister));
-    pfnREMR3NotifyPhysRamRegister(pVM, GCPhys, cb, pvRam, fFlags);
-#endif
-}
-
+    pfnREMR3NotifyPhysRamRegister(pVM, GCPhys, cb, fFlags);
+#endif
+}
+
+#ifndef VBOX_WITH_NEW_PHYS_CODE
 REMR3DECL(void) REMR3NotifyPhysRamChunkRegister(PVM pVM, RTGCPHYS GCPhys, RTUINT cb, RTHCUINTPTR pvRam, unsigned fFlags)
 {
@@ -1996 +1999 @@
 #endif
 }
+#endif
 
 REMR3DECL(void) REMR3NotifyPhysRomRegister(PVM pVM, RTGCPHYS GCPhys, RTUINT cb, void *pvCopy, bool fShadow)

trunk/src/recompiler/VBoxRecompiler.c

@@ -1096 +1096 @@
  * @param   eip         The EIP to check this for (might differ from env->eip).
  * @param   fFlags      hflags OR'ed with IOPL, TF and VM from eflags.
- * @param   pExceptionIndex  Stores EXCP_EXECUTE_RAW/HWACC in case raw mode is supported in this context
+ * @param   piException Stores EXCP_EXECUTE_RAW/HWACC in case raw mode is supported in this context
  *
  * @remark  This function must be kept in perfect sync with the scheduler in EM.cpp!
  */
-bool remR3CanExecuteRaw(CPUState *env, RTGCPTR eip, unsigned fFlags, uint32_t *pExceptionIndex)
+bool remR3CanExecuteRaw(CPUState *env, RTGCPTR eip, unsigned fFlags, int *piException)
 {
     /* !!! THIS MUST BE IN SYNC WITH emR3Reschedule !!! */
@@ -1147 +1147 @@
         if (HWACCMR3CanExecuteGuest(env->pVM, &Ctx) == true)
         {
-            *pExceptionIndex = EXCP_EXECUTE_HWACC;
+            *piException = EXCP_EXECUTE_HWACC;
             return true;
         }
@@ -1259 +1259 @@
         {
             Log2(("raw r0 mode forced: patch code\n"));
-            *pExceptionIndex = EXCP_EXECUTE_RAW;
+            *piException = EXCP_EXECUTE_RAW;
             return true;
         }
@@ -1288 +1288 @@
 
     Assert(PGMPhysIsA20Enabled(env->pVM));
-    *pExceptionIndex = EXCP_EXECUTE_RAW;
+    *piException = EXCP_EXECUTE_RAW;
     return true;
 }
@@ -1352 +1352 @@
     //RAWEx_ProfileStart(env, STATS_QEMU_TOTAL);
 }
+
 
 /**
@@ -1369 +1370 @@
         CSAMR3MonitorPage(env->pVM, GCPtr, CSAM_TAG_REM);
 }
+
 
 /**
@@ -1462 +1464 @@
 }
 
+
 /**
  * Called from compiled code to schedule pending timers in VMM
@@ -1476 +1479 @@
 }
 
+
 /**
  * Record trap occurance
@@ -1489 +1493 @@
     PVM pVM = env->pVM;
 #ifdef VBOX_WITH_STATISTICS
-    static STAMCOUNTER aStatTrap[255];
-    static bool        aRegisters[ELEMENTS(aStatTrap)];
+    static STAMCOUNTER s_aStatTrap[255];
+    static bool        s_aRegisters[RT_ELEMENTS(s_aStatTrap)];
 #endif
 
@@ -1496 +1500 @@
     if (uTrap < 255)
     {
-        if (!aRegisters[uTrap])
+        if (!s_aRegisters[uTrap])
         {
-            aRegisters[uTrap] = true;
+            s_aRegisters[uTrap] = true;
             char szStatName[64];
             RTStrPrintf(szStatName, sizeof(szStatName), "/REM/Trap/0x%02X", uTrap);
-            STAM_REG(env->pVM, &aStatTrap[uTrap], STAMTYPE_COUNTER, szStatName, STAMUNIT_OCCURENCES, "Trap stats.");
+            STAM_REG(env->pVM, &s_aStatTrap[uTrap], STAMTYPE_COUNTER, szStatName, STAMUNIT_OCCURENCES, "Trap stats.");
         }
-        STAM_COUNTER_INC(&aStatTrap[uTrap]);
+        STAM_COUNTER_INC(&s_aStatTrap[uTrap]);
     }
 #endif
@@ -1536 +1540 @@
 }
 
+
 /*
  * Clear current active trap
@@ -1549 +1554 @@
 }
 
+
 /*
  * Record previous call instruction addresses
@@ -1558 +1564 @@
     CSAMR3RecordCallAddress(env->pVM, env->eip);
 }
+
 
 /**
@@ -1861 +1868 @@
     if (VBOX_SUCCESS(rc))
     {
-        #ifdef DEBUG
+#ifdef DEBUG
         if (u8TrapNo == 0x80)
         {
@@ -1867 +1874 @@
             remR3DumpOBsdSyscall(pVM);
         }
-        #endif
+#endif
 
         pVM->rem.s.Env.exception_index = u8TrapNo;
@@ -2437 +2444 @@
 }
 
+
 /**
  * Notification about a successful MMR3PhysRegister() call.
@@ -2443 +2451 @@
  * @param   GCPhys      The physical address the RAM.
  * @param   cb          Size of the memory.
- * @param   pvRam       The HC address of the RAM.
  * @param   fFlags      Flags of the MM_RAM_FLAGS_* defines.
  */
-REMR3DECL(void) REMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTUINT cb, void *pvRam, unsigned fFlags)
-{
-    Log(("REMR3NotifyPhysRamRegister: GCPhys=%VGp cb=%d pvRam=%p fFlags=%d\n", GCPhys, cb, pvRam, fFlags));
+REMR3DECL(void) REMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTUINT cb, unsigned fFlags)
+{
+    Log(("REMR3NotifyPhysRamRegister: GCPhys=%VGp cb=%d fFlags=%d\n", GCPhys, cb, fFlags));
     VM_ASSERT_EMT(pVM);
 
@@ -2454 +2461 @@
      * Validate input - we trust the caller.
      */
-    Assert(!GCPhys || pvRam);
-    Assert(RT_ALIGN_P(pvRam, PAGE_SIZE) == pvRam);
     Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
     Assert(cb);
@@ -2487 +2492 @@
     pVM->rem.s.fIgnoreAll = true;
 
+#ifdef VBOX_WITH_NEW_PHYS_CODE
+    if (fFlags & MM_RAM_FLAGS_RESERVED)
+        cpu_register_physical_memory(GCPhys, cb, IO_MEM_UNASSIGNED);
+    else
+        cpu_register_physical_memory(GCPhys, cb, GCPhys);
+#else
     if (!GCPhys)
         cpu_register_physical_memory(GCPhys, cb, GCPhys | IO_MEM_RAM_MISSING);
@@ -2496 +2507 @@
             cpu_register_physical_memory(GCPhys, cb, GCPhys);
     }
+#endif
     Assert(pVM->rem.s.fIgnoreAll);
     pVM->rem.s.fIgnoreAll = false;
 }
 
+#ifndef VBOX_WITH_NEW_PHYS_CODE
 
 /**
@@ -2554 +2567 @@
 }
 
+#endif /* !VBOX_WITH_NEW_PHYS_CODE */
 
 /**
@@ -3445 +3459 @@
 #else
         Cpu.mode = CPUMODE_64BIT;
-#endif 
+#endif
 
         RTLogPrintf("Recompiled Code: %p %#lx (%ld) bytes\n", pvCode, cb, cb);
@@ -3459 +3473 @@
 #ifdef RT_ARCH_AMD64 /** @todo remove when DISInstr starts supporing 64-bit code. */
                 break;
-#endif 
+#endif
             }
             off += cbInstr;

trunk/src/recompiler/cpu-all.h

@@ -196 +196 @@
 void     remR3PhysWriteU64(RTGCPHYS DstGCPhys, uint64_t val);
 
+#ifndef VBOX_WITH_NEW_PHYS_CODE
 void     remR3GrowDynRange(unsigned long physaddr);
+#endif
 #if 0 /*defined(RT_ARCH_AMD64) && defined(VBOX_STRICT)*/
 # define VBOX_CHECK_ADDR(ptr) do { if ((uintptr_t)(ptr) >= _4G) __asm__("int3"); } while (0)
@@ -997 +999 @@
 #define IO_MEM_UNASSIGNED  (2 << IO_MEM_SHIFT)
 #define IO_MEM_NOTDIRTY    (4 << IO_MEM_SHIFT) /* used internally, never use directly */
-#if defined(VBOX)
+#if defined(VBOX) && !defined(VBOX_WITH_NEW_PHYS_CODE)
 #define IO_MEM_RAM_MISSING (5 << IO_MEM_SHIFT) /* used internally, never use directly */
 #endif

trunk/src/recompiler/cpu-exec.c

@@ -1 +1 @@
 /*
  *  i386 emulator main execution loop
- * 
+ *
  *  Copyright (c) 2003-2005 Fabrice Bellard
  *
@@ -55 +55 @@
    restored in a state compatible with the CPU emulator
  */
-void cpu_resume_from_signal(CPUState *env1, void *puc) 
+void cpu_resume_from_signal(CPUState *env1, void *puc)
 {
 #if !defined(CONFIG_SOFTMMU)
@@ -84 +84 @@
     target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
     uint8_t *tc_ptr;
-    
+
     spin_lock(&tb_lock);
 
     tb_invalidated_flag = 0;
-    
+
     regs_to_env(); /* XXX: do it just before cpu_gen_code() */
-    
+
     /* find translated block using physical mappings */
     phys_pc = get_phys_addr_code(env, pc);
@@ -101 +101 @@
         if (!tb)
             goto not_found;
-        if (tb->pc == pc && 
+        if (tb->pc == pc &&
             tb->page_addr[0] == phys_page1 &&
-            tb->cs_base == cs_base && 
+            tb->cs_base == cs_base &&
             tb->flags == flags) {
             /* check next page if needed */
             if (tb->page_addr[1] != -1) {
-                virt_page2 = (pc & TARGET_PAGE_MASK) + 
+                virt_page2 = (pc & TARGET_PAGE_MASK) +
                     TARGET_PAGE_SIZE;
                 phys_page2 = get_phys_addr_code(env, virt_page2);
@@ -135 +135 @@
     cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
     code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
-    
+
     /* check next page if needed */
     virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
@@ -143 +143 @@
     }
     tb_link_phys(tb, phys_pc, phys_page2);
-    
+
  found:
     /* we add the TB in the virtual pc hash table */
@@ -249 +249 @@
 #elif defined(TARGET_PPC)
     if (env1->halted) {
-        if (env1->msr[MSR_EE] && 
-            (env1->interrupt_request & 
+        if (env1->msr[MSR_EE] &&
+            (env1->interrupt_request &
              (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER))) {
             env1->halted = 0;
@@ -288 +288 @@
 #endif
 
-    cpu_single_env = env1; 
+    cpu_single_env = env1;
 
     /* first we save global registers */
@@ -321 +321 @@
 #ifndef VBOX /* VBOX: We need to raise traps and suchlike from the outside. */
     env->exception_index = -1;
-#endif 
+#endif
 
     /* prepare setjmp context for exception handling */
     for(;;) {
-        if (setjmp(env->jmp_env) == 0) 
+        if (setjmp(env->jmp_env) == 0)
         {
             env->current_tb = NULL;
@@ -354 +354 @@
                     RAWEx_ProfileStart(env, STATS_IRQ_HANDLING);
                     Log(("do_interrupt %d %d %08x\n", env->exception_index, env->exception_is_int, env->exception_next_eip));
-                    do_interrupt(env->exception_index, 
-                                 env->exception_is_int, 
-                                 env->error_code, 
+                    do_interrupt(env->exception_index,
+                                 env->exception_is_int,
+                                 env->error_code,
                                  env->exception_next_eip, 0);
                     RAWEx_ProfileStop(env, STATS_IRQ_HANDLING);
@@ -405 +405 @@
                         do_smm_enter();
                         T0 = 0;
-                    } 
+                    }
                     else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
-                             (env->eflags & IF_MASK) && 
-                             !(env->hflags & HF_INHIBIT_IRQ_MASK)) 
+                             (env->eflags & IF_MASK) &&
+                             !(env->hflags & HF_INHIBIT_IRQ_MASK))
                     {
                         /* if hardware interrupt pending, we execute it */
@@ -431 +431 @@
                     }
                     RAWEx_ProfileStop(env, STATS_IRQ_HANDLING);
-                    if (interrupt_request & CPU_INTERRUPT_EXIT) 
+                    if (interrupt_request & CPU_INTERRUPT_EXIT)
                     {
                         env->exception_index = EXCP_INTERRUPT;
@@ -438 +438 @@
                         cpu_loop_exit();
                     }
-                    if (interrupt_request & CPU_INTERRUPT_RC) 
+                    if (interrupt_request & CPU_INTERRUPT_RC)
                     {
                         env->exception_index = EXCP_RC;
@@ -451 +451 @@
                  */
                 RAWEx_ProfileStart(env, STATS_RAW_CHECK);
-                if (remR3CanExecuteRaw(env, 
-                                       env->eip + env->segs[R_CS].base, 
+                if (remR3CanExecuteRaw(env,
+                                       env->eip + env->segs[R_CS].base,
                                        env->hflags | (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK)),
                                        &env->exception_index))
@@ -469 +469 @@
                    jump. */
                 if (T0 != 0
-                    && !(tb->cflags & CF_RAW_MODE) 
-                    && tb->page_addr[1] == -1) 
+                    && !(tb->cflags & CF_RAW_MODE)
+                    && tb->page_addr[1] == -1)
                 {
                     spin_lock(&tb_lock);
@@ -484 +484 @@
 #if defined(DEBUG) && defined(VBOX) && !defined(DEBUG_dmik)
 #if !defined(DEBUG_bird)
-                if (((env->hflags >> HF_CPL_SHIFT) & 3) == 0 && (env->hflags & HF_PE_MASK) && (env->cr[0] & CR0_PG_MASK)) 
+                if (((env->hflags >> HF_CPL_SHIFT) & 3) == 0 && (env->hflags & HF_PE_MASK) && (env->cr[0] & CR0_PG_MASK))
                 {
                     if(!(env->state & CPU_EMULATE_SINGLE_STEP))
@@ -492 +492 @@
                 }
                 else
-                if (((env->hflags >> HF_CPL_SHIFT) & 3) == 3 && (env->hflags & HF_PE_MASK) && (env->cr[0] & CR0_PG_MASK)) 
+                if (((env->hflags >> HF_CPL_SHIFT) & 3) == 3 && (env->hflags & HF_PE_MASK) && (env->cr[0] & CR0_PG_MASK))
                 {
                     if(!(env->state & CPU_EMULATE_SINGLE_STEP))
@@ -506 +506 @@
                     }
                 }
-                else 
+                else
                 {
                     Log(("EMRM: %04X:%08X SS:ESP=%04X:%08X IF=%d TF=%d CPL=%d PE=%d PG=%d\n", env->segs[R_CS].selector, env->eip, env->segs[R_SS].selector, ESP, (env->eflags & IF_MASK) ? 1 : 0, (env->eflags & TF_MASK) ? 1 : 0, (env->hflags >> HF_CPL_SHIFT) & 3, env->cr[0] & X86_CR0_PE, env->cr[0] & X86_CR0_PG));
@@ -524 +524 @@
                         #else
                         env->state &= ~CPU_EMULATE_SINGLE_STEP;
-                        #endif 
+                        #endif
                     }
 #endif
@@ -535 +535 @@
                     }
                 }
-                else 
+                else
                 {
                     RAWEx_ProfileStart(env, STATS_QEMU_RUN_EMULATED_CODE);
@@ -563 +563 @@
         }
 #ifdef VBOX_HIGH_RES_TIMERS_HACK
-        /* NULL the current_tb here so cpu_interrupt() doesn't do 
+        /* NULL the current_tb here so cpu_interrupt() doesn't do
            anything unnecessary (like crashing during emulate single instruction). */
         env->current_tb = NULL;
@@ -610 +610 @@
 #elif defined(TARGET_PPC)
     if (env1->halted) {
-        if (env1->msr[MSR_EE] && 
-            (env1->interrupt_request & 
+        if (env1->msr[MSR_EE] &&
+            (env1->interrupt_request &
              (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER))) {
             env1->halted = 0;
@@ -649 +649 @@
 #endif
 
-    cpu_single_env = env1; 
+    cpu_single_env = env1;
 
     /* first we save global registers */
@@ -685 +685 @@
 #ifndef VBOX /* VBOX: We need to raise traps and suchlike from the outside. */
     env->exception_index = -1;
-#endif 
+#endif
 
     /* prepare setjmp context for exception handling */
@@ -691 +691 @@
         if (setjmp(env->jmp_env) == 0) {
             env->current_tb = NULL;
-#ifdef VBOX 
+#ifdef VBOX
             VMMR3Unlock(env->pVM);
             VMMR3Lock(env->pVM);
 
-            /* Check for high priority requests first (like fatal 
+            /* Check for high priority requests first (like fatal
                errors). */
             if (env->interrupt_request & CPU_INTERRUPT_RC) {
@@ -717 +717 @@
                        loop */
 #if defined(TARGET_I386)
-                    do_interrupt_user(env->exception_index, 
-                                      env->exception_is_int, 
-                                      env->error_code, 
+                    do_interrupt_user(env->exception_index,
+                                      env->exception_is_int,
+                                      env->error_code,
                                       env->exception_next_eip);
 #endif
@@ -729 +729 @@
                        trigger new exceptions, but we do not handle
                        double or triple faults yet. */
-                    do_interrupt(env->exception_index, 
-                                 env->exception_is_int, 
-                                 env->error_code, 
+                    do_interrupt(env->exception_index,
+                                 env->exception_is_int,
+                                 env->error_code,
                                  env->exception_next_eip, 0);
 #elif defined(TARGET_PPC)
@@ -746 +746 @@
                 }
                 env->exception_index = -1;
-            } 
+            }
 #ifdef USE_KQEMU
             if (kqemu_is_ok(env) && env->interrupt_request == 0) {
@@ -776 +776 @@
             for(;;) {
 #if defined(__sparc__) && !defined(HOST_SOLARIS)
-                /* g1 can be modified by some libc? functions */ 
+                /* g1 can be modified by some libc? functions */
                 tmp_T0 = T0;
-#endif      
+#endif
                 interrupt_request = env->interrupt_request;
                 if (__builtin_expect(interrupt_request, 0)) {
@@ -784 +784 @@
                     /* Single instruction exec request, we execute it and return (one way or the other).
                        The caller will always reschedule after doing this operation! */
-                    if (interrupt_request & CPU_INTERRUPT_SINGLE_INSTR) 
+                    if (interrupt_request & CPU_INTERRUPT_SINGLE_INSTR)
                     {
                         /* not in flight are we? */
-                        if (!(env->interrupt_request & CPU_INTERRUPT_SINGLE_INSTR_IN_FLIGHT)) 
+                        if (!(env->interrupt_request & CPU_INTERRUPT_SINGLE_INSTR_IN_FLIGHT))
                         {
                             ASMAtomicOrS32(&env->interrupt_request, CPU_INTERRUPT_SINGLE_INSTR_IN_FLIGHT);
@@ -801 +801 @@
                                 || !(env->eflags & IF_MASK)
                                 ||  (env->hflags & HF_INHIBIT_IRQ_MASK)
-                               ) 
+                               )
                             {
                                 env->exception_index = ret = EXCP_SINGLE_INSTR;
@@ -824 +824 @@
 #endif
                     } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
-                        (env->eflags & IF_MASK) && 
+                        (env->eflags & IF_MASK) &&
                         !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
                         int intno;
@@ -831 +831 @@
 #else
                         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
-#endif 
+#endif
                         intno = cpu_get_pic_interrupt(env);
                         if (loglevel & CPU_LOG_TB_IN_ASM) {
@@ -944 +944 @@
 #else
                         env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
-#endif 
+#endif
                         /* ensure that no TB jump will be modified as
                            the program flow was changed */
@@ -955 +955 @@
 #ifdef VBOX
                     RAWEx_ProfileStop(env, STATS_IRQ_HANDLING);
-#endif 
+#endif
                     if (interrupt_request & CPU_INTERRUPT_EXIT) {
 #if defined(VBOX)
@@ -963 +963 @@
                         env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
                         env->exception_index = EXCP_INTERRUPT;
-#endif 
+#endif
                         cpu_loop_exit();
                     }
@@ -1024 +1024 @@
                     cpu_dump_state(env, logfile, fprintf, 0);
 #else
-#error unsupported target CPU 
+#error unsupported target CPU
 #endif
                 }
@@ -1033 +1033 @@
                  */
                 RAWEx_ProfileStart(env, STATS_RAW_CHECK);
-                if (remR3CanExecuteRaw(env, 
-                                       env->eip + env->segs[R_CS].base, 
+                if (remR3CanExecuteRaw(env,
+                                       env->eip + env->segs[R_CS].base,
                                        env->hflags | (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK))
                                        flags, &env->exception_index))
@@ -1054 +1054 @@
 #if defined(__sparc__) && !defined(HOST_SOLARIS)
                 T0 = tmp_T0;
-#endif      
+#endif
                 /* see if we can patch the calling TB. When the TB
                    spans two pages, we cannot safely do a direct
@@ -1068 +1068 @@
                         tb->page_addr[1] == -1
 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
-                    && (tb->cflags & CF_CODE_COPY) == 
+                    && (tb->cflags & CF_CODE_COPY) ==
                     (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
 #endif
@@ -1076 +1076 @@
 #if defined(USE_CODE_COPY)
                     /* propagates the FP use info */
-                    ((TranslationBlock *)(T0 & ~3))->cflags |= 
+                    ((TranslationBlock *)(T0 & ~3))->cflags |=
                         (tb->cflags & CF_FP_USED);
 #endif
@@ -1090 +1090 @@
                                      "mov       %%o7,%%i0"
                                      : /* no outputs */
-                                     : "r" (gen_func) 
+                                     : "r" (gen_func)
                                      : "i0", "i1", "i2", "i3", "i4", "i5",
                                        "l0", "l1", "l2", "l3", "l4", "l5",
@@ -1187 +1187 @@
 #if defined(DEBUG) && defined(VBOX) && !defined(DEBUG_dmik)
 #if !defined(DEBUG_bird)
-                if (((env->hflags >> HF_CPL_SHIFT) & 3) == 0 && (env->hflags & HF_PE_MASK) && (env->cr[0] & CR0_PG_MASK)) 
+                if (((env->hflags >> HF_CPL_SHIFT) & 3) == 0 && (env->hflags & HF_PE_MASK) && (env->cr[0] & CR0_PG_MASK))
                 {
                     if(!(env->state & CPU_EMULATE_SINGLE_STEP))
@@ -1195 +1195 @@
                 }
                 else
-                if (((env->hflags >> HF_CPL_SHIFT) & 3) == 3 && (env->hflags & HF_PE_MASK) && (env->cr[0] & CR0_PG_MASK)) 
+                if (((env->hflags >> HF_CPL_SHIFT) & 3) == 3 && (env->hflags & HF_PE_MASK) && (env->cr[0] & CR0_PG_MASK))
                 {
                     if(!(env->state & CPU_EMULATE_SINGLE_STEP))
@@ -1222 +1222 @@
                         #else
                         env->state &= ~CPU_EMULATE_SINGLE_STEP;
-                        #endif 
-                    }
-#endif 
+                        #endif
+                    }
+#endif
                     TMCpuTickPause(env->pVM);
                     remR3DisasInstr(env, -1, NULL);
@@ -1233 +1233 @@
                     }
                 }
-                else 
+                else
                 {
                     RAWEx_ProfileStart(env, STATS_QEMU_RUN_EMULATED_CODE);
@@ -1307 +1307 @@
 
     /* fail safe : never use cpu_single_env outside cpu_exec() */
-    cpu_single_env = NULL; 
+    cpu_single_env = NULL;
     return ret;
 }
@@ -1336 +1336 @@
     if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
         selector &= 0xffff;
-        cpu_x86_load_seg_cache(env, seg_reg, selector, 
+        cpu_x86_load_seg_cache(env, seg_reg, selector,
                                (selector << 4), 0xffff, 0);
     } else {
@@ -1350 +1350 @@
     saved_env = env;
     env = s;
-    
+
     helper_fsave((target_ulong)ptr, data32);
 
@@ -1362 +1362 @@
     saved_env = env;
     env = s;
-    
+
     helper_frstor((target_ulong)ptr, data32);
 
@@ -1379 +1379 @@
    signal set which should be restored */
 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
-                                    int is_write, sigset_t *old_set, 
+                                    int is_write, sigset_t *old_set,
                                     void *puc)
 {
@@ -1388 +1388 @@
         env = cpu_single_env; /* XXX: find a correct solution for multithread */
 #if defined(DEBUG_SIGNAL)
-    qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", 
+    qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
                 pc, address, is_write, *(unsigned long *)old_set);
 #endif
@@ -1397 +1397 @@
 
     /* see if it is an MMU fault */
-    ret = cpu_x86_handle_mmu_fault(env, address, is_write, 
+    ret = cpu_x86_handle_mmu_fault(env, address, is_write,
                                    ((env->hflags & HF_CPL_MASK) == 3), 0);
     if (ret < 0)
@@ -1412 +1412 @@
     if (ret == 1) {
 #if 0
-        printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n", 
+        printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
                env->eip, env->cr[2], env->error_code);
 #endif
@@ -1439 +1439 @@
         env = cpu_single_env; /* XXX: find a correct solution for multithread */
 #if defined(DEBUG_SIGNAL)
-    printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", 
+    printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
            pc, address, is_write, *(unsigned long *)old_set);
 #endif
@@ -1475 +1475 @@
         env = cpu_single_env; /* XXX: find a correct solution for multithread */
 #if defined(DEBUG_SIGNAL)
-    printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", 
+    printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
            pc, address, is_write, *(unsigned long *)old_set);
 #endif
@@ -1507 +1507 @@
     TranslationBlock *tb;
     int ret;
-    
+
     if (cpu_single_env)
         env = cpu_single_env; /* XXX: find a correct solution for multithread */
 #if defined(DEBUG_SIGNAL)
-    printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", 
+    printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
            pc, address, is_write, *(unsigned long *)old_set);
 #endif
@@ -1535 +1535 @@
     if (ret == 1) {
 #if 0
-        printf("PF exception: NIP=0x%08x error=0x%x %p\n", 
+        printf("PF exception: NIP=0x%08x error=0x%x %p\n",
                env->nip, env->error_code, tb);
 #endif
@@ -1561 +1561 @@
         env = cpu_single_env; /* XXX: find a correct solution for multithread */
 #if defined(DEBUG_SIGNAL)
-    printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", 
+    printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
            pc, address, is_write, *(unsigned long *)old_set);
 #endif
@@ -1596 +1596 @@
     TranslationBlock *tb;
     int ret;
-    
+
     if (cpu_single_env)
         env = cpu_single_env; /* XXX: find a correct solution for multithread */
 #if defined(DEBUG_SIGNAL)
-    printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", 
+    printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
            pc, address, is_write, *(unsigned long *)old_set);
 #endif
@@ -1624 +1624 @@
     if (ret == 1) {
 #if 0
-        printf("PF exception: NIP=0x%08x error=0x%x %p\n", 
+        printf("PF exception: NIP=0x%08x error=0x%x %p\n",
                env->nip, env->error_code, tb);
 #endif
@@ -1646 +1646 @@
     TranslationBlock *tb;
     int ret;
-    
+
     if (cpu_single_env)
         env = cpu_single_env; /* XXX: find a correct solution for multithread */
 #if defined(DEBUG_SIGNAL)
-    printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", 
+    printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
            pc, address, is_write, *(unsigned long *)old_set);
 #endif
@@ -1673 +1673 @@
     }
 #if 0
-        printf("PF exception: NIP=0x%08x error=0x%x %p\n", 
+        printf("PF exception: NIP=0x%08x error=0x%x %p\n",
                env->nip, env->error_code, tb);
 #endif
@@ -1690 +1690 @@
 
 #if defined(USE_CODE_COPY)
-static void cpu_send_trap(unsigned long pc, int trap, 
+static void cpu_send_trap(unsigned long pc, int trap,
                           struct ucontext *uc)
 {
@@ -1709 +1709 @@
 #endif
 
-int cpu_signal_handler(int host_signum, void *pinfo, 
+int cpu_signal_handler(int host_signum, void *pinfo,
                        void *puc)
 {
@@ -1732 +1732 @@
     } else
 #endif
-        return handle_cpu_signal(pc, (unsigned long)info->si_addr, 
-                                 trapno == 0xe ? 
+        return handle_cpu_signal(pc, (unsigned long)info->si_addr,
+                                 trapno == 0xe ?
                                  (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
                                  &uc->uc_sigmask, puc);
@@ -1748 +1748 @@
 
     pc = uc->uc_mcontext.gregs[REG_RIP];
-    return handle_cpu_signal(pc, (unsigned long)info->si_addr, 
-                             uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ? 
+    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
+                             uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
                              (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
                              &uc->uc_sigmask, puc);
@@ -1805 +1805 @@
 #endif /* __APPLE__ */
 
-int cpu_signal_handler(int host_signum, void *pinfo, 
+int cpu_signal_handler(int host_signum, void *pinfo,
                        void *puc)
 {
@@ -1823 +1823 @@
         is_write = 1;
 #endif
-    return handle_cpu_signal(pc, (unsigned long)info->si_addr, 
+    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
                              is_write, &uc->uc_sigmask, puc);
 }
@@ -1829 +1829 @@
 #elif defined(__alpha__)
 
-int cpu_signal_handler(int host_signum, void *pinfo, 
+int cpu_signal_handler(int host_signum, void *pinfo,
                            void *puc)
 {
@@ -1854 +1854 @@
     }
 
-    return handle_cpu_signal(pc, (unsigned long)info->si_addr, 
+    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
                              is_write, &uc->uc_sigmask, puc);
 }
 #elif defined(__sparc__)
 
-int cpu_signal_handler(int host_signum, void *pinfo, 
+int cpu_signal_handler(int host_signum, void *pinfo,
                        void *puc)
 {
@@ -1868 +1868 @@
     int is_write;
     uint32_t insn;
-    
+
     /* XXX: is there a standard glibc define ? */
     pc = regs[1];
@@ -1887 +1887 @@
       }
     }
-    return handle_cpu_signal(pc, (unsigned long)info->si_addr, 
+    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
                              is_write, sigmask, NULL);
 }
@@ -1893 +1893 @@
 #elif defined(__arm__)
 
-int cpu_signal_handler(int host_signum, void *pinfo, 
+int cpu_signal_handler(int host_signum, void *pinfo,
                        void *puc)
 {
@@ -1900 +1900 @@
     unsigned long pc;
     int is_write;
-    
+
     pc = uc->uc_mcontext.gregs[R15];
     /* XXX: compute is_write */
     is_write = 0;
-    return handle_cpu_signal(pc, (unsigned long)info->si_addr, 
+    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
                              is_write,
                              &uc->uc_sigmask, puc);
@@ -1911 +1911 @@
 #elif defined(__mc68000)
 
-int cpu_signal_handler(int host_signum, void *pinfo, 
+int cpu_signal_handler(int host_signum, void *pinfo,
                        void *puc)
 {
@@ -1918 +1918 @@
     unsigned long pc;
     int is_write;
-    
+
     pc = uc->uc_mcontext.gregs[16];
     /* XXX: compute is_write */
     is_write = 0;
-    return handle_cpu_signal(pc, (unsigned long)info->si_addr, 
+    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
                              is_write,
                              &uc->uc_sigmask, puc);
@@ -1963 +1963 @@
 #elif defined(__s390__)
 
-int cpu_signal_handler(int host_signum, void *pinfo, 
+int cpu_signal_handler(int host_signum, void *pinfo,
                        void *puc)
 {
@@ -1970 +1970 @@
     unsigned long pc;
     int is_write;
-    
+
     pc = uc->uc_mcontext.psw.addr;
     /* XXX: compute is_write */
     is_write = 0;
-    return handle_cpu_signal(pc, (unsigned long)info->si_addr, 
+    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
                              is_write,
                              &uc->uc_sigmask, puc);

trunk/src/recompiler/exec.c

@@ -277 +277 @@
           pd[i].phys_offset = IO_MEM_UNASSIGNED;
     }
-#if defined(VBOX)
+#if defined(VBOX) && !defined(VBOX_WITH_NEW_PHYS_CODE)
     pd = ((PhysPageDesc *)pd) + (index & (L2_SIZE - 1));
     if (RT_UNLIKELY((pd->phys_offset & ~TARGET_PAGE_MASK) == IO_MEM_RAM_MISSING))
@@ -1953 +1953 @@
         p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 1);
         p->phys_offset = phys_offset;
-#if !defined(VBOX)
+#if !defined(VBOX) || defined(VBOX_WITH_NEW_PHYS_CODE)
         if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM ||
             (phys_offset & IO_MEM_ROMD))
@@ -2163 +2163 @@
     cpu_register_io_memory(IO_MEM_UNASSIGNED >> IO_MEM_SHIFT, unassigned_mem_read, unassigned_mem_write, NULL);
     cpu_register_io_memory(IO_MEM_NOTDIRTY >> IO_MEM_SHIFT, error_mem_read, notdirty_mem_write, NULL);
-#if defined(VBOX)
+#if defined(VBOX) && !defined(VBOX_WITH_NEW_PHYS_CODE)
     cpu_register_io_memory(IO_MEM_RAM_MISSING >> IO_MEM_SHIFT, unassigned_mem_read, unassigned_mem_write, NULL);
     io_mem_nb = 6;