Changeset 65507 in vbox

Timestamp:

Jan 29, 2017 5:32:33 PM (8 years ago)

Author:

vboxsync

Message:

bs3-cpu-instr-2: Simple cmpxchg16b testcase.

Location:

trunk/src/VBox/ValidationKit/bootsectors

Files:

• bs3-cpu-instr-2-template.c (modified) (2 diffs)
• bs3-cpu-instr-2-template.mac (modified) (1 diff)
• bs3-cpu-instr-2.c (modified) (2 diffs)
• bs3kit/bs3kit.h (modified) (1 diff)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-2-template.c

@@ -51 +51 @@
 extern FNBS3FAR     BS3_CMN_NM(bs3CpuInstr2_div_xBX_ud2);
 extern FNBS3FAR     BS3_CMN_NM(bs3CpuInstr2_idiv_xBX_ud2);
+# if ARCH_BITS == 64
+extern FNBS3FAR     BS3_CMN_NM(bs3CpuInstr2_cmpxchg16b_rdi_ud2);
+extern FNBS3FAR     BS3_CMN_NM(bs3CpuInstr2_lock_cmpxchg16b_rdi_ud2);
+# endif
 #endif
 
@@ -537 +541 @@
 
 
+# if ARCH_BITS == 64
+BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr2_cmpxchg16b)(uint8_t bMode)
+{
+    BS3REGCTX       Ctx;
+    BS3REGCTX       ExpectCtx;
+    BS3TRAPFRAME    TrapFrame;
+    RTUINT128U      au128[3];
+    PRTUINT128U     pau128       = RT_ALIGN_PT(&au128[0], sizeof(RTUINT128U), PRTUINT128U);
+    bool const      fSupportCX16 = RT_BOOL(ASMCpuId_ECX(1) & X86_CPUID_FEATURE_ECX_CX16);
+    unsigned        iLocked;
+    unsigned        iFlags;
+    unsigned        offBuf;
+    unsigned        iMatch;
+
+    /* Ensure the structures are allocated before we sample the stack pointer. */
+    Bs3MemSet(&Ctx, 0, sizeof(Ctx));
+    Bs3MemSet(&ExpectCtx, 0, sizeof(ExpectCtx));
+    Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame));
+    Bs3MemSet(pau128, 0, sizeof(pau128[0]) * 2);
+
+    /*
+     * Create test context.
+     */
+    Bs3RegCtxSaveEx(&Ctx, bMode, 512);
+    if (!fSupportCX16)
+        Bs3TestPrintf("Note! CMPXCHG16B is not supported by the CPU!\n");
+
+    /*
+     * One loop with the normal variant and one with the locked one
+     */
+    g_usBs3TestStep = 0;
+    Bs3RegCtxSetRipCsFromCurPtr(&Ctx, BS3_CMN_NM(bs3CpuInstr2_cmpxchg16b_rdi_ud2));
+    for (iLocked = 0; iLocked < 2; iLocked++)
+    {
+        /*
+         * One loop with all status flags set, and one with them clear.
+         */
+        Ctx.rflags.u16 |= X86_EFL_STATUS_BITS;
+        for (iFlags = 0; iFlags < 2; iFlags++)
+        {
+            Bs3MemCpy(&ExpectCtx, &Ctx, sizeof(ExpectCtx));
+
+            for (offBuf = 0; offBuf < sizeof(RTUINT128U); offBuf++)
+            {
+#  define CX16_OLD_LO       UINT64_C(0xabb6345dcc9c4bbd)
+#  define CX16_OLD_HI       UINT64_C(0x7b06ea35749549ab)
+#  define CX16_MISMATCH_LO  UINT64_C(0xbace3e3590f18981)
+#  define CX16_MISMATCH_HI  UINT64_C(0x9b385e8bfd5b4000)
+#  define CX16_STORE_LO     UINT64_C(0x5cbd27d251f6559b)
+#  define CX16_STORE_HI     UINT64_C(0x17ff434ed1b54963)
+
+                PRTUINT128U pBuf = (PRTUINT128U)&pau128->au8[offBuf];
+
+                ExpectCtx.rax.u = Ctx.rax.u = CX16_MISMATCH_LO;
+                ExpectCtx.rdx.u = Ctx.rdx.u = CX16_MISMATCH_HI;
+                for (iMatch = 0; iMatch < 2; iMatch++)
+                {
+                    uint8_t bExpectXcpt;
+                    pBuf->s.Lo = CX16_OLD_LO;
+                    pBuf->s.Hi = CX16_OLD_HI;
+                    ExpectCtx.rdi.u = Ctx.rdi.u = (uintptr_t)pBuf;
+                    Bs3TrapSetJmpAndRestore(&Ctx, &TrapFrame);
+                    g_usBs3TestStep++;
+                    //Bs3TestPrintf("Test: iFlags=%d offBuf=%d iMatch=%u\n", iFlags, offBuf, iMatch);
+                    bExpectXcpt = X86_XCPT_UD;
+                    if (fSupportCX16)
+                    {
+                        if (offBuf & 15)
+                        {
+                            bExpectXcpt = X86_XCPT_GP;
+                            ExpectCtx.rip.u = Ctx.rip.u;
+                            ExpectCtx.rflags.u32 = Ctx.rflags.u32;
+                        }
+                        else
+                        {
+                            ExpectCtx.rax.u = CX16_OLD_LO;
+                            ExpectCtx.rdx.u = CX16_OLD_HI;
+                            if (iMatch & 1)
+                                ExpectCtx.rflags.u32 = Ctx.rflags.u32 | X86_EFL_ZF;
+                            else
+                                ExpectCtx.rflags.u32 = Ctx.rflags.u32 & ~X86_EFL_ZF;
+                            ExpectCtx.rip.u = Ctx.rip.u + 4 + (iLocked & 1);
+                        }
+                        ExpectCtx.rflags.u32 |= X86_EFL_RF;
+                    }
+                    if (   !Bs3TestCheckRegCtxEx(&TrapFrame.Ctx, &ExpectCtx, 0 /*cbPcAdjust*/, 0 /*cbSpAdjust*/,
+                                                 0 /*fExtraEfl*/, "lm64", 0 /*idTestStep*/)
+                        || TrapFrame.bXcpt != bExpectXcpt)
+                    {
+                        if (TrapFrame.bXcpt != bExpectXcpt)
+                            Bs3TestFailedF("Expected bXcpt=#%x, got %#x (%#x)", bExpectXcpt, TrapFrame.bXcpt, TrapFrame.uErrCd);
+                        Bs3TestFailedF("^^^ iLocked=%d iFlags=%d offBuf=%d iMatch=%u\n", iLocked, iFlags, offBuf, iMatch);
+                        ASMHalt();
+                    }
+
+                    ExpectCtx.rax.u = Ctx.rax.u = CX16_OLD_LO;
+                    ExpectCtx.rdx.u = Ctx.rdx.u = CX16_OLD_HI;
+                }
+            }
+            Ctx.rflags.u16 &= ~X86_EFL_STATUS_BITS;
+        }
+        Bs3RegCtxSetRipCsFromCurPtr(&Ctx, BS3_CMN_NM(bs3CpuInstr2_lock_cmpxchg16b_rdi_ud2));
+    }
+
+    return 0;
+
+}
+# endif /* ARCH_BITS == 64 */
+
+
 #endif /* BS3_INSTANTIATING_CMN */
 

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-2-template.mac

@@ -83 +83 @@
 BS3_PROC_END_CMN   bs3CpuInstr2_idiv_xBX_ud2
 
+
+ %if TMPL_BITS == 64
+BS3_PROC_BEGIN_CMN bs3CpuInstr2_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
+        cmpxchg16b [rdi]
+.again:
+        ud2
+        jmp     .again
+AssertCompile(.again - BS3_LAST_LABEL == 4)
+BS3_PROC_END_CMN   bs3CpuInstr2_cmpxchg16b_rdi_ud2
+
+
+BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
+        lock cmpxchg16b [rdi]
+.again:
+        ud2
+        jmp     .again
+AssertCompile(.again - BS3_LAST_LABEL == 5)
+BS3_PROC_END_CMN   bs3CpuInstr2_lock_cmpxchg16b_rdi_ud2
+ %endif ; TMPL_BITS == 64
+
+
 %endif ; BS3_INSTANTIATING_CMN
 

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-2.c

@@ -39 +39 @@
 BS3TESTMODE_PROTOTYPES_CMN(bs3CpuInstr2_div);
 BS3TESTMODE_PROTOTYPES_CMN(bs3CpuInstr2_idiv);
+BS3TESTMODE_PROTOTYPES_CMN_64(bs3CpuInstr2_cmpxchg16b);
 
 
@@ -46 +47 @@
 static const BS3TESTMODEENTRY g_aModeTests[] =
 {
+#if 0
     BS3TESTMODEENTRY_CMN("mul", bs3CpuInstr2_mul),
     BS3TESTMODEENTRY_CMN("imul", bs3CpuInstr2_imul),
     BS3TESTMODEENTRY_CMN("div", bs3CpuInstr2_div),
     BS3TESTMODEENTRY_CMN("idiv", bs3CpuInstr2_idiv),
+#endif
+    BS3TESTMODEENTRY_CMN_64("cmpxchg16b", bs3CpuInstr2_cmpxchg16b),
 };
 

trunk/src/VBox/ValidationKit/bootsectors/bs3kit/bs3kit.h

@@ -3107 +3107 @@
     FNBS3TESTDOMODE /*BS3_FAR_CODE*/    RT_CONCAT(a_BaseNm, _c64)
 
+/** @def BS3TESTMODEENTRY_CMN_64
+ * Produces a BS3TESTMODEENTRY initializer for common 64-bit test functions. */
+#define BS3TESTMODEENTRY_CMN_64(a_szTest, a_BaseNm) \
+    {   /*pszSubTest =*/ a_szTest, \
+        /*RM*/        NULL, \
+        /*PE16*/      NULL, \
+        /*PE16_32*/   NULL, \
+        /*PE16_V86*/  NULL, \
+        /*PE32*/      NULL, \
+        /*PE32_16*/   NULL, \
+        /*PEV86*/     NULL, \
+        /*PP16*/      NULL, \
+        /*PP16_32*/   NULL, \
+        /*PP16_V86*/  NULL, \
+        /*PP32*/      NULL, \
+        /*PP32_16*/   NULL, \
+        /*PPV86*/     NULL, \
+        /*PAE16*/     NULL, \
+        /*PAE16_32*/  NULL, \
+        /*PAE16_V86*/ NULL, \
+        /*PAE32*/     NULL, \
+        /*PAE32_16*/  NULL, \
+        /*PAEV86*/    NULL, \
+        /*LM16*/      NULL, \
+        /*LM32*/      NULL, \
+        /*LM64*/      RT_CONCAT(a_BaseNm, _c64), \
+    }
+
+/** @def BS3TESTMODE_PROTOTYPES_CMN
+ * Standard protype to go with #BS3TESTMODEENTRY_CMN_64. */
+#define BS3TESTMODE_PROTOTYPES_CMN_64(a_BaseNm) \
+    FNBS3TESTDOMODE /*BS3_FAR_CODE*/    RT_CONCAT(a_BaseNm, _c64)
+
 /** @def BS3TESTMODEENTRY_MODE
  * Produces a BS3TESTMODEENTRY initializer for a full set of mode test