Changeset 65575 in vbox
- Timestamp:
- Feb 1, 2017 6:52:58 PM (8 years ago)
- Location:
- trunk/src/VBox/ValidationKit/bootsectors
- Files:
-
- 4 edited
-
Makefile.kmk (modified) (1 diff)
-
bs3-cpu-decoding-1-asm.asm (modified) (1 diff)
-
bs3-cpu-decoding-1-template.mac (modified) (2 diffs)
-
bs3-cpu-decoding-1.c32 (modified) (3 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/ValidationKit/bootsectors/Makefile.kmk
r64704 r65575 288 288 # bs3kit/bs3-cmn-instantiate.c32 \ 289 289 # bs3kit/bs3-cmn-instantiate.c64 290 #bs3-cpu-decoding-1-template.o:: \ 290 bs3-cpu-decoding-1-template.o:: \ 291 $$(bs3-cpu-decoding-1_0_OUTDIR)/bs3-cpu-decoding-1-asm.o16 291 292 # $$(bs3-cpu-decoding-1_0_OUTDIR)/bs3kit/bs3-cmn-instantiate.o16 \ 292 293 # $$(bs3-cpu-decoding-1_0_OUTDIR)/bs3kit/bs3-cmn-instantiate.o32 \ 293 294 # $$(bs3-cpu-decoding-1_0_OUTDIR)/bs3kit/bs3-cmn-instantiate.o64 \ 294 # $$(bs3-cpu-decoding-1_0_OUTDIR)/bs3-cpu-decoding-1-asm.o16295 295 296 296 -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-decoding-1-asm.asm
r61538 r65575 36 36 ; 37 37 BS3_INSTANTIATE_TEMPLATE_ESSENTIALS "bs3-cpu-decoding-1-template.mac" 38 BS3_INSTANTIATE_COMMON_TEMPLATE "bs3-cpu-decoding-1-template.mac" 38 39 -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-decoding-1-template.mac
r61538 r65575 5 5 6 6 ; 7 ; Copyright (C) 2007-201 6Oracle Corporation7 ; Copyright (C) 2007-2017 Oracle Corporation 8 8 ; 9 9 ; This file is part of VirtualBox Open Source Edition (OSE), as … … 38 38 39 39 40 %ifdef BS3_INSTANTIATING_CMN 41 42 BS3_PROC_BEGIN_CMN bs3CpuDecoding1_LoadXmm0, BS3_PBC_NEAR 43 BS3_CALL_CONV_PROLOG 1 44 push xBP 45 mov xBP, xSP 46 47 %if TMPL_BITS == 16 48 push es 49 push bx 50 les bx, [xBP + xCB + cbCurRetAddr] 51 movupd xmm0, [es:bx] 52 pop bx 53 pop es 54 %else 55 mov xAX, [xBP + xCB + cbCurRetAddr] 56 movupd xmm0, [xAX] 57 %endif 58 59 leave 60 BS3_CALL_CONV_EPILOG 1 61 BS3_HYBRID_RET 62 BS3_PROC_END_CMN bs3CpuDecoding1_LoadXmm0 63 64 65 BS3_PROC_BEGIN_CMN bs3CpuDecoding1_LoadXmm1, BS3_PBC_NEAR 66 BS3_CALL_CONV_PROLOG 1 67 push xBP 68 mov xBP, xSP 69 70 %if TMPL_BITS == 16 71 push es 72 push bx 73 les bx, [xBP + xCB + cbCurRetAddr] 74 movupd xmm1, [es:bx] 75 pop bx 76 pop es 77 %else 78 mov xAX, [xBP + xCB + cbCurRetAddr] 79 movupd xmm1, [xAX] 80 %endif 81 82 leave 83 BS3_CALL_CONV_EPILOG 1 84 BS3_HYBRID_RET 85 BS3_PROC_END_CMN bs3CpuDecoding1_LoadXmm1 86 87 88 BS3_PROC_BEGIN_CMN bs3CpuDecoding1_SaveXmm0, BS3_PBC_NEAR 89 BS3_CALL_CONV_PROLOG 1 90 push xBP 91 mov xBP, xSP 92 93 %if TMPL_BITS == 16 94 push es 95 push bx 96 les bx, [xBP + xCB + cbCurRetAddr] 97 movupd [es:bx], xmm0 98 pop bx 99 pop es 100 %else 101 mov xAX, [xBP + xCB + cbCurRetAddr] 102 movupd [xAX], xmm0 103 %endif 104 105 leave 106 BS3_CALL_CONV_EPILOG 1 107 BS3_HYBRID_RET 108 BS3_PROC_END_CMN bs3CpuDecoding1_SaveXmm0 109 110 111 %endif 112 40 113 %include "bs3kit-template-footer.mac" ; reset environment 41 114 -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-decoding-1.c32
r65556 r65575 33 33 34 34 35 /* bs3-cpu-decoding-1-template.mac: */ 36 BS3_DECL_NEAR(void) BS3_CMN_NM(bs3CpuDecoding1_LoadXmm0)(PCRTUINT128U); 37 BS3_DECL_NEAR(void) BS3_CMN_NM(bs3CpuDecoding1_LoadXmm1)(PCRTUINT128U); 38 BS3_DECL_NEAR(void) BS3_CMN_NM(bs3CpuDecoding1_SaveXmm0)(PRTUINT128U); 39 40 35 41 /********************************************************************************************************************************* 36 42 * Structures and Typedefs * … … 67 73 #define RM_EAX_SIB_DISP8 ((1 << X86_MODRM_MOD_SHIFT) | (X86_GREG_xAX << X86_MODRM_REG_SHIFT) | 4) 68 74 #define RM_EAX_SIB_DISP32 ((2 << X86_MODRM_MOD_SHIFT) | (X86_GREG_xAX << X86_MODRM_REG_SHIFT) | 4) 75 76 #define RM_XMM0_XMM1 ((3 << X86_MODRM_MOD_SHIFT) | (0 << X86_MODRM_REG_SHIFT) | 1) 69 77 70 78 #define SIB_EBX_X1_NONE ((0 << X86_SIB_SCALE_SHIFT) | (4 << X86_SIB_INDEX_SHIFT) | (X86_GREG_xBX)) … … 1093 1101 1094 1102 1103 1104 /** 1105 * Checks various prefix encodings with the CMPPS, CMPPD, CMPSS and CMPSD 1106 * instructions to try figure out how they are decoded. 1107 * 1108 * The important thing to check here is that unlike CRC32/MOVBE the operand size 1109 * prefix (66h) is ignored when the F2h and F3h prefixes are used. We also 1110 * check that the prefix ordering is irrelevant and that the last one of F2h and 1111 * F3h wins. 1112 * 1113 */ 1114 static void DecodeCmppsCmppdCmpssCmpsd(void) 1115 { 1116 uint8_t BS3_FAR *pbPages; 1117 1118 /* Check that the instructions are supported. */ 1119 if ( !(g_uBs3CpuDetected & BS3CPU_F_CPUID) 1120 || (ASMCpuId_EDX(1) & (X86_CPUID_FEATURE_EDX_SSE | X86_CPUID_FEATURE_EDX_SSE2)) 1121 != (X86_CPUID_FEATURE_EDX_SSE | X86_CPUID_FEATURE_EDX_SSE2) ) 1122 { 1123 Bs3TestSkipped("SSE and/or SSE2 are not supported"); 1124 return; 1125 } 1126 1127 /* Setup a guarded page. */ 1128 pbPages = Bs3MemGuardedTestPageAlloc(BS3MEMKIND_FLAT32); 1129 if (pbPages) 1130 { 1131 unsigned iTest; 1132 BS3REGCTX Ctx; 1133 BS3TRAPFRAME TrapFrame; 1134 BS3REGCTX ExpectCtxPf; 1135 BS3REGCTX ExpectCtxUd; 1136 static const struct 1137 { 1138 RTUINT128U Xmm0Expect; 1139 uint8_t bXcpt; 1140 uint8_t cbOpcodes; 1141 uint8_t abOpcodes[18]; 1142 } s_aTests[] = 1143 { 1144 #define BECRC_IN_XMM1 RTUINT128_INIT_C(0x76547654bbaa9988, 0x7766554433221100) 1145 #define BECRC_IN_XMM0 RTUINT128_INIT_C(0x765476549988bbaa, 0x7766554400112233) 1146 #define BECRC_OUT_PS RTUINT128_INIT_C(0xffffffff00000000, 0xffffffff00000000) /* No prefix. */ 1147 #define BECRC_OUT_PD RTUINT128_INIT_C(0x0000000000000000, 0x0000000000000000) /* P_OZ (66h) */ 1148 #define BECRC_OUT_SS RTUINT128_INIT_C(0x765476549988bbaa, 0x7766554400000000) /* P_RN (f3h) */ 1149 #define BECRC_OUT_SD RTUINT128_INIT_C(0x765476549988bbaa, 0x0000000000000000) /* P_RZ (f2h) */ 1150 1151 /* We use imm8=0 which checks for equality, with the subvalue result being all 1152 F's if equal and all zeros if not equal. The input values are choosen such 1153 that the 4 variants produces different results in xmm0. */ 1154 /* CMPPS xmm0, xmm1, 0: 0f c2 /r ib ; Compares four 32-bit subvalues. */ 1155 /* CMPPD xmm0, xmm1, 0: 66 0f c2 /r ib ; Compares two 64-bit subvalues. */ 1156 /* CMPSS xmm0, xmm1, 0: f3 0f c2 /r ib ; Compares two 32-bit subvalues, top 64-bit remains unchanged. */ 1157 /* CMPSD xmm0, xmm1, 0: f2 0f c2 /r ib ; Compares one 64-bit subvalue, top 64-bit remains unchanged. */ 1158 1159 /* base forms. */ 1160 { BECRC_OUT_PS, X86_XCPT_PF, 4, { 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1161 { BECRC_OUT_PD, X86_XCPT_PF, 5, { P_OZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1162 { BECRC_OUT_SS, X86_XCPT_PF, 5, { P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1163 { BECRC_OUT_SD, X86_XCPT_PF, 5, { P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1164 1165 /* Skylake ignores the 66h prefix with both f3h (P_RN) and f2h (P_RZ). */ 1166 { BECRC_OUT_SS, X86_XCPT_PF, 6, { P_OZ, P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1167 { BECRC_OUT_SS, X86_XCPT_PF, 6, { P_RN, P_OZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1168 { BECRC_OUT_SD, X86_XCPT_PF, 6, { P_OZ, P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1169 { BECRC_OUT_SD, X86_XCPT_PF, 6, { P_RZ, P_OZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1170 1171 /* Throw in segment prefixes and address size prefixes. */ 1172 { BECRC_OUT_PS, X86_XCPT_PF, 5, { P_ES, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1173 { BECRC_OUT_PS, X86_XCPT_PF, 6, { P_ES, P_SS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1174 { BECRC_OUT_PS, X86_XCPT_PF, 5, { P_AZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1175 { BECRC_OUT_PS, X86_XCPT_PF, 6, { P_AZ, P_CS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1176 1177 { BECRC_OUT_PD, X86_XCPT_PF, 6, { P_ES, P_OZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1178 { BECRC_OUT_PD, X86_XCPT_PF, 6, { P_OZ, P_ES, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1179 { BECRC_OUT_PD, X86_XCPT_PF, 7, { P_ES, P_SS, P_OZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1180 { BECRC_OUT_PD, X86_XCPT_PF, 7, { P_ES, P_OZ, P_SS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1181 { BECRC_OUT_PD, X86_XCPT_PF, 7, { P_OZ, P_ES, P_SS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1182 { BECRC_OUT_PD, X86_XCPT_PF, 6, { P_AZ, P_OZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1183 { BECRC_OUT_PD, X86_XCPT_PF, 6, { P_OZ, P_AZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1184 { BECRC_OUT_PD, X86_XCPT_PF, 7, { P_AZ, P_CS, P_OZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1185 { BECRC_OUT_PD, X86_XCPT_PF, 7, { P_AZ, P_OZ, P_CS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1186 { BECRC_OUT_PD, X86_XCPT_PF, 7, { P_OZ, P_AZ, P_CS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1187 1188 { BECRC_OUT_SS, X86_XCPT_PF, 6, { P_ES, P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1189 { BECRC_OUT_SS, X86_XCPT_PF, 6, { P_RN, P_ES, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1190 { BECRC_OUT_SS, X86_XCPT_PF, 7, { P_ES, P_SS, P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1191 { BECRC_OUT_SS, X86_XCPT_PF, 7, { P_ES, P_RN, P_SS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1192 { BECRC_OUT_SS, X86_XCPT_PF, 7, { P_RN, P_ES, P_SS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1193 { BECRC_OUT_SS, X86_XCPT_PF, 6, { P_AZ, P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1194 { BECRC_OUT_SS, X86_XCPT_PF, 6, { P_RN, P_AZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1195 { BECRC_OUT_SS, X86_XCPT_PF, 7, { P_AZ, P_CS, P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1196 { BECRC_OUT_SS, X86_XCPT_PF, 7, { P_AZ, P_RN, P_CS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1197 { BECRC_OUT_SS, X86_XCPT_PF, 7, { P_RN, P_AZ, P_CS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1198 { BECRC_OUT_SS, X86_XCPT_PF, 8, { P_OZ, P_RN, P_AZ, P_CS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1199 { BECRC_OUT_SS, X86_XCPT_PF, 8, { P_RN, P_OZ, P_AZ, P_CS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1200 { BECRC_OUT_SS, X86_XCPT_PF, 8, { P_RN, P_AZ, P_OZ, P_CS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1201 { BECRC_OUT_SS, X86_XCPT_PF, 8, { P_RN, P_AZ, P_CS, P_OZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1202 1203 { BECRC_OUT_SD, X86_XCPT_PF, 6, { P_ES, P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1204 { BECRC_OUT_SD, X86_XCPT_PF, 6, { P_RZ, P_ES, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1205 { BECRC_OUT_SD, X86_XCPT_PF, 7, { P_ES, P_SS, P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1206 { BECRC_OUT_SD, X86_XCPT_PF, 7, { P_ES, P_RZ, P_SS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1207 { BECRC_OUT_SD, X86_XCPT_PF, 7, { P_RZ, P_ES, P_SS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1208 { BECRC_OUT_SD, X86_XCPT_PF, 6, { P_AZ, P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1209 { BECRC_OUT_SD, X86_XCPT_PF, 6, { P_RZ, P_AZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1210 { BECRC_OUT_SD, X86_XCPT_PF, 7, { P_AZ, P_CS, P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1211 { BECRC_OUT_SD, X86_XCPT_PF, 7, { P_AZ, P_RZ, P_CS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1212 { BECRC_OUT_SD, X86_XCPT_PF, 7, { P_RZ, P_AZ, P_CS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1213 { BECRC_OUT_SD, X86_XCPT_PF, 8, { P_OZ, P_RZ, P_AZ, P_CS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1214 { BECRC_OUT_SD, X86_XCPT_PF, 8, { P_RZ, P_OZ, P_AZ, P_CS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1215 { BECRC_OUT_SD, X86_XCPT_PF, 8, { P_RZ, P_AZ, P_OZ, P_CS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1216 { BECRC_OUT_SD, X86_XCPT_PF, 8, { P_RZ, P_AZ, P_CS, P_OZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1217 1218 /* Pit f2h against f3h, on skylake the last prefix wins. */ 1219 { BECRC_OUT_SS, X86_XCPT_PF, 6, { P_RZ, P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1220 { BECRC_OUT_SS, X86_XCPT_PF, 7, { P_RZ, P_RZ, P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1221 { BECRC_OUT_SS, X86_XCPT_PF, 7, { P_RN, P_RZ, P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1222 { BECRC_OUT_SS, X86_XCPT_PF, 7, { P_RZ, P_RN, P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1223 { BECRC_OUT_SS, X86_XCPT_PF, 8, { P_RZ, P_RZ, P_RZ, P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1224 { BECRC_OUT_SS, X86_XCPT_PF, 8, { P_RZ, P_RZ, P_RN, P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1225 { BECRC_OUT_SS, X86_XCPT_PF, 8, { P_RZ, P_RN, P_RZ, P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1226 { BECRC_OUT_SS, X86_XCPT_PF, 8, { P_RN, P_RZ, P_RZ, P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1227 { BECRC_OUT_SS, X86_XCPT_PF, 8, { P_RN, P_RN, P_RZ, P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1228 { BECRC_OUT_SS, X86_XCPT_PF, 8, { P_RZ, P_RN, P_RN, P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1229 1230 { BECRC_OUT_SD, X86_XCPT_PF, 6, { P_RN, P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1231 { BECRC_OUT_SD, X86_XCPT_PF, 7, { P_RN, P_RN, P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1232 { BECRC_OUT_SD, X86_XCPT_PF, 7, { P_RZ, P_RN, P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1233 { BECRC_OUT_SD, X86_XCPT_PF, 7, { P_RN, P_RZ, P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1234 { BECRC_OUT_SD, X86_XCPT_PF, 8, { P_RN, P_RN, P_RN, P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1235 { BECRC_OUT_SD, X86_XCPT_PF, 8, { P_RN, P_RN, P_RZ, P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1236 { BECRC_OUT_SD, X86_XCPT_PF, 8, { P_RN, P_RZ, P_RN, P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1237 { BECRC_OUT_SD, X86_XCPT_PF, 8, { P_RZ, P_RN, P_RN, P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1238 { BECRC_OUT_SD, X86_XCPT_PF, 8, { P_RZ, P_RZ, P_RN, P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1239 { BECRC_OUT_SD, X86_XCPT_PF, 8, { P_RN, P_RZ, P_RZ, P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1240 }; 1241 RTUINT128U InXmm0 = BECRC_IN_XMM0; 1242 RTUINT128U InXmm1 = BECRC_IN_XMM1; 1243 RTUINT128U OutXmm0 = RTUINT128_INIT_C(0xeeeeeeeeeeeeeeee, 0xcccccccccccccccc); 1244 1245 Bs3MemZero(&Ctx, sizeof(Ctx)); 1246 Bs3MemZero(&ExpectCtxPf, sizeof(ExpectCtxPf)); 1247 Bs3MemZero(&ExpectCtxUd, sizeof(ExpectCtxUd)); 1248 Bs3MemZero(&TrapFrame, sizeof(TrapFrame)); 1249 1250 /* Enable SSE. */ 1251 ASMSetCR0((ASMGetCR0() & ~(X86_CR0_EM | X86_CR0_TS)) | X86_CR0_MP); 1252 ASMSetCR4(ASMGetCR4() | X86_CR4_OSFXSR); 1253 1254 /* Create a test context. */ 1255 Bs3RegCtxSaveEx(&Ctx, BS3_MODE_CODE_32, 512); 1256 Ctx.rax.u = BECRC_EAX; 1257 Ctx.rbx.u = (uintptr_t)pbPages; 1258 1259 /* Create expected result contexts. */ 1260 Bs3MemCpy(&ExpectCtxPf, &Ctx, sizeof(ExpectCtxPf)); 1261 ExpectCtxPf.rflags.u32 |= X86_EFL_RF; 1262 ExpectCtxPf.rip.u = (uintptr_t)&pbPages[X86_PAGE_SIZE]; 1263 ExpectCtxPf.cr2.u = (uintptr_t)&pbPages[X86_PAGE_SIZE]; 1264 1265 Bs3MemCpy(&ExpectCtxUd, &Ctx, sizeof(ExpectCtxUd)); 1266 ExpectCtxUd.rflags.u32 |= X86_EFL_RF; 1267 1268 /* Loop thru the tests. */ 1269 g_usBs3TestStep = 0; 1270 for (iTest = 0; iTest < RT_ELEMENTS(s_aTests); iTest++) 1271 { 1272 unsigned const cbOpcodes = s_aTests[iTest].cbOpcodes; 1273 uint8_t BS3_FAR *pbRip = &pbPages[X86_PAGE_SIZE - cbOpcodes]; 1274 1275 Bs3MemCpy(pbRip, s_aTests[iTest].abOpcodes, cbOpcodes); 1276 Bs3RegCtxSetRipCsFromFlat(&Ctx, (uintptr_t)pbRip); 1277 ExpectCtxUd.rip = Ctx.rip; 1278 #if 0 1279 Bs3TestPrintf("iTest=%d pbRip=%p cbOpcodes=%d: %.*Rhxs\n", 1280 iTest, pbRip, cbOpcodes, cbOpcodes, s_aTests[iTest].abOpcodes); 1281 //Bs3RegCtxPrint(&Ctx); 1282 #endif 1283 BS3_CMN_NM(bs3CpuDecoding1_LoadXmm0)(&InXmm0); 1284 BS3_CMN_NM(bs3CpuDecoding1_LoadXmm1)(&InXmm1); 1285 Bs3TrapSetJmpAndRestore(&Ctx, &TrapFrame); 1286 BS3_CMN_NM(bs3CpuDecoding1_SaveXmm0)(&OutXmm0); 1287 1288 if ( !Bs3TestCheckRegCtxEx(&TrapFrame.Ctx, s_aTests[iTest].bXcpt == X86_XCPT_UD ? &ExpectCtxUd : &ExpectCtxPf, 1289 0 /*cbPcAdjust*/, 0 /*cbSpAdjust*/, 0 /*fExtraEfl*/, "mode", iTest) 1290 || TrapFrame.bXcpt != s_aTests[iTest].bXcpt 1291 || OutXmm0.s.Lo != s_aTests[iTest].Xmm0Expect.s.Lo 1292 || OutXmm0.s.Hi != s_aTests[iTest].Xmm0Expect.s.Hi) 1293 { 1294 Bs3TestFailedF("iTest=%d cbOpcodes=%d: %.*Rhxs\n", iTest, cbOpcodes, cbOpcodes, s_aTests[iTest].abOpcodes); 1295 if (TrapFrame.bXcpt != s_aTests[iTest].bXcpt) 1296 Bs3TestFailedF("Expected bXcpt=%#x, got %#x\n", s_aTests[iTest].bXcpt, TrapFrame.bXcpt); 1297 if ( OutXmm0.s.Lo != s_aTests[iTest].Xmm0Expect.s.Lo 1298 || OutXmm0.s.Hi != s_aTests[iTest].Xmm0Expect.s.Hi) 1299 Bs3TestFailedF("Expected XMM0=%08RX32:%08RX32:%08RX32:%08RX32, not %08RX32:%08RX32:%08RX32:%08RX32\n", 1300 s_aTests[iTest].Xmm0Expect.DWords.dw3, s_aTests[iTest].Xmm0Expect.DWords.dw2, 1301 s_aTests[iTest].Xmm0Expect.DWords.dw1, s_aTests[iTest].Xmm0Expect.DWords.dw0, 1302 OutXmm0.DWords.dw3, OutXmm0.DWords.dw2, OutXmm0.DWords.dw1, OutXmm0.DWords.dw0); 1303 } 1304 } 1305 1306 Bs3MemGuardedTestPageFree(pbPages); 1307 } 1308 else 1309 Bs3TestFailed("Failed to allocate two pages!\n"); 1310 } 1311 1312 1095 1313 BS3_DECL(void) Main_pp32() 1096 1314 { 1097 1315 Bs3TestInit("bs3-cpu-decoding-1"); 1098 1316 Bs3TestPrintf("g_uBs3CpuDetected=%#x\n", g_uBs3CpuDetected); 1317 1318 Bs3TestSub("CMPPS, CMPPD, CMPSS, CMPSD"); 1319 DecodeCmppsCmppdCmpssCmpsd(); 1099 1320 1100 1321 Bs3TestSub("MOVBE vs CRC32");
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