Changeset 65761 in vbox

Timestamp:

Feb 13, 2017 12:15:26 PM (8 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

113476

Message:

IEM: VEX decoding updates.

Location:

trunk/src/VBox/VMM

Files:

• VMMAll/IEMAllInstructionsOneByte.cpp.h (modified) (3 diffs)
• include/IEMInternal.h (modified) (1 diff)

trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsOneByte.cpp.h

@@ -5249 +5249 @@
 FNIEMOP_DEF(iemOp_les_Gv_Mp_vex2)
 {
+    /* The LES instruction is invalid 64-bit mode. In legacy and
+       compatability mode it is invalid with MOD=3.
+       The use as a VEX prefix is made possible by assigning the inverted
+       REX.R to the top MOD bit, and the top bit in the inverted register
+       specifier to the bottom MOD bit, thereby effectively limiting 32-bit
+       to accessing registers 0..7 in this VEX form. */
     uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
     if (   pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT
@@ -5254 +5260 @@
     {
         IEMOP_MNEMONIC(vex2_prefix, "2-byte-vex");
-        /* The LES instruction is invalid 64-bit mode. In legacy and
-           compatability mode it is invalid with MOD=3.
-           The use as a VEX prefix is made possible by assigning the inverted
-           REX.R to the top MOD bit, and the top bit in the inverted register
-           specifier to the bottom MOD bit, thereby effectively limiting 32-bit
-           to accessing registers 0..7 in this VEX form. */
-        /** @todo VEX: Just use new tables for it. */
+        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx)
+        {
+            uint8_t bOpcode; IEM_OPCODE_GET_NEXT_U8(&bOpcode);
+            if (   (  pVCpu->iem.s.fPrefixes
+                    & (IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REPZ | IEM_OP_PRF_REPNZ | IEM_OP_PRF_LOCK | IEM_OP_PRF_REX))
+                == 0)
+            {
+                pVCpu->iem.s.fPrefixes |= IEM_OP_PRF_VEX;
+                pVCpu->iem.s.uRexReg    = ~bRm >> (7 - 3);
+                pVCpu->iem.s.uVex3rdReg = (~bRm >> 3) & 0xf;
+                pVCpu->iem.s.uVexLength = (bRm >> 2) & 1;
+                pVCpu->iem.s.idxPrefix  = bRm & 0x3;
+
+                /** @todo VEX: Just use new tables and decoders. */
+                IEMOP_BITCH_ABOUT_STUB();
+                return VERR_IEM_INSTR_NOT_IMPLEMENTED;
+            }
+            Log(("VEX2: Invalid prefix mix!\n"));
+        }
+        else
+            Log(("VEX2: AVX support disabled!\n"));
+
+        /* @todo does intel completely decode the sequence with SIB/disp before \#UD? */
         return IEMOP_RAISE_INVALID_OPCODE();
     }
@@ -5288 +5310 @@
 
     IEMOP_MNEMONIC(vex3_prefix, "3-byte-vex");
-    /** @todo Test when exctly the VEX conformance checks kick in during
-     * instruction decoding and fetching (using \#PF). */
-    uint8_t bVex1;   IEM_OPCODE_GET_NEXT_U8(&bVex1);
-    uint8_t bVex2;   IEM_OPCODE_GET_NEXT_U8(&bVex2);
-    uint8_t bOpcode; IEM_OPCODE_GET_NEXT_U8(&bOpcode);
-#if 0 /* will make sense of this next week... */
-    if (   !(pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REPNZ | IEM_OP_PRF_REPZ | IEM_OP_PRF_REPZ | IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REX))
-        &&
-        )
-    {
-
-    }
-#endif
-
-    /** @todo VEX: Just use new tables for it. */
+    if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx)
+    {
+        /** @todo Test when exctly the VEX conformance checks kick in during
+         * instruction decoding and fetching (using \#PF). */
+        uint8_t bVex2;   IEM_OPCODE_GET_NEXT_U8(&bVex2);
+        uint8_t bOpcode; IEM_OPCODE_GET_NEXT_U8(&bOpcode);
+        if (   (  pVCpu->iem.s.fPrefixes
+                & (IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REPZ | IEM_OP_PRF_REPNZ | IEM_OP_PRF_LOCK | IEM_OP_PRF_REX))
+            == 0)
+        {
+            pVCpu->iem.s.fPrefixes |= IEM_OP_PRF_VEX;
+            if (bVex2 & 0x80 /* VEX.W */)
+                pVCpu->iem.s.fPrefixes |= IEM_OP_PRF_SIZE_REX_W;
+            pVCpu->iem.s.uRexReg    = ~bRm >> (7 - 3);
+            pVCpu->iem.s.uRexIndex  = ~bRm >> (6 - 3);
+            pVCpu->iem.s.uRexB      = ~bRm >> (5 - 3);
+            pVCpu->iem.s.uVex3rdReg = (~bVex2 >> 3) & 0xf;
+            pVCpu->iem.s.uVexLength = (bVex2 >> 2) & 1;
+            pVCpu->iem.s.idxPrefix  = bVex2 & 0x3;
+
+            /** @todo VEX: Just use new tables and decoders. */
+            switch (bRm & 0xf)
+            {
+                case 1: /* 0x0f lead opcode byte. */
+                    IEMOP_BITCH_ABOUT_STUB();
+                    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
+
+                case 2: /* 0x0f 0x38 lead opcode bytes. */
+                    IEMOP_BITCH_ABOUT_STUB();
+                    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
+
+                case 3: /* 0x0f 0x3a lead opcode bytes. */
+                    IEMOP_BITCH_ABOUT_STUB();
+                    return VERR_IEM_INSTR_NOT_IMPLEMENTED;
+
+                default:
+                    Log(("VEX3: Invalid vvvv value: %#x!\n", bRm & 0xf));
+                    return IEMOP_RAISE_INVALID_OPCODE();
+            }
+        }
+        else
+            Log(("VEX3: Invalid prefix mix!\n"));
+    }
+    else
+        Log(("VEX3: AVX support disabled!\n"));
     return IEMOP_RAISE_INVALID_OPCODE();
 }

trunk/src/VBox/VMM/include/IEMInternal.h

@@ -837 +837 @@
  * For testing whether any REX prefix is present, use  IEM_OP_PRF_REX instead. */
 #define IEM_OP_PRF_REX_MASK  (IEM_OP_PRF_REX | IEM_OP_PRF_REX_R | IEM_OP_PRF_REX_B | IEM_OP_PRF_REX_X | IEM_OP_PRF_SIZE_REX_W )
+
+#define IEM_OP_PRF_VEX                  RT_BIT_32(28) /**< Indiciates VEX prefix. */
+#define IEM_OP_PRF_EVEX                 RT_BIT_32(29) /**< Indiciates EVEX prefix. */
 /** @} */