Changeset 65776 in vbox for trunk/src/VBox/ValidationKit/bootsectors
- Timestamp:
- Feb 13, 2017 5:06:27 PM (8 years ago)
- Location:
- trunk/src/VBox/ValidationKit/bootsectors
- Files:
-
- 2 edited
-
bootsector2-cpu-instr-1-template.mac (modified) (2 diffs)
-
bs3-cpu-decoding-1.c32 (modified) (11 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/ValidationKit/bootsectors/bootsector2-cpu-instr-1-template.mac
r62484 r65776 95 95 BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_SIZE_OP, 0fh, 0aeh, MY_RM ; (used in group) 96 96 BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_LOCK, 0fh, 0aeh, MY_RM ; (used in group) 97 BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_REPNZ, 0fh, 0aeh, MY_RM ; (used in group) 97 98 BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_REPZ, 0fh, 0aeh, MY_RM ; (used in group) 98 BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_REPNZ, 0fh, 0aeh, MY_RM ; (used in group)99 99 %ifdef TMPL_64BIT 100 100 %assign MY_REX 0x40 … … 111 111 BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_SIZE_OP, MY_REX, 0fh, 0aeh, MY_RM ; (used in group) 112 112 BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_LOCK, MY_REX, 0fh, 0aeh, MY_RM ; (used in group) 113 BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_REPNZ, MY_REX, 0fh, 0aeh, MY_RM ; (used in group) 113 114 BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_REPZ, MY_REX, 0fh, 0aeh, MY_RM ; (used in group) 114 BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_REPNZ, MY_REX, 0fh, 0aeh, MY_RM ; (used in group)115 115 %assign MY_REX (MY_REX + 1) 116 116 %endrep -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-decoding-1.c32
r65617 r65776 63 63 #define P_AZ X86_OP_PRF_SIZE_ADDR 64 64 #define P_LK X86_OP_PRF_LOCK 65 #define P_RN X86_OP_PRF_REPNZ 65 66 #define P_RZ X86_OP_PRF_REPZ 66 #define P_RN X86_OP_PRF_REPNZ67 67 68 68 #define RM_EAX_EAX ((3 << X86_MODRM_MOD_SHIFT) | (X86_GREG_xAX << X86_MODRM_REG_SHIFT) | (X86_GREG_xAX)) … … 105 105 { F_UD, 3, { 0x0f, 0x7a, RM_EAX_EAX, } }, 106 106 { F_UD, 3+1, { P_LK, 0x0f, 0x7a, RM_EAX_EAX, } }, 107 { F_UD, 3+1, { P_RZ, 0x0f, 0x7a, RM_EAX_EAX, } }, 107 108 { F_UD, 3+1, { P_RN, 0x0f, 0x7a, RM_EAX_EAX, } }, 108 { F_UD, 3+1, { P_RZ, 0x0f, 0x7a, RM_EAX_EAX, } },109 109 { F_UD, 3+2, { P_LK, P_LK, 0x0f, 0x7a, RM_EAX_EAX, } }, 110 110 { F_UD, 4, { 0x0f, 0x7a, RM_EAX_DEREF_EBX_DISP8, 0 } }, 111 111 { F_UD, 4+1, { P_LK, 0x0f, 0x7a, RM_EAX_DEREF_EBX_DISP8, 0 } }, 112 { F_UD, 4+1, { P_RZ, 0x0f, 0x7a, RM_EAX_DEREF_EBX_DISP8, 0 } }, 112 113 { F_UD, 4+1, { P_RN, 0x0f, 0x7a, RM_EAX_DEREF_EBX_DISP8, 0 } }, 113 { F_UD, 4+1, { P_RZ, 0x0f, 0x7a, RM_EAX_DEREF_EBX_DISP8, 0 } },114 114 { F_UD, 4+2, { P_LK, P_LK, 0x0f, 0x7a, RM_EAX_DEREF_EBX_DISP8, 0 } }, 115 115 { F_UD, 7, { 0x0f, 0x7a, RM_EAX_DEREF_EBX_DISP32, 0, 0, 0, 0 } }, 116 116 { F_UD, 7+1, { P_LK, 0x0f, 0x7a, RM_EAX_DEREF_EBX_DISP32, 0, 0, 0, 0 } }, 117 { F_UD, 7+1, { P_RZ, 0x0f, 0x7a, RM_EAX_DEREF_EBX_DISP32, 0, 0, 0, 0 } }, 117 118 { F_UD, 7+1, { P_RN, 0x0f, 0x7a, RM_EAX_DEREF_EBX_DISP32, 0, 0, 0, 0 } }, 118 { F_UD, 7+1, { P_RZ, 0x0f, 0x7a, RM_EAX_DEREF_EBX_DISP32, 0, 0, 0, 0 } },119 119 { F_UD, 7+2, { P_LK, P_LK, 0x0f, 0x7a, RM_EAX_DEREF_EBX_DISP32, 0, 0, 0, 0 } }, 120 120 #endif … … 123 123 { F_UD, 3, { 0x0f, 0x7b, RM_EAX_EAX, } }, 124 124 { F_UD, 3+1, { P_LK, 0x0f, 0x7b, RM_EAX_EAX, } }, 125 { F_UD, 3+1, { P_RZ, 0x0f, 0x7b, RM_EAX_EAX, } }, 125 126 { F_UD, 3+1, { P_RN, 0x0f, 0x7b, RM_EAX_EAX, } }, 126 { F_UD, 3+1, { P_RZ, 0x0f, 0x7b, RM_EAX_EAX, } },127 127 { F_UD, 3+2, { P_LK, P_LK, 0x0f, 0x7b, RM_EAX_EAX, } }, 128 128 #endif … … 131 131 { F_UD, 3, { 0x0f, 0x24, RM_EAX_EAX, } }, 132 132 { F_UD, 3+1, { P_LK, 0x0f, 0x24, RM_EAX_EAX, } }, 133 { F_UD, 3+1, { P_RZ, 0x0f, 0x24, RM_EAX_EAX, } }, 133 134 { F_UD, 3+1, { P_RN, 0x0f, 0x24, RM_EAX_EAX, } }, 134 { F_UD, 3+1, { P_RZ, 0x0f, 0x24, RM_EAX_EAX, } },135 135 { F_UD, 3+2, { P_LK, P_LK, 0x0f, 0x24, RM_EAX_EAX, } }, 136 136 #endif … … 140 140 { F_486 | F_OK, 3, { 0x0f, 0xc1, RM_EAX_EAX, } }, 141 141 { F_486 | F_OK, 4, { P_OZ, 0x0f, 0xc1, RM_EAX_EAX, } }, 142 { F_486 | F_OK, 4, { P_RZ, 0x0f, 0xc1, RM_EAX_EAX, } }, 143 { F_486 | F_OK, 5, { P_OZ, P_RZ, 0x0f, 0xc1, RM_EAX_EAX, } }, 144 { F_486 | F_OK, 5, { P_RZ, P_OZ, 0x0f, 0xc1, RM_EAX_EAX, } }, 142 145 { F_486 | F_OK, 4, { P_RN, 0x0f, 0xc1, RM_EAX_EAX, } }, 143 146 { F_486 | F_OK, 5, { P_OZ, P_RN, 0x0f, 0xc1, RM_EAX_EAX, } }, 144 147 { F_486 | F_OK, 5, { P_RN, P_OZ, 0x0f, 0xc1, RM_EAX_EAX, } }, 145 { F_486 | F_OK, 4, { P_RZ, 0x0f, 0xc1, RM_EAX_EAX, } },146 { F_486 | F_OK, 5, { P_OZ, P_RZ, 0x0f, 0xc1, RM_EAX_EAX, } },147 { F_486 | F_OK, 5, { P_RZ, P_OZ, 0x0f, 0xc1, RM_EAX_EAX, } },148 148 #endif 149 149 #if 0 … … 152 152 { F_SSE2 | F_OK, 3, { 0x0f, 0xc3, RM_EAX_DEREF_EBX, } }, 153 153 { F_SSE2 | F_UD, 4, { P_OZ, 0x0f, 0xc3, RM_EAX_DEREF_EBX, } }, /* invalid */ 154 { F_SSE2 | F_UD, 4, { P_RZ, 0x0f, 0xc3, RM_EAX_DEREF_EBX, } }, /* invalid */ 154 155 { F_SSE2 | F_UD, 4, { P_RN, 0x0f, 0xc3, RM_EAX_DEREF_EBX, } }, /* invalid */ 155 { F_SSE2 | F_UD, 4, { P_RZ, 0x0f, 0xc3, RM_EAX_DEREF_EBX, } }, /* invalid */156 156 { F_SSE2 | F_UD, 4, { P_LK, 0x0f, 0xc3, RM_EAX_DEREF_EBX, } }, /* invalid */ 157 { F_SSE2 | F_UD, 5, { P_R Z, P_LK, 0x0f, 0xc3, RM_EAX_DEREF_EBX, } }, /* invalid */157 { F_SSE2 | F_UD, 5, { P_RN, P_LK, 0x0f, 0xc3, RM_EAX_DEREF_EBX, } }, /* invalid */ 158 158 #endif 159 159 #if 0 160 160 /* The lddqu instruction requires a 0xf2 prefix, intel only lists 0x66 and empty 161 161 prefix for it. Check what they really mean by that*/ 162 { F_SSE3 | F_UD, 4, { P_R Z, 0x0f, 0xf0, RM_EAX_EAX, } }, /* invalid - reg, reg */163 { F_SSE3 | F_OK, 4, { P_R Z, 0x0f, 0xf0, RM_EAX_DEREF_EBX, } },164 { F_SSE3 | F_OK, 5, { P_R Z, P_RZ, 0x0f, 0xf0, RM_EAX_DEREF_EBX, } },162 { F_SSE3 | F_UD, 4, { P_RN, 0x0f, 0xf0, RM_EAX_EAX, } }, /* invalid - reg, reg */ 163 { F_SSE3 | F_OK, 4, { P_RN, 0x0f, 0xf0, RM_EAX_DEREF_EBX, } }, 164 { F_SSE3 | F_OK, 5, { P_RN, P_RN, 0x0f, 0xf0, RM_EAX_DEREF_EBX, } }, 165 165 { F_SSE3 | F_UD, 3, { 0x0f, 0xf0, RM_EAX_DEREF_EBX, } }, 166 { F_SSE3 | F_UD, 4, { P_R N, 0x0f, 0xf0, RM_EAX_DEREF_EBX, } },166 { F_SSE3 | F_UD, 4, { P_RZ, 0x0f, 0xf0, RM_EAX_DEREF_EBX, } }, 167 167 { F_SSE3 | F_UD, 4, { P_OZ, 0x0f, 0xf0, RM_EAX_DEREF_EBX, } }, 168 168 { F_SSE3 | F_UD, 4, { P_LK, 0x0f, 0xf0, RM_EAX_DEREF_EBX, } }, 169 { F_SSE3 | F_UD, 5, { P_R Z, P_RN, 0x0f, 0xf0, RM_EAX_DEREF_EBX, } },170 { F_SSE3 | F_OK, 5, { P_R Z, P_OZ, 0x0f, 0xf0, RM_EAX_DEREF_EBX, } }, // AMD,why?171 { F_SSE3 | F_UD, 5, { P_R Z, P_LK, 0x0f, 0xf0, RM_EAX_DEREF_EBX, } },172 { F_SSE3 | F_OK, 5, { P_R N, P_RZ, 0x0f, 0xf0, RM_EAX_DEREF_EBX, } },173 { F_SSE3 | F_OK, 5, { P_OZ, P_R Z, 0x0f, 0xf0, RM_EAX_DEREF_EBX, } },174 { F_SSE3 | F_UD, 5, { P_LK, P_R Z, 0x0f, 0xf0, RM_EAX_DEREF_EBX, } },175 { F_SSE3 | F_OK, 5, { P_OZ, P_R Z, 0x0f, 0xf0, RM_EAX_DEREF_EBX, } },176 { F_SSE3 | F_OK, 6,{ P_OZ, P_R N, P_RZ, 0x0f, 0xf0, RM_EAX_DEREF_EBX, } },169 { F_SSE3 | F_UD, 5, { P_RN, P_RZ, 0x0f, 0xf0, RM_EAX_DEREF_EBX, } }, 170 { F_SSE3 | F_OK, 5, { P_RN, P_OZ, 0x0f, 0xf0, RM_EAX_DEREF_EBX, } }, // AMD,why? 171 { F_SSE3 | F_UD, 5, { P_RN, P_LK, 0x0f, 0xf0, RM_EAX_DEREF_EBX, } }, 172 { F_SSE3 | F_OK, 5, { P_RZ, P_RN, 0x0f, 0xf0, RM_EAX_DEREF_EBX, } }, 173 { F_SSE3 | F_OK, 5, { P_OZ, P_RN, 0x0f, 0xf0, RM_EAX_DEREF_EBX, } }, 174 { F_SSE3 | F_UD, 5, { P_LK, P_RN, 0x0f, 0xf0, RM_EAX_DEREF_EBX, } }, 175 { F_SSE3 | F_OK, 5, { P_OZ, P_RN, 0x0f, 0xf0, RM_EAX_DEREF_EBX, } }, 176 { F_SSE3 | F_OK, 6,{ P_OZ, P_RZ, P_RN, 0x0f, 0xf0, RM_EAX_DEREF_EBX, } }, 177 177 #endif 178 178 #if 0 179 179 { F_SSE2 | F_OK, 3, { 0x0f, 0x7e, RM_EAX_EAX, } }, 180 180 { F_SSE2 | F_OK, 4, { P_OZ, 0x0f, 0x7e, RM_EAX_EAX, } }, 181 { F_SSE2 | F_UD, 5,{ P_R Z, P_OZ, 0x0f, 0x7e, RM_EAX_EAX, } }, // WTF?182 { F_SSE2 | F_UD, 5,{ P_OZ, P_R Z, 0x0f, 0x7e, RM_EAX_EAX, } },183 { F_SSE2 | F_OK, 5,{ P_R N, P_OZ, 0x0f, 0x7e, RM_EAX_EAX, } },184 { F_SSE2 | F_OK, 4, { P_R N, 0x0f, 0x7e, RM_EAX_EAX, } },185 { F_SSE2 | F_UD, 4, { P_R Z, 0x0f, 0x7e, RM_EAX_EAX, } },181 { F_SSE2 | F_UD, 5,{ P_RN, P_OZ, 0x0f, 0x7e, RM_EAX_EAX, } }, // WTF? 182 { F_SSE2 | F_UD, 5,{ P_OZ, P_RN, 0x0f, 0x7e, RM_EAX_EAX, } }, 183 { F_SSE2 | F_OK, 5,{ P_RZ, P_OZ, 0x0f, 0x7e, RM_EAX_EAX, } }, 184 { F_SSE2 | F_OK, 4, { P_RZ, 0x0f, 0x7e, RM_EAX_EAX, } }, 185 { F_SSE2 | F_UD, 4, { P_RN, 0x0f, 0x7e, RM_EAX_EAX, } }, 186 186 #endif 187 187 /** @todo crc32 / movbe */ … … 767 767 { 0, { 0 }, UD_F_NOT_NO_PFX }, 768 768 { 1, { P_OZ }, UD_F_NOT_OZ_PFX }, 769 { 1, { P_R Z}, UD_F_NOT_RZ_PFX },770 { 1, { P_R N}, UD_F_NOT_RN_PFX },769 { 1, { P_RN }, UD_F_NOT_RZ_PFX }, 770 { 1, { P_RZ }, UD_F_NOT_RN_PFX }, 771 771 { 1, { P_LK }, UD_F_NOT_LK_PFX }, 772 772 { 2, { P_OZ, P_OZ }, UD_F_NOT_OZ_PFX | UD_F_NOT_OZ_PFX }, 773 { 2, { P_R Z, P_OZ }, UD_F_NOT_RZ_PFX | UD_F_NOT_OZ_PFX },774 { 2, { P_R N, P_OZ }, UD_F_NOT_RN_PFX | UD_F_NOT_OZ_PFX },773 { 2, { P_RN, P_OZ }, UD_F_NOT_RZ_PFX | UD_F_NOT_OZ_PFX }, 774 { 2, { P_RZ, P_OZ }, UD_F_NOT_RN_PFX | UD_F_NOT_OZ_PFX }, 775 775 { 2, { P_LK, P_OZ }, UD_F_NOT_LK_PFX | UD_F_NOT_OZ_PFX }, 776 { 2, { P_OZ, P_R Z}, UD_F_NOT_OZ_PFX | UD_F_NOT_RZ_PFX },777 { 2, { P_R Z, P_RZ}, UD_F_NOT_RZ_PFX | UD_F_NOT_RZ_PFX },778 { 2, { P_R N, P_RZ}, UD_F_NOT_RN_PFX | UD_F_NOT_RZ_PFX },779 { 2, { P_LK, P_R Z}, UD_F_NOT_LK_PFX | UD_F_NOT_RZ_PFX },780 { 2, { P_OZ, P_R N}, UD_F_NOT_OZ_PFX | UD_F_NOT_RN_PFX },781 { 2, { P_R Z, P_RN}, UD_F_NOT_RZ_PFX | UD_F_NOT_RN_PFX },782 { 2, { P_R N, P_RN}, UD_F_NOT_RN_PFX | UD_F_NOT_RN_PFX },783 { 2, { P_LK, P_R N}, UD_F_NOT_LK_PFX | UD_F_NOT_RN_PFX },776 { 2, { P_OZ, P_RN }, UD_F_NOT_OZ_PFX | UD_F_NOT_RZ_PFX }, 777 { 2, { P_RN, P_RN }, UD_F_NOT_RZ_PFX | UD_F_NOT_RZ_PFX }, 778 { 2, { P_RZ, P_RN }, UD_F_NOT_RN_PFX | UD_F_NOT_RZ_PFX }, 779 { 2, { P_LK, P_RN }, UD_F_NOT_LK_PFX | UD_F_NOT_RZ_PFX }, 780 { 2, { P_OZ, P_RZ }, UD_F_NOT_OZ_PFX | UD_F_NOT_RN_PFX }, 781 { 2, { P_RN, P_RZ }, UD_F_NOT_RZ_PFX | UD_F_NOT_RN_PFX }, 782 { 2, { P_RZ, P_RZ }, UD_F_NOT_RN_PFX | UD_F_NOT_RN_PFX }, 783 { 2, { P_LK, P_RZ }, UD_F_NOT_LK_PFX | UD_F_NOT_RN_PFX }, 784 784 { 2, { P_OZ, P_LK }, UD_F_NOT_OZ_PFX | UD_F_NOT_LK_PFX }, 785 { 2, { P_R Z, P_LK }, UD_F_NOT_RZ_PFX | UD_F_NOT_LK_PFX },786 { 2, { P_R N, P_LK }, UD_F_NOT_RN_PFX | UD_F_NOT_LK_PFX },785 { 2, { P_RN, P_LK }, UD_F_NOT_RZ_PFX | UD_F_NOT_LK_PFX }, 786 { 2, { P_RZ, P_LK }, UD_F_NOT_RN_PFX | UD_F_NOT_LK_PFX }, 787 787 { 2, { P_LK, P_LK }, UD_F_NOT_LK_PFX | UD_F_NOT_LK_PFX }, 788 788 }; … … 997 997 { BECRC_MEM_BE32, 0, X86_XCPT_PF, 4, { 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } }, 998 998 { BECRC_MEM_BE16, 1, X86_XCPT_PF, 5, { P_OZ, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } }, 999 { BECRC_MEM_ORG, 2, X86_XCPT_PF, 5, { P_R Z, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } },1000 { BECRC_MEM_ORG, 3, X86_XCPT_PF, 6, { P_OZ, P_R Z, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } },1001 { BECRC_MEM_ORG, 4, X86_XCPT_UD, 5, { P_R N, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } }, /* undefined F3 (P_RN) */1002 { BECRC_MEM_ORG, 4, X86_XCPT_UD, 6, { P_OZ, P_R N, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } }, /* undefined F3 (P_RN) */999 { BECRC_MEM_ORG, 2, X86_XCPT_PF, 5, { P_RN, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } }, 1000 { BECRC_MEM_ORG, 3, X86_XCPT_PF, 6, { P_OZ, P_RN, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } }, 1001 { BECRC_MEM_ORG, 4, X86_XCPT_UD, 5, { P_RZ, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } }, /* undefined F3 (P_RZ) */ 1002 { BECRC_MEM_ORG, 4, X86_XCPT_UD, 6, { P_OZ, P_RZ, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } }, /* undefined F3 (P_RZ) */ 1003 1003 1004 1004 /* CRC32 eax, [word ebx]: Simple variations showing it doesn't matter where the prefixes are placed. */ 1005 { BECRC_MEM_ORG, 3, X86_XCPT_PF, 6, { P_R Z, P_OZ, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } },1006 { BECRC_MEM_ORG, 3, X86_XCPT_PF, 7, { P_R Z, P_OZ, P_ES, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } },1007 { BECRC_MEM_ORG, 3, X86_XCPT_PF, 8, { P_R Z, P_SS, P_OZ, P_ES, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } },1008 { BECRC_MEM_ORG, 3, X86_XCPT_PF, 8, { P_R Z, P_SS, P_ES, P_OZ, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } },1009 { BECRC_MEM_ORG, 3, X86_XCPT_PF, 8, { P_SS, P_R Z, P_ES, P_OZ, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } },1010 { BECRC_MEM_ORG, 3, X86_XCPT_PF, 8, { P_SS, P_ES, P_R Z, P_OZ, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } },1011 { BECRC_MEM_ORG, 3, X86_XCPT_PF, 8, { P_SS, P_ES, P_OZ, P_R Z, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } },1012 { BECRC_MEM_ORG, 3, X86_XCPT_PF, 8, { P_SS, P_OZ, P_ES, P_R Z, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } },1013 { BECRC_MEM_ORG, 3, X86_XCPT_PF, 8, { P_OZ, P_SS, P_ES, P_R Z, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } },1005 { BECRC_MEM_ORG, 3, X86_XCPT_PF, 6, { P_RN, P_OZ, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } }, 1006 { BECRC_MEM_ORG, 3, X86_XCPT_PF, 7, { P_RN, P_OZ, P_ES, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } }, 1007 { BECRC_MEM_ORG, 3, X86_XCPT_PF, 8, { P_RN, P_SS, P_OZ, P_ES, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } }, 1008 { BECRC_MEM_ORG, 3, X86_XCPT_PF, 8, { P_RN, P_SS, P_ES, P_OZ, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } }, 1009 { BECRC_MEM_ORG, 3, X86_XCPT_PF, 8, { P_SS, P_RN, P_ES, P_OZ, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } }, 1010 { BECRC_MEM_ORG, 3, X86_XCPT_PF, 8, { P_SS, P_ES, P_RN, P_OZ, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } }, 1011 { BECRC_MEM_ORG, 3, X86_XCPT_PF, 8, { P_SS, P_ES, P_OZ, P_RN, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } }, 1012 { BECRC_MEM_ORG, 3, X86_XCPT_PF, 8, { P_SS, P_OZ, P_ES, P_RN, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } }, 1013 { BECRC_MEM_ORG, 3, X86_XCPT_PF, 8, { P_OZ, P_SS, P_ES, P_RN, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } }, 1014 1014 1015 1015 /* CRC32 eax, [word ebx]: Throw the F3h prefix into the mix. The last of F3 and F2 wins on skylake+jaguar. */ 1016 { BECRC_MEM_ORG, 3, X86_XCPT_PF, 7, { P_R N, P_OZ, P_RZ, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } },1017 { BECRC_MEM_ORG, 3, X86_XCPT_PF, 7, { P_OZ, P_R N, P_RZ, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } },1018 { BECRC_MEM_ORG, 4, X86_XCPT_UD, 7, { P_OZ, P_R Z, P_RN, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } },1019 { BECRC_MEM_ORG, 3, X86_XCPT_PF, 8, { P_OZ, P_R Z, P_RN, P_RZ, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } },1020 { BECRC_MEM_ORG, 3, X86_XCPT_PF, 8, { P_R Z, P_RN, P_OZ, P_RZ, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } },1021 { BECRC_MEM_ORG, 3, X86_XCPT_PF, 8, { P_R Z, P_RN, P_RZ, P_OZ, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } },1022 1023 { BECRC_MEM_ORG, 4, X86_XCPT_UD, 7, { P_OZ, P_R Z, P_RN, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } },1016 { BECRC_MEM_ORG, 3, X86_XCPT_PF, 7, { P_RZ, P_OZ, P_RN, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } }, 1017 { BECRC_MEM_ORG, 3, X86_XCPT_PF, 7, { P_OZ, P_RZ, P_RN, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } }, 1018 { BECRC_MEM_ORG, 4, X86_XCPT_UD, 7, { P_OZ, P_RN, P_RZ, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } }, 1019 { BECRC_MEM_ORG, 3, X86_XCPT_PF, 8, { P_OZ, P_RN, P_RZ, P_RN, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } }, 1020 { BECRC_MEM_ORG, 3, X86_XCPT_PF, 8, { P_RN, P_RZ, P_OZ, P_RN, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } }, 1021 { BECRC_MEM_ORG, 3, X86_XCPT_PF, 8, { P_RN, P_RZ, P_RN, P_OZ, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } }, 1022 1023 { BECRC_MEM_ORG, 4, X86_XCPT_UD, 7, { P_OZ, P_RN, P_RZ, 0x0f, 0x38, 0xf1, RM_EAX_DEREF_EBX } }, 1024 1024 }; 1025 1025 … … 1146 1146 #define BECRC_OUT_PS RTUINT128_INIT_C(0xffffffff00000000, 0xffffffff00000000) /* No prefix. */ 1147 1147 #define BECRC_OUT_PD RTUINT128_INIT_C(0x0000000000000000, 0x0000000000000000) /* P_OZ (66h) */ 1148 #define BECRC_OUT_SS RTUINT128_INIT_C(0x765476549988bbaa, 0x7766554400000000) /* P_R N(f3h) */1149 #define BECRC_OUT_SD RTUINT128_INIT_C(0x765476549988bbaa, 0x0000000000000000) /* P_R Z(f2h) */1148 #define BECRC_OUT_SS RTUINT128_INIT_C(0x765476549988bbaa, 0x7766554400000000) /* P_RZ (f3h) */ 1149 #define BECRC_OUT_SD RTUINT128_INIT_C(0x765476549988bbaa, 0x0000000000000000) /* P_RN (f2h) */ 1150 1150 1151 1151 /* We use imm8=0 which checks for equality, with the subvalue result being all … … 1160 1160 { BECRC_OUT_PS, X86_XCPT_PF, 4, { 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1161 1161 { BECRC_OUT_PD, X86_XCPT_PF, 5, { P_OZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1162 { BECRC_OUT_SS, X86_XCPT_PF, 5, { P_R N, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1163 { BECRC_OUT_SD, X86_XCPT_PF, 5, { P_R Z, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1164 1165 /* Skylake+jaguar ignores the 66h prefix with both f3h (P_R N) and f2h (P_RZ). */1166 { BECRC_OUT_SS, X86_XCPT_PF, 6, { P_OZ, P_R N, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1167 { BECRC_OUT_SS, X86_XCPT_PF, 6, { P_R N, P_OZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1168 { BECRC_OUT_SD, X86_XCPT_PF, 6, { P_OZ, P_R Z, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1169 { BECRC_OUT_SD, X86_XCPT_PF, 6, { P_R Z, P_OZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1162 { BECRC_OUT_SS, X86_XCPT_PF, 5, { P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1163 { BECRC_OUT_SD, X86_XCPT_PF, 5, { P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1164 1165 /* Skylake+jaguar ignores the 66h prefix with both f3h (P_RZ) and f2h (P_RN). */ 1166 { BECRC_OUT_SS, X86_XCPT_PF, 6, { P_OZ, P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1167 { BECRC_OUT_SS, X86_XCPT_PF, 6, { P_RZ, P_OZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1168 { BECRC_OUT_SD, X86_XCPT_PF, 6, { P_OZ, P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1169 { BECRC_OUT_SD, X86_XCPT_PF, 6, { P_RN, P_OZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1170 1170 1171 1171 /* Throw in segment prefixes and address size prefixes. */ … … 1186 1186 { BECRC_OUT_PD, X86_XCPT_PF, 7, { P_OZ, P_AZ, P_CS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1187 1187 1188 { BECRC_OUT_SS, X86_XCPT_PF, 6, { P_ES, P_R N, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1189 { BECRC_OUT_SS, X86_XCPT_PF, 6, { P_R N, P_ES, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1190 { BECRC_OUT_SS, X86_XCPT_PF, 7, { P_ES, P_SS, P_R N, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1191 { BECRC_OUT_SS, X86_XCPT_PF, 7, { P_ES, P_R N, P_SS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1192 { BECRC_OUT_SS, X86_XCPT_PF, 7, { P_R N, P_ES, P_SS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1193 { BECRC_OUT_SS, X86_XCPT_PF, 6, { P_AZ, P_R N, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1194 { BECRC_OUT_SS, X86_XCPT_PF, 6, { P_R N, P_AZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1195 { BECRC_OUT_SS, X86_XCPT_PF, 7, { P_AZ, P_CS, P_R N, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1196 { BECRC_OUT_SS, X86_XCPT_PF, 7, { P_AZ, P_R N, P_CS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1197 { BECRC_OUT_SS, X86_XCPT_PF, 7, { P_R N, P_AZ, P_CS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1198 { BECRC_OUT_SS, X86_XCPT_PF, 8, { P_OZ, P_R N, P_AZ, P_CS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1199 { BECRC_OUT_SS, X86_XCPT_PF, 8, { P_R N, P_OZ, P_AZ, P_CS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1200 { BECRC_OUT_SS, X86_XCPT_PF, 8, { P_R N, P_AZ, P_OZ, P_CS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1201 { BECRC_OUT_SS, X86_XCPT_PF, 8, { P_R N, P_AZ, P_CS, P_OZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1202 1203 { BECRC_OUT_SD, X86_XCPT_PF, 6, { P_ES, P_R Z, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1204 { BECRC_OUT_SD, X86_XCPT_PF, 6, { P_R Z, P_ES, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1205 { BECRC_OUT_SD, X86_XCPT_PF, 7, { P_ES, P_SS, P_R Z, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1206 { BECRC_OUT_SD, X86_XCPT_PF, 7, { P_ES, P_R Z, P_SS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1207 { BECRC_OUT_SD, X86_XCPT_PF, 7, { P_R Z, P_ES, P_SS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1208 { BECRC_OUT_SD, X86_XCPT_PF, 6, { P_AZ, P_R Z, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1209 { BECRC_OUT_SD, X86_XCPT_PF, 6, { P_R Z, P_AZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1210 { BECRC_OUT_SD, X86_XCPT_PF, 7, { P_AZ, P_CS, P_R Z, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1211 { BECRC_OUT_SD, X86_XCPT_PF, 7, { P_AZ, P_R Z, P_CS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1212 { BECRC_OUT_SD, X86_XCPT_PF, 7, { P_R Z, P_AZ, P_CS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1213 { BECRC_OUT_SD, X86_XCPT_PF, 8, { P_OZ, P_R Z, P_AZ, P_CS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1214 { BECRC_OUT_SD, X86_XCPT_PF, 8, { P_R Z, P_OZ, P_AZ, P_CS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1215 { BECRC_OUT_SD, X86_XCPT_PF, 8, { P_R Z, P_AZ, P_OZ, P_CS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1216 { BECRC_OUT_SD, X86_XCPT_PF, 8, { P_R Z, P_AZ, P_CS, P_OZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1188 { BECRC_OUT_SS, X86_XCPT_PF, 6, { P_ES, P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1189 { BECRC_OUT_SS, X86_XCPT_PF, 6, { P_RZ, P_ES, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1190 { BECRC_OUT_SS, X86_XCPT_PF, 7, { P_ES, P_SS, P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1191 { BECRC_OUT_SS, X86_XCPT_PF, 7, { P_ES, P_RZ, P_SS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1192 { BECRC_OUT_SS, X86_XCPT_PF, 7, { P_RZ, P_ES, P_SS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1193 { BECRC_OUT_SS, X86_XCPT_PF, 6, { P_AZ, P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1194 { BECRC_OUT_SS, X86_XCPT_PF, 6, { P_RZ, P_AZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1195 { BECRC_OUT_SS, X86_XCPT_PF, 7, { P_AZ, P_CS, P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1196 { BECRC_OUT_SS, X86_XCPT_PF, 7, { P_AZ, P_RZ, P_CS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1197 { BECRC_OUT_SS, X86_XCPT_PF, 7, { P_RZ, P_AZ, P_CS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1198 { BECRC_OUT_SS, X86_XCPT_PF, 8, { P_OZ, P_RZ, P_AZ, P_CS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1199 { BECRC_OUT_SS, X86_XCPT_PF, 8, { P_RZ, P_OZ, P_AZ, P_CS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1200 { BECRC_OUT_SS, X86_XCPT_PF, 8, { P_RZ, P_AZ, P_OZ, P_CS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1201 { BECRC_OUT_SS, X86_XCPT_PF, 8, { P_RZ, P_AZ, P_CS, P_OZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1202 1203 { BECRC_OUT_SD, X86_XCPT_PF, 6, { P_ES, P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1204 { BECRC_OUT_SD, X86_XCPT_PF, 6, { P_RN, P_ES, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1205 { BECRC_OUT_SD, X86_XCPT_PF, 7, { P_ES, P_SS, P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1206 { BECRC_OUT_SD, X86_XCPT_PF, 7, { P_ES, P_RN, P_SS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1207 { BECRC_OUT_SD, X86_XCPT_PF, 7, { P_RN, P_ES, P_SS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1208 { BECRC_OUT_SD, X86_XCPT_PF, 6, { P_AZ, P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1209 { BECRC_OUT_SD, X86_XCPT_PF, 6, { P_RN, P_AZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1210 { BECRC_OUT_SD, X86_XCPT_PF, 7, { P_AZ, P_CS, P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1211 { BECRC_OUT_SD, X86_XCPT_PF, 7, { P_AZ, P_RN, P_CS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1212 { BECRC_OUT_SD, X86_XCPT_PF, 7, { P_RN, P_AZ, P_CS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1213 { BECRC_OUT_SD, X86_XCPT_PF, 8, { P_OZ, P_RN, P_AZ, P_CS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1214 { BECRC_OUT_SD, X86_XCPT_PF, 8, { P_RN, P_OZ, P_AZ, P_CS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1215 { BECRC_OUT_SD, X86_XCPT_PF, 8, { P_RN, P_AZ, P_OZ, P_CS, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1216 { BECRC_OUT_SD, X86_XCPT_PF, 8, { P_RN, P_AZ, P_CS, P_OZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1217 1217 1218 1218 /* Pit f2h against f3h, on skylake+jaguar the last prefix wins. */ 1219 { BECRC_OUT_SS, X86_XCPT_PF, 6, { P_R Z, P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1220 { BECRC_OUT_SS, X86_XCPT_PF, 7, { P_R Z, P_RZ, P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1221 { BECRC_OUT_SS, X86_XCPT_PF, 7, { P_R N, P_RZ, P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1222 { BECRC_OUT_SS, X86_XCPT_PF, 7, { P_R Z, P_RN, P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1223 { BECRC_OUT_SS, X86_XCPT_PF, 8, { P_R Z, P_RZ, P_RZ, P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1224 { BECRC_OUT_SS, X86_XCPT_PF, 8, { P_R Z, P_RZ, P_RN, P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1225 { BECRC_OUT_SS, X86_XCPT_PF, 8, { P_R Z, P_RN, P_RZ, P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1226 { BECRC_OUT_SS, X86_XCPT_PF, 8, { P_R N, P_RZ, P_RZ, P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1227 { BECRC_OUT_SS, X86_XCPT_PF, 8, { P_R N, P_RN, P_RZ, P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1228 { BECRC_OUT_SS, X86_XCPT_PF, 8, { P_R Z, P_RN, P_RN, P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1229 1230 { BECRC_OUT_SD, X86_XCPT_PF, 6, { P_R N, P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1231 { BECRC_OUT_SD, X86_XCPT_PF, 7, { P_R N, P_RN, P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1232 { BECRC_OUT_SD, X86_XCPT_PF, 7, { P_R Z, P_RN, P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1233 { BECRC_OUT_SD, X86_XCPT_PF, 7, { P_R N, P_RZ, P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1234 { BECRC_OUT_SD, X86_XCPT_PF, 8, { P_R N, P_RN, P_RN, P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1235 { BECRC_OUT_SD, X86_XCPT_PF, 8, { P_R N, P_RN, P_RZ, P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1236 { BECRC_OUT_SD, X86_XCPT_PF, 8, { P_R N, P_RZ, P_RN, P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1237 { BECRC_OUT_SD, X86_XCPT_PF, 8, { P_R Z, P_RN, P_RN, P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1238 { BECRC_OUT_SD, X86_XCPT_PF, 8, { P_R Z, P_RZ, P_RN, P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1239 { BECRC_OUT_SD, X86_XCPT_PF, 8, { P_R N, P_RZ, P_RZ, P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } },1219 { BECRC_OUT_SS, X86_XCPT_PF, 6, { P_RN, P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1220 { BECRC_OUT_SS, X86_XCPT_PF, 7, { P_RN, P_RN, P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1221 { BECRC_OUT_SS, X86_XCPT_PF, 7, { P_RZ, P_RN, P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1222 { BECRC_OUT_SS, X86_XCPT_PF, 7, { P_RN, P_RZ, P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1223 { BECRC_OUT_SS, X86_XCPT_PF, 8, { P_RN, P_RN, P_RN, P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1224 { BECRC_OUT_SS, X86_XCPT_PF, 8, { P_RN, P_RN, P_RZ, P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1225 { BECRC_OUT_SS, X86_XCPT_PF, 8, { P_RN, P_RZ, P_RN, P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1226 { BECRC_OUT_SS, X86_XCPT_PF, 8, { P_RZ, P_RN, P_RN, P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1227 { BECRC_OUT_SS, X86_XCPT_PF, 8, { P_RZ, P_RZ, P_RN, P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1228 { BECRC_OUT_SS, X86_XCPT_PF, 8, { P_RN, P_RZ, P_RZ, P_RZ, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1229 1230 { BECRC_OUT_SD, X86_XCPT_PF, 6, { P_RZ, P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1231 { BECRC_OUT_SD, X86_XCPT_PF, 7, { P_RZ, P_RZ, P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1232 { BECRC_OUT_SD, X86_XCPT_PF, 7, { P_RN, P_RZ, P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1233 { BECRC_OUT_SD, X86_XCPT_PF, 7, { P_RZ, P_RN, P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1234 { BECRC_OUT_SD, X86_XCPT_PF, 8, { P_RZ, P_RZ, P_RZ, P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1235 { BECRC_OUT_SD, X86_XCPT_PF, 8, { P_RZ, P_RZ, P_RN, P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1236 { BECRC_OUT_SD, X86_XCPT_PF, 8, { P_RZ, P_RN, P_RZ, P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1237 { BECRC_OUT_SD, X86_XCPT_PF, 8, { P_RN, P_RZ, P_RZ, P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1238 { BECRC_OUT_SD, X86_XCPT_PF, 8, { P_RN, P_RN, P_RZ, P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1239 { BECRC_OUT_SD, X86_XCPT_PF, 8, { P_RZ, P_RN, P_RN, P_RN, 0x0f, 0xc2, RM_XMM0_XMM1, 0 } }, 1240 1240 }; 1241 1241 RTUINT128U InXmm0 = BECRC_IN_XMM0;
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