Changeset 65844 in vbox

Timestamp:

Feb 22, 2017 7:30:22 PM (8 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

113613

Message:

Devices/Bus: symbolic constants

Location:

trunk/src/VBox/Devices/Bus

Files:

• DevPCI.cpp (modified) (2 diffs)
• DevPciIch9.cpp (modified) (9 diffs)

trunk/src/VBox/Devices/Bus/DevPCI.cpp

@@ -615 +615 @@
                  * through the bridge but we want to be compliant to the spec.
                  */
-                if ((pGlobals->uPciBiosIo % 4096) != 0)
-                    pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
+                if ((pGlobals->uPciBiosIo % 4*_1K) != 0)
+                    pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*_1K);
                 Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosIo));
                 pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0);
 
                 /* The MMIO range for the bridge must be aligned to a 1MB boundary. */
-                if ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0)
-                    pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
+                if ((pGlobals->uPciBiosMmio % _1M) != 0)
+                    pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, _1M);
                 Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosMmio));
                 pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0));
@@ -643 +643 @@
                  * interface. Again this doesn't really matter here but we want to be compliant to the spec.
                  */
-                if ((u32IoAddressBase != pGlobals->uPciBiosIo) && ((pGlobals->uPciBiosIo % 4096) != 0))
+                if ((u32IoAddressBase != pGlobals->uPciBiosIo) && ((pGlobals->uPciBiosIo % 4*_1K) != 0))
                 {
                     /* The upper boundary must be one byte less than a 4KB boundary. */
-                    pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
+                    pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*_1K);
                 }
                 pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1);
 
                 /* Same with the MMIO limit register but with 1MB boundary here. */
-                if ((u32MMIOAddressBase != pGlobals->uPciBiosMmio) && ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0))
+                if ((u32MMIOAddressBase != pGlobals->uPciBiosMmio) && ((pGlobals->uPciBiosMmio % _1M) != 0))
                 {
                     /* The upper boundary must be one byte less than a 1MB boundary. */
-                    pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
+                    pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, _1M);
                 }
                 pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1);

trunk/src/VBox/Devices/Bus/DevPciIch9.cpp

@@ -1564 +1564 @@
      * through the bridge but we want to be compliant to the spec.
      */
-    if ((pPciRoot->uPciBiosIo % 4096) != 0)
-    {
-        pPciRoot->uPciBiosIo = RT_ALIGN_32(pPciRoot->uPciBiosIo, 4*1024);
+    if ((pPciRoot->uPciBiosIo % 4*_1K) != 0)
+    {
+        pPciRoot->uPciBiosIo = RT_ALIGN_32(pPciRoot->uPciBiosIo, 4*_1K);
         Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pPciRoot->uPciBiosIo));
     }
@@ -1572 +1572 @@
 
     /* The MMIO range for the bridge must be aligned to a 1MB boundary. */
-    if ((pPciRoot->uPciBiosMmio % (1024 * 1024)) != 0)
-    {
-        pPciRoot->uPciBiosMmio = RT_ALIGN_32(pPciRoot->uPciBiosMmio, 1024*1024);
+    if ((pPciRoot->uPciBiosMmio % _1M) != 0)
+    {
+        pPciRoot->uPciBiosMmio = RT_ALIGN_32(pPciRoot->uPciBiosMmio, _1M);
         Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pPciRoot->uPciBiosMmio));
     }
@@ -1594 +1594 @@
     {
         /* Need again alignment to a 4KB boundary. */
-        pPciRoot->uPciBiosIo = RT_ALIGN_32(pPciRoot->uPciBiosIo, 4*1024);
+        pPciRoot->uPciBiosIo = RT_ALIGN_32(pPciRoot->uPciBiosIo, 4*_1K);
         ich9pciBiosInitWriteConfig(pPciRoot, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pPciRoot->uPciBiosIo - 1) >> 8) & 0xf0, 1);
     }
@@ -1606 +1606 @@
     if (u32MMIOAddressBase != pPciRoot->uPciBiosMmio)
     {
-        pPciRoot->uPciBiosMmio = RT_ALIGN_32(pPciRoot->uPciBiosMmio, 1024*1024);
+        pPciRoot->uPciBiosMmio = RT_ALIGN_32(pPciRoot->uPciBiosMmio, _1M);
         ich9pciBiosInitWriteConfig(pPciRoot, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pPciRoot->uPciBiosMmio - 1) >> 16) & UINT32_C(0xfff0), 2);
     }
@@ -1889 +1889 @@
     Log(("BIOS init bridge (prefetch): %02x:%02x.%d\n", uBus, uDevFn >> 3, uDevFn & 7));
 
-    pPciRoot->uPciBiosMmio = RT_ALIGN_32(pPciRoot->uPciBiosMmio, 1024*1024);
-    pPciRoot->uPciBiosMmio64 = RT_ALIGN_64(pPciRoot->uPciBiosMmio64, 1024*1024);
+    pPciRoot->uPciBiosMmio = RT_ALIGN_32(pPciRoot->uPciBiosMmio, _1M);
+    pPciRoot->uPciBiosMmio64 = RT_ALIGN_64(pPciRoot->uPciBiosMmio64, _1M);
 
     /* Save values to compare later to. */
@@ -1911 +1911 @@
             return false;
         uBase = u64MMIOAddressBase;
-        uLimit = RT_ALIGN_64(pPciRoot->uPciBiosMmio64, 1024*1024) - 1;
+        uLimit = RT_ALIGN_64(pPciRoot->uPciBiosMmio64, _1M) - 1;
     }
     else
@@ -1918 +1918 @@
             return false;
         uBase = u32MMIOAddressBase;
-        uLimit = RT_ALIGN_32(pPciRoot->uPciBiosMmio, 1024*1024) - 1;
+        uLimit = RT_ALIGN_32(pPciRoot->uPciBiosMmio, _1M) - 1;
     }
     ich9pciBiosInitWriteConfig(pPciRoot, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, uBase >> 32, 4);
@@ -2282 +2282 @@
     else
     {
-        if (uAddress + cb < 4096)
+        if (uAddress + cb < 4*_1K)
             LogRel(("PCI: %8s/%u: Read from extended register %d fallen back to generic code\n",
                     pPciDev->pszNameR3, pPciDev->Int.s.CTX_SUFF(pDevIns)->iInstance, uAddress));
@@ -2697 +2697 @@
         }
     }
-    else if (uAddress + cb <= 4096)
+    else if (uAddress + cb <= 4*_1K)
         LogRel(("PCI: %8s/%u: Write to extended register %d fallen back to generic code\n",
                 pPciDev->pszNameR3, pPciDev->Int.s.CTX_SUFF(pDevIns)->iInstance, uAddress));