Changeset 65847 in vbox for trunk/src/VBox/Devices
- Timestamp:
- Feb 23, 2017 8:49:49 AM (8 years ago)
- Location:
- trunk/src/VBox/Devices/Bus
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/Bus/DevPCI.cpp
r65844 r65847 615 615 * through the bridge but we want to be compliant to the spec. 616 616 */ 617 if ((pGlobals->uPciBiosIo % 4*_1K) != 0)618 pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*_1K);617 if ((pGlobals->uPciBiosIo % _4K) != 0) 618 pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, _4K); 619 619 Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosIo)); 620 620 pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0); … … 643 643 * interface. Again this doesn't really matter here but we want to be compliant to the spec. 644 644 */ 645 if ((u32IoAddressBase != pGlobals->uPciBiosIo) && ((pGlobals->uPciBiosIo % 4*_1K) != 0))645 if ((u32IoAddressBase != pGlobals->uPciBiosIo) && ((pGlobals->uPciBiosIo % _4K) != 0)) 646 646 { 647 647 /* The upper boundary must be one byte less than a 4KB boundary. */ 648 pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*_1K);648 pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, _4K); 649 649 } 650 650 pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1); -
trunk/src/VBox/Devices/Bus/DevPciIch9.cpp
r65845 r65847 1567 1567 * through the bridge but we want to be compliant to the spec. 1568 1568 */ 1569 if ((pPciRoot->uPciBiosIo % 4*_1K) != 0)1570 { 1571 pPciRoot->uPciBiosIo = RT_ALIGN_32(pPciRoot->uPciBiosIo, 4*_1K);1569 if ((pPciRoot->uPciBiosIo % _4K) != 0) 1570 { 1571 pPciRoot->uPciBiosIo = RT_ALIGN_32(pPciRoot->uPciBiosIo, _4K); 1572 1572 Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pPciRoot->uPciBiosIo)); 1573 1573 } … … 1597 1597 { 1598 1598 /* Need again alignment to a 4KB boundary. */ 1599 pPciRoot->uPciBiosIo = RT_ALIGN_32(pPciRoot->uPciBiosIo, 4*_1K);1599 pPciRoot->uPciBiosIo = RT_ALIGN_32(pPciRoot->uPciBiosIo, _4K); 1600 1600 ich9pciBiosInitWriteConfig(pPciRoot, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pPciRoot->uPciBiosIo - 1) >> 8) & 0xf0, 1); 1601 1601 } … … 2287 2287 else 2288 2288 { 2289 if (uAddress + cb < 4*_1K)2289 if (uAddress + cb < _4K) 2290 2290 LogRel(("PCI: %8s/%u: Read from extended register %d fallen back to generic code\n", 2291 2291 pPciDev->pszNameR3, pPciDev->Int.s.CTX_SUFF(pDevIns)->iInstance, uAddress)); … … 2703 2703 } 2704 2704 } 2705 else if (uAddress + cb <= 4*_1K)2705 else if (uAddress + cb <= _4K) 2706 2706 LogRel(("PCI: %8s/%u: Write to extended register %d fallen back to generic code\n", 2707 2707 pPciDev->pszNameR3, pPciDev->Int.s.CTX_SUFF(pDevIns)->iInstance, uAddress));
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