VirtualBox

Changeset 66216 in vbox


Ignore:
Timestamp:
Mar 22, 2017 11:16:35 PM (8 years ago)
Author:
vboxsync
Message:

bs3-cpu-generated-1: SSE testing work (not quite there, but close).

Location:
trunk/src/VBox/ValidationKit/bootsectors
Files:
3 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c

    r66206 r66216  
    228228    BS3REGCTX               aInitialCtxs[4];
    229229
     230    /** The extended context. */
     231    PBS3EXTCTX              pExtCtx;
     232    /** The initial extended context. */
     233    PBS3EXTCTX              pInitialExtCtx;
     234
    230235    /** Memory operand scratch space. */
    231236    union
    … …  
    380385    /* [BS3CG1DST_OZ_R15] = */  BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
    381386
     387    /* [BS3CG1DST_FCW] = */         2,
     388    /* [BS3CG1DST_FSW] = */         2,
     389    /* [BS3CG1DST_FTW] = */         2,
     390    /* [BS3CG1DST_FOP] = */         2,
     391    /* [BS3CG1DST_FPUIP] = */       2,
     392    /* [BS3CG1DST_FPUCS] = */       2,
     393    /* [BS3CG1DST_FPUDP] = */       2,
     394    /* [BS3CG1DST_FPUDS] = */       2,
     395    /* [BS3CG1DST_MXCSR] = */       4,
     396    /* [BS3CG1DST_MXCSR_MASK] = */  4,
     397    /* [BS3CG1DST_ST0] = */         12,
     398    /* [BS3CG1DST_ST1] = */         12,
     399    /* [BS3CG1DST_ST2] = */         12,
     400    /* [BS3CG1DST_ST3] = */         12,
     401    /* [BS3CG1DST_ST4] = */         12,
     402    /* [BS3CG1DST_ST5] = */         12,
     403    /* [BS3CG1DST_ST6] = */         12,
     404    /* [BS3CG1DST_ST7] = */         12,
     405    /* [BS3CG1DST_MM0] = */         8,
     406    /* [BS3CG1DST_MM1] = */         8,
     407    /* [BS3CG1DST_MM2] = */         8,
     408    /* [BS3CG1DST_MM3] = */         8,
     409    /* [BS3CG1DST_MM4] = */         8,
     410    /* [BS3CG1DST_MM5] = */         8,
     411    /* [BS3CG1DST_MM6] = */         8,
     412    /* [BS3CG1DST_MM7] = */         8,
     413    /* [BS3CG1DST_XMM0] = */        16,
     414    /* [BS3CG1DST_XMM1] = */        16,
     415    /* [BS3CG1DST_XMM2] = */        16,
     416    /* [BS3CG1DST_XMM3] = */        16,
     417    /* [BS3CG1DST_XMM4] = */        16,
     418    /* [BS3CG1DST_XMM5] = */        16,
     419    /* [BS3CG1DST_XMM6] = */        16,
     420    /* [BS3CG1DST_XMM7] = */        16,
     421    /* [BS3CG1DST_XMM8] = */        16,
     422    /* [BS3CG1DST_XMM9] = */        16,
     423    /* [BS3CG1DST_XMM10] = */       16,
     424    /* [BS3CG1DST_XMM11] = */       16,
     425    /* [BS3CG1DST_XMM12] = */       16,
     426    /* [BS3CG1DST_XMM13] = */       16,
     427    /* [BS3CG1DST_XMM14] = */       16,
     428    /* [BS3CG1DST_XMM15] = */       16,
     429    /* [BS3CG1DST_YMM0] = */        32,
     430    /* [BS3CG1DST_YMM1] = */        32,
     431    /* [BS3CG1DST_YMM2] = */        32,
     432    /* [BS3CG1DST_YMM3] = */        32,
     433    /* [BS3CG1DST_YMM4] = */        32,
     434    /* [BS3CG1DST_YMM5] = */        32,
     435    /* [BS3CG1DST_YMM6] = */        32,
     436    /* [BS3CG1DST_YMM7] = */        32,
     437    /* [BS3CG1DST_YMM8] = */        32,
     438    /* [BS3CG1DST_YMM9] = */        32,
     439    /* [BS3CG1DST_YMM10] = */       32,
     440    /* [BS3CG1DST_YMM11] = */       32,
     441    /* [BS3CG1DST_YMM12] = */       32,
     442    /* [BS3CG1DST_YMM13] = */       32,
     443    /* [BS3CG1DST_YMM14] = */       32,
     444    /* [BS3CG1DST_YMM15] = */       32,
     445
    382446    /* [BS3CG1DST_VALUE_XCPT] = */ 1,
    383 
    384447};
     448AssertCompile(RT_ELEMENTS(g_acbBs3Cg1DstFields) == BS3CG1DST_END);
    385449
    386450/** Destination field offset indexed by bBS3CG1DST.
    … …  
    388452static const unsigned g_aoffBs3Cg1DstFields[] =
    389453{
    390     /* [BS3CG1DST_INVALID] = */ ~0U,
    391     /* [BS3CG1DST_OP1] = */     ~0U,
    392     /* [BS3CG1DST_OP2] = */     ~0U,
    393     /* [BS3CG1DST_OP3] = */     ~0U,
    394     /* [BS3CG1DST_OP4] = */     ~0U,
    395     /* [BS3CG1DST_EFL] = */     RT_OFFSETOF(BS3REGCTX, rflags),
    396     /* [BS3CG1DST_EFL_UNDEF]=*/ ~0, /* special field */
    397 
    398     /* [BS3CG1DST_AL] = */      RT_OFFSETOF(BS3REGCTX, rax.u8),
    399     /* [BS3CG1DST_CL] = */      RT_OFFSETOF(BS3REGCTX, rcx.u8),
    400     /* [BS3CG1DST_DL] = */      RT_OFFSETOF(BS3REGCTX, rdx.u8),
    401     /* [BS3CG1DST_BL] = */      RT_OFFSETOF(BS3REGCTX, rbx.u8),
    402     /* [BS3CG1DST_AH] = */      RT_OFFSETOF(BS3REGCTX, rax.b.bHi),
    403     /* [BS3CG1DST_CH] = */      RT_OFFSETOF(BS3REGCTX, rcx.b.bHi),
    404     /* [BS3CG1DST_DH] = */      RT_OFFSETOF(BS3REGCTX, rdx.b.bHi),
    405     /* [BS3CG1DST_BH] = */      RT_OFFSETOF(BS3REGCTX, rbx.b.bHi),
    406     /* [BS3CG1DST_SPL] = */     RT_OFFSETOF(BS3REGCTX, rsp.u8),
    407     /* [BS3CG1DST_BPL] = */     RT_OFFSETOF(BS3REGCTX, rbp.u8),
    408     /* [BS3CG1DST_SIL] = */     RT_OFFSETOF(BS3REGCTX, rsi.u8),
    409     /* [BS3CG1DST_DIL] = */     RT_OFFSETOF(BS3REGCTX, rdi.u8),
    410     /* [BS3CG1DST_R8L] = */     RT_OFFSETOF(BS3REGCTX, r8.u8),
    411     /* [BS3CG1DST_R9L] = */     RT_OFFSETOF(BS3REGCTX, r9.u8),
    412     /* [BS3CG1DST_R10L] = */    RT_OFFSETOF(BS3REGCTX, r10.u8),
    413     /* [BS3CG1DST_R11L] = */    RT_OFFSETOF(BS3REGCTX, r11.u8),
    414     /* [BS3CG1DST_R12L] = */    RT_OFFSETOF(BS3REGCTX, r12.u8),
    415     /* [BS3CG1DST_R13L] = */    RT_OFFSETOF(BS3REGCTX, r13.u8),
    416     /* [BS3CG1DST_R14L] = */    RT_OFFSETOF(BS3REGCTX, r14.u8),
    417     /* [BS3CG1DST_R15L] = */    RT_OFFSETOF(BS3REGCTX, r15.u8),
    418 
    419     /* [BS3CG1DST_AX] = */      RT_OFFSETOF(BS3REGCTX, rax.u16),
    420     /* [BS3CG1DST_CX] = */      RT_OFFSETOF(BS3REGCTX, rcx.u16),
    421     /* [BS3CG1DST_DX] = */      RT_OFFSETOF(BS3REGCTX, rdx.u16),
    422     /* [BS3CG1DST_BX] = */      RT_OFFSETOF(BS3REGCTX, rbx.u16),
    423     /* [BS3CG1DST_SP] = */      RT_OFFSETOF(BS3REGCTX, rsp.u16),
    424     /* [BS3CG1DST_BP] = */      RT_OFFSETOF(BS3REGCTX, rbp.u16),
    425     /* [BS3CG1DST_SI] = */      RT_OFFSETOF(BS3REGCTX, rsi.u16),
    426     /* [BS3CG1DST_DI] = */      RT_OFFSETOF(BS3REGCTX, rdi.u16),
    427     /* [BS3CG1DST_R8W] = */     RT_OFFSETOF(BS3REGCTX, r8.u16),
    428     /* [BS3CG1DST_R9W] = */     RT_OFFSETOF(BS3REGCTX, r9.u16),
    429     /* [BS3CG1DST_R10W] = */    RT_OFFSETOF(BS3REGCTX, r10.u16),
    430     /* [BS3CG1DST_R11W] = */    RT_OFFSETOF(BS3REGCTX, r11.u16),
    431     /* [BS3CG1DST_R12W] = */    RT_OFFSETOF(BS3REGCTX, r12.u16),
    432     /* [BS3CG1DST_R13W] = */    RT_OFFSETOF(BS3REGCTX, r13.u16),
    433     /* [BS3CG1DST_R14W] = */    RT_OFFSETOF(BS3REGCTX, r14.u16),
    434     /* [BS3CG1DST_R15W] = */    RT_OFFSETOF(BS3REGCTX, r15.u16),
    435 
    436     /* [BS3CG1DST_EAX] = */     RT_OFFSETOF(BS3REGCTX, rax.u32),
    437     /* [BS3CG1DST_ECX] = */     RT_OFFSETOF(BS3REGCTX, rcx.u32),
    438     /* [BS3CG1DST_EDX] = */     RT_OFFSETOF(BS3REGCTX, rdx.u32),
    439     /* [BS3CG1DST_EBX] = */     RT_OFFSETOF(BS3REGCTX, rbx.u32),
    440     /* [BS3CG1DST_ESP] = */     RT_OFFSETOF(BS3REGCTX, rsp.u32),
    441     /* [BS3CG1DST_EBP] = */     RT_OFFSETOF(BS3REGCTX, rbp.u32),
    442     /* [BS3CG1DST_ESI] = */     RT_OFFSETOF(BS3REGCTX, rsi.u32),
    443     /* [BS3CG1DST_EDI] = */     RT_OFFSETOF(BS3REGCTX, rdi.u32),
    444     /* [BS3CG1DST_R8D] = */     RT_OFFSETOF(BS3REGCTX, r8.u32),
    445     /* [BS3CG1DST_R9D] = */     RT_OFFSETOF(BS3REGCTX, r9.u32),
    446     /* [BS3CG1DST_R10D] = */    RT_OFFSETOF(BS3REGCTX, r10.u32),
    447     /* [BS3CG1DST_R11D] = */    RT_OFFSETOF(BS3REGCTX, r11.u32),
    448     /* [BS3CG1DST_R12D] = */    RT_OFFSETOF(BS3REGCTX, r12.u32),
    449     /* [BS3CG1DST_R13D] = */    RT_OFFSETOF(BS3REGCTX, r13.u32),
    450     /* [BS3CG1DST_R14D] = */    RT_OFFSETOF(BS3REGCTX, r14.u32),
    451     /* [BS3CG1DST_R15D] = */    RT_OFFSETOF(BS3REGCTX, r15.u32),
    452 
    453     /* [BS3CG1DST_RAX] = */     RT_OFFSETOF(BS3REGCTX, rax.u64),
    454     /* [BS3CG1DST_RCX] = */     RT_OFFSETOF(BS3REGCTX, rcx.u64),
    455     /* [BS3CG1DST_RDX] = */     RT_OFFSETOF(BS3REGCTX, rdx.u64),
    456     /* [BS3CG1DST_RBX] = */     RT_OFFSETOF(BS3REGCTX, rbx.u64),
    457     /* [BS3CG1DST_RSP] = */     RT_OFFSETOF(BS3REGCTX, rsp.u64),
    458     /* [BS3CG1DST_RBP] = */     RT_OFFSETOF(BS3REGCTX, rbp.u64),
    459     /* [BS3CG1DST_RSI] = */     RT_OFFSETOF(BS3REGCTX, rsi.u64),
    460     /* [BS3CG1DST_RDI] = */     RT_OFFSETOF(BS3REGCTX, rdi.u64),
    461     /* [BS3CG1DST_R8] = */      RT_OFFSETOF(BS3REGCTX, r8.u64),
    462     /* [BS3CG1DST_R9] = */      RT_OFFSETOF(BS3REGCTX, r9.u64),
    463     /* [BS3CG1DST_R10] = */     RT_OFFSETOF(BS3REGCTX, r10.u64),
    464     /* [BS3CG1DST_R11] = */     RT_OFFSETOF(BS3REGCTX, r11.u64),
    465     /* [BS3CG1DST_R12] = */     RT_OFFSETOF(BS3REGCTX, r12.u64),
    466     /* [BS3CG1DST_R13] = */     RT_OFFSETOF(BS3REGCTX, r13.u64),
    467     /* [BS3CG1DST_R14] = */     RT_OFFSETOF(BS3REGCTX, r14.u64),
    468     /* [BS3CG1DST_R15] = */     RT_OFFSETOF(BS3REGCTX, r15.u64),
    469 
    470     /* [BS3CG1DST_OZ_RAX] = */  RT_OFFSETOF(BS3REGCTX, rax),
    471     /* [BS3CG1DST_OZ_RCX] = */  RT_OFFSETOF(BS3REGCTX, rcx),
    472     /* [BS3CG1DST_OZ_RDX] = */  RT_OFFSETOF(BS3REGCTX, rdx),
    473     /* [BS3CG1DST_OZ_RBX] = */  RT_OFFSETOF(BS3REGCTX, rbx),
    474     /* [BS3CG1DST_OZ_RSP] = */  RT_OFFSETOF(BS3REGCTX, rsp),
    475     /* [BS3CG1DST_OZ_RBP] = */  RT_OFFSETOF(BS3REGCTX, rbp),
    476     /* [BS3CG1DST_OZ_RSI] = */  RT_OFFSETOF(BS3REGCTX, rsi),
    477     /* [BS3CG1DST_OZ_RDI] = */  RT_OFFSETOF(BS3REGCTX, rdi),
    478     /* [BS3CG1DST_OZ_R8] = */   RT_OFFSETOF(BS3REGCTX, r8),
    479     /* [BS3CG1DST_OZ_R9] = */   RT_OFFSETOF(BS3REGCTX, r9),
    480     /* [BS3CG1DST_OZ_R10] = */  RT_OFFSETOF(BS3REGCTX, r10),
    481     /* [BS3CG1DST_OZ_R11] = */  RT_OFFSETOF(BS3REGCTX, r11),
    482     /* [BS3CG1DST_OZ_R12] = */  RT_OFFSETOF(BS3REGCTX, r12),
    483     /* [BS3CG1DST_OZ_R13] = */  RT_OFFSETOF(BS3REGCTX, r13),
    484     /* [BS3CG1DST_OZ_R14] = */  RT_OFFSETOF(BS3REGCTX, r14),
    485     /* [BS3CG1DST_OZ_R15] = */  RT_OFFSETOF(BS3REGCTX, r15),
    486 
    487     /* [BS3CG1DST_VALUE_XCPT] = */ ~0U,
     454    /* [BS3CG1DST_INVALID] = */     ~0U,
     455    /* [BS3CG1DST_OP1] = */         ~0U,
     456    /* [BS3CG1DST_OP2] = */         ~0U,
     457    /* [BS3CG1DST_OP3] = */         ~0U,
     458    /* [BS3CG1DST_OP4] = */         ~0U,
     459    /* [BS3CG1DST_EFL] = */         RT_OFFSETOF(BS3REGCTX, rflags),
     460    /* [BS3CG1DST_EFL_UNDEF]=*/     ~0, /* special field */
     461
     462    /* [BS3CG1DST_AL] = */          RT_OFFSETOF(BS3REGCTX, rax.u8),
     463    /* [BS3CG1DST_CL] = */          RT_OFFSETOF(BS3REGCTX, rcx.u8),
     464    /* [BS3CG1DST_DL] = */          RT_OFFSETOF(BS3REGCTX, rdx.u8),
     465    /* [BS3CG1DST_BL] = */          RT_OFFSETOF(BS3REGCTX, rbx.u8),
     466    /* [BS3CG1DST_AH] = */          RT_OFFSETOF(BS3REGCTX, rax.b.bHi),
     467    /* [BS3CG1DST_CH] = */          RT_OFFSETOF(BS3REGCTX, rcx.b.bHi),
     468    /* [BS3CG1DST_DH] = */          RT_OFFSETOF(BS3REGCTX, rdx.b.bHi),
     469    /* [BS3CG1DST_BH] = */          RT_OFFSETOF(BS3REGCTX, rbx.b.bHi),
     470    /* [BS3CG1DST_SPL] = */         RT_OFFSETOF(BS3REGCTX, rsp.u8),
     471    /* [BS3CG1DST_BPL] = */         RT_OFFSETOF(BS3REGCTX, rbp.u8),
     472    /* [BS3CG1DST_SIL] = */         RT_OFFSETOF(BS3REGCTX, rsi.u8),
     473    /* [BS3CG1DST_DIL] = */         RT_OFFSETOF(BS3REGCTX, rdi.u8),
     474    /* [BS3CG1DST_R8L] = */         RT_OFFSETOF(BS3REGCTX, r8.u8),
     475    /* [BS3CG1DST_R9L] = */         RT_OFFSETOF(BS3REGCTX, r9.u8),
     476    /* [BS3CG1DST_R10L] = */        RT_OFFSETOF(BS3REGCTX, r10.u8),
     477    /* [BS3CG1DST_R11L] = */        RT_OFFSETOF(BS3REGCTX, r11.u8),
     478    /* [BS3CG1DST_R12L] = */        RT_OFFSETOF(BS3REGCTX, r12.u8),
     479    /* [BS3CG1DST_R13L] = */        RT_OFFSETOF(BS3REGCTX, r13.u8),
     480    /* [BS3CG1DST_R14L] = */        RT_OFFSETOF(BS3REGCTX, r14.u8),
     481    /* [BS3CG1DST_R15L] = */        RT_OFFSETOF(BS3REGCTX, r15.u8),
     482
     483    /* [BS3CG1DST_AX] = */          RT_OFFSETOF(BS3REGCTX, rax.u16),
     484    /* [BS3CG1DST_CX] = */          RT_OFFSETOF(BS3REGCTX, rcx.u16),
     485    /* [BS3CG1DST_DX] = */          RT_OFFSETOF(BS3REGCTX, rdx.u16),
     486    /* [BS3CG1DST_BX] = */          RT_OFFSETOF(BS3REGCTX, rbx.u16),
     487    /* [BS3CG1DST_SP] = */          RT_OFFSETOF(BS3REGCTX, rsp.u16),
     488    /* [BS3CG1DST_BP] = */          RT_OFFSETOF(BS3REGCTX, rbp.u16),
     489    /* [BS3CG1DST_SI] = */          RT_OFFSETOF(BS3REGCTX, rsi.u16),
     490    /* [BS3CG1DST_DI] = */          RT_OFFSETOF(BS3REGCTX, rdi.u16),
     491    /* [BS3CG1DST_R8W] = */         RT_OFFSETOF(BS3REGCTX, r8.u16),
     492    /* [BS3CG1DST_R9W] = */         RT_OFFSETOF(BS3REGCTX, r9.u16),
     493    /* [BS3CG1DST_R10W] = */        RT_OFFSETOF(BS3REGCTX, r10.u16),
     494    /* [BS3CG1DST_R11W] = */        RT_OFFSETOF(BS3REGCTX, r11.u16),
     495    /* [BS3CG1DST_R12W] = */        RT_OFFSETOF(BS3REGCTX, r12.u16),
     496    /* [BS3CG1DST_R13W] = */        RT_OFFSETOF(BS3REGCTX, r13.u16),
     497    /* [BS3CG1DST_R14W] = */        RT_OFFSETOF(BS3REGCTX, r14.u16),
     498    /* [BS3CG1DST_R15W] = */        RT_OFFSETOF(BS3REGCTX, r15.u16),
     499
     500    /* [BS3CG1DST_EAX] = */         RT_OFFSETOF(BS3REGCTX, rax.u32),
     501    /* [BS3CG1DST_ECX] = */         RT_OFFSETOF(BS3REGCTX, rcx.u32),
     502    /* [BS3CG1DST_EDX] = */         RT_OFFSETOF(BS3REGCTX, rdx.u32),
     503    /* [BS3CG1DST_EBX] = */         RT_OFFSETOF(BS3REGCTX, rbx.u32),
     504    /* [BS3CG1DST_ESP] = */         RT_OFFSETOF(BS3REGCTX, rsp.u32),
     505    /* [BS3CG1DST_EBP] = */         RT_OFFSETOF(BS3REGCTX, rbp.u32),
     506    /* [BS3CG1DST_ESI] = */         RT_OFFSETOF(BS3REGCTX, rsi.u32),
     507    /* [BS3CG1DST_EDI] = */         RT_OFFSETOF(BS3REGCTX, rdi.u32),
     508    /* [BS3CG1DST_R8D] = */         RT_OFFSETOF(BS3REGCTX, r8.u32),
     509    /* [BS3CG1DST_R9D] = */         RT_OFFSETOF(BS3REGCTX, r9.u32),
     510    /* [BS3CG1DST_R10D] = */        RT_OFFSETOF(BS3REGCTX, r10.u32),
     511    /* [BS3CG1DST_R11D] = */        RT_OFFSETOF(BS3REGCTX, r11.u32),
     512    /* [BS3CG1DST_R12D] = */        RT_OFFSETOF(BS3REGCTX, r12.u32),
     513    /* [BS3CG1DST_R13D] = */        RT_OFFSETOF(BS3REGCTX, r13.u32),
     514    /* [BS3CG1DST_R14D] = */        RT_OFFSETOF(BS3REGCTX, r14.u32),
     515    /* [BS3CG1DST_R15D] = */        RT_OFFSETOF(BS3REGCTX, r15.u32),
     516
     517    /* [BS3CG1DST_RAX] = */         RT_OFFSETOF(BS3REGCTX, rax.u64),
     518    /* [BS3CG1DST_RCX] = */         RT_OFFSETOF(BS3REGCTX, rcx.u64),
     519    /* [BS3CG1DST_RDX] = */         RT_OFFSETOF(BS3REGCTX, rdx.u64),
     520    /* [BS3CG1DST_RBX] = */         RT_OFFSETOF(BS3REGCTX, rbx.u64),
     521    /* [BS3CG1DST_RSP] = */         RT_OFFSETOF(BS3REGCTX, rsp.u64),
     522    /* [BS3CG1DST_RBP] = */         RT_OFFSETOF(BS3REGCTX, rbp.u64),
     523    /* [BS3CG1DST_RSI] = */         RT_OFFSETOF(BS3REGCTX, rsi.u64),
     524    /* [BS3CG1DST_RDI] = */         RT_OFFSETOF(BS3REGCTX, rdi.u64),
     525    /* [BS3CG1DST_R8] = */          RT_OFFSETOF(BS3REGCTX, r8.u64),
     526    /* [BS3CG1DST_R9] = */          RT_OFFSETOF(BS3REGCTX, r9.u64),
     527    /* [BS3CG1DST_R10] = */         RT_OFFSETOF(BS3REGCTX, r10.u64),
     528    /* [BS3CG1DST_R11] = */         RT_OFFSETOF(BS3REGCTX, r11.u64),
     529    /* [BS3CG1DST_R12] = */         RT_OFFSETOF(BS3REGCTX, r12.u64),
     530    /* [BS3CG1DST_R13] = */         RT_OFFSETOF(BS3REGCTX, r13.u64),
     531    /* [BS3CG1DST_R14] = */         RT_OFFSETOF(BS3REGCTX, r14.u64),
     532    /* [BS3CG1DST_R15] = */         RT_OFFSETOF(BS3REGCTX, r15.u64),
     533
     534    /* [BS3CG1DST_OZ_RAX] = */      RT_OFFSETOF(BS3REGCTX, rax),
     535    /* [BS3CG1DST_OZ_RCX] = */      RT_OFFSETOF(BS3REGCTX, rcx),
     536    /* [BS3CG1DST_OZ_RDX] = */      RT_OFFSETOF(BS3REGCTX, rdx),
     537    /* [BS3CG1DST_OZ_RBX] = */      RT_OFFSETOF(BS3REGCTX, rbx),
     538    /* [BS3CG1DST_OZ_RSP] = */      RT_OFFSETOF(BS3REGCTX, rsp),
     539    /* [BS3CG1DST_OZ_RBP] = */      RT_OFFSETOF(BS3REGCTX, rbp),
     540    /* [BS3CG1DST_OZ_RSI] = */      RT_OFFSETOF(BS3REGCTX, rsi),
     541    /* [BS3CG1DST_OZ_RDI] = */      RT_OFFSETOF(BS3REGCTX, rdi),
     542    /* [BS3CG1DST_OZ_R8] = */       RT_OFFSETOF(BS3REGCTX, r8),
     543    /* [BS3CG1DST_OZ_R9] = */       RT_OFFSETOF(BS3REGCTX, r9),
     544    /* [BS3CG1DST_OZ_R10] = */      RT_OFFSETOF(BS3REGCTX, r10),
     545    /* [BS3CG1DST_OZ_R11] = */      RT_OFFSETOF(BS3REGCTX, r11),
     546    /* [BS3CG1DST_OZ_R12] = */      RT_OFFSETOF(BS3REGCTX, r12),
     547    /* [BS3CG1DST_OZ_R13] = */      RT_OFFSETOF(BS3REGCTX, r13),
     548    /* [BS3CG1DST_OZ_R14] = */      RT_OFFSETOF(BS3REGCTX, r14),
     549    /* [BS3CG1DST_OZ_R15] = */      RT_OFFSETOF(BS3REGCTX, r15),
     550
     551    /* [BS3CG1DST_FCW] = */         sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FCW),
     552    /* [BS3CG1DST_FSW] = */         sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FSW),
     553    /* [BS3CG1DST_FTW] = */         sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FTW),
     554    /* [BS3CG1DST_FOP] = */         sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FOP),
     555    /* [BS3CG1DST_FPUIP] = */       sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FPUIP),
     556    /* [BS3CG1DST_FPUCS] = */       sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.CS),
     557    /* [BS3CG1DST_FPUDP] = */       sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FPUDP),
     558    /* [BS3CG1DST_FPUDS] = */       sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.DS),
     559    /* [BS3CG1DST_MXCSR] = */       sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.MXCSR),
     560    /* [BS3CG1DST_MXCSR_MASK] = */  sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.MXCSR_MASK),
     561    /* [BS3CG1DST_ST0] = */         sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[0]),
     562    /* [BS3CG1DST_ST1] = */         sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[1]),
     563    /* [BS3CG1DST_ST2] = */         sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[2]),
     564    /* [BS3CG1DST_ST3] = */         sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[3]),
     565    /* [BS3CG1DST_ST4] = */         sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[4]),
     566    /* [BS3CG1DST_ST5] = */         sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[5]),
     567    /* [BS3CG1DST_ST6] = */         sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[6]),
     568    /* [BS3CG1DST_ST7] = */         sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[7]),
     569    /* [BS3CG1DST_MM0] = */         sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[0]),
     570    /* [BS3CG1DST_MM1] = */         sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[1]),
     571    /* [BS3CG1DST_MM2] = */         sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[2]),
     572    /* [BS3CG1DST_MM3] = */         sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[3]),
     573    /* [BS3CG1DST_MM4] = */         sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[4]),
     574    /* [BS3CG1DST_MM5] = */         sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[5]),
     575    /* [BS3CG1DST_MM6] = */         sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[6]),
     576    /* [BS3CG1DST_MM7] = */         sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[7]),
     577    /* [BS3CG1DST_XMM0] = */        sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0]),
     578    /* [BS3CG1DST_XMM1] = */        sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1]),
     579    /* [BS3CG1DST_XMM2] = */        sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2]),
     580    /* [BS3CG1DST_XMM3] = */        sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3]),
     581    /* [BS3CG1DST_XMM4] = */        sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4]),
     582    /* [BS3CG1DST_XMM5] = */        sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5]),
     583    /* [BS3CG1DST_XMM6] = */        sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6]),
     584    /* [BS3CG1DST_XMM7] = */        sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7]),
     585    /* [BS3CG1DST_XMM8] = */        sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8]),
     586    /* [BS3CG1DST_XMM9] = */        sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9]),
     587    /* [BS3CG1DST_XMM10] = */       sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10]),
     588    /* [BS3CG1DST_XMM11] = */       sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11]),
     589    /* [BS3CG1DST_XMM12] = */       sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12]),
     590    /* [BS3CG1DST_XMM13] = */       sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13]),
     591    /* [BS3CG1DST_XMM14] = */       sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]),
     592    /* [BS3CG1DST_XMM15] = */       sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]),
     593    /* [BS3CG1DST_YMM0] = */        ~0U,
     594    /* [BS3CG1DST_YMM1] = */        ~0U,
     595    /* [BS3CG1DST_YMM2] = */        ~0U,
     596    /* [BS3CG1DST_YMM3] = */        ~0U,
     597    /* [BS3CG1DST_YMM4] = */        ~0U,
     598    /* [BS3CG1DST_YMM5] = */        ~0U,
     599    /* [BS3CG1DST_YMM6] = */        ~0U,
     600    /* [BS3CG1DST_YMM7] = */        ~0U,
     601    /* [BS3CG1DST_YMM8] = */        ~0U,
     602    /* [BS3CG1DST_YMM9] = */        ~0U,
     603    /* [BS3CG1DST_YMM10] = */       ~0U,
     604    /* [BS3CG1DST_YMM11] = */       ~0U,
     605    /* [BS3CG1DST_YMM12] = */       ~0U,
     606    /* [BS3CG1DST_YMM13] = */       ~0U,
     607    /* [BS3CG1DST_YMM14] = */       ~0U,
     608    /* [BS3CG1DST_YMM15] = */       ~0U,
     609
     610    /* [BS3CG1DST_VALUE_XCPT] = */  ~0U,
    488611};
     612AssertCompile(RT_ELEMENTS(g_aoffBs3Cg1DstFields) == BS3CG1DST_END);
    489613
    490614#ifdef BS3CG1_DEBUG_CTX_MOD
    … …  
    589713    { "OZ_R15" },
    590714
     715    { "FCW" },
     716    { "FSW" },
     717    { "FTW" },
     718    { "FOP" },
     719    { "FPUIP" },
     720    { "FPUCS" },
     721    { "FPUDP" },
     722    { "FPUDS" },
     723    { "MXCSR" },
     724    { "MXCSR_M" },
     725    { "ST0" },
     726    { "ST1" },
     727    { "ST2" },
     728    { "ST3" },
     729    { "ST4" },
     730    { "ST5" },
     731    { "ST6" },
     732    { "ST7" },
     733    { "MM0" },
     734    { "MM1" },
     735    { "MM2" },
     736    { "MM3" },
     737    { "MM4" },
     738    { "MM5" },
     739    { "MM6" },
     740    { "MM7" },
     741    { "XMM0" },
     742    { "XMM1" },
     743    { "XMM2" },
     744    { "XMM3" },
     745    { "XMM4" },
     746    { "XMM5" },
     747    { "XMM6" },
     748    { "XMM7" },
     749    { "XMM8" },
     750    { "XMM9" },
     751    { "XMM10" },
     752    { "XMM11" },
     753    { "XMM12" },
     754    { "XMM13" },
     755    { "XMM14" },
     756    { "XMM15" },
     757    { "YMM0" },
     758    { "YMM1" },
     759    { "YMM2" },
     760    { "YMM3" },
     761    { "YMM4" },
     762    { "YMM5" },
     763    { "YMM6" },
     764    { "YMM7" },
     765    { "YMM8" },
     766    { "YMM9" },
     767    { "YMM10" },
     768    { "YMM11" },
     769    { "YMM12" },
     770    { "YMM13" },
     771    { "YMM14" },
     772    { "YMM15" },
     773
    591774    { "VALXCPT" },
    592775};
     776AssertCompile(RT_ELEMENTS(g_aszBs3Cg1DstFields) == BS3CG1DST_END);
    593777
    594778#endif
    … …  
    8701054            break;
    8711055
     1056        case BS3CG1ENC_MODRM_Wsd_Vsd:
     1057            if (iEncoding == 0)
     1058            {
     1059                off = Bs3Cg1InsertOpcodes(pThis, 0);
     1060                pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 1, 0);
     1061                pThis->aOperands[pThis->iRmOp ].idxField    = BS3CG1DST_XMM0;
     1062                pThis->aOperands[pThis->iRegOp].idxField    = BS3CG1DST_XMM1;
     1063            }
     1064            else
     1065                break;
     1066            pThis->cbCurInstr = off;
     1067            iEncoding++;
     1068            break;
     1069
     1070
    8721071        case BS3CG1ENC_MODRM_Gv_Ma:
    8731072            cbOp = BS3_MODE_IS_16BIT_CODE(pThis->bMode) ? 2 : 4;
    … …  
    10631262            pThis->aOperands[1].enmLocation = BS3CG1OPLOC_MEM;
    10641263            pThis->aOperands[1].idxField    = BS3CG1DST_INVALID;
     1264            break;
     1265
     1266        case BS3CG1ENC_MODRM_Wsd_Vsd:
     1267            pThis->iRmOp  = 0;
     1268            pThis->iRegOp = 1;
     1269            pThis->aOperands[0].cbOp = 16;
     1270            pThis->aOperands[1].cbOp = 16;
     1271            pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
     1272            pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
    10651273            break;
    10661274
    … …  
    13011509        unsigned        cbDst;
    13021510        BS3CG1DST       idxField;
     1511        BS3PTRUNION     PtrField;
    13031512
    13041513        /* Expand the destiation field (can be escaped). */
    … …  
    13841593        {
    13851594            unsigned const offField = g_aoffBs3Cg1DstFields[idxField];
    1386             BS3PTRUNION    PtrField;
    13871595
    13881596            /*
    … …  
    14711679                PtrField.pu8 = &pThis->bValueXcpt;
    14721680            }
    1473             /// @todo else if (idxField <= BS3CG1DST_OP4)
    1474             /// @todo {
    1475             /// @todo
    1476             /// @todo }
     1681            /* FPU and FXSAVE format. */
     1682            else if (   pThis->pExtCtx->enmMethod != BS3EXTCTXMETHOD_ANCIENT
     1683                     && offField - sizeof(BS3REGCTX) <= RT_UOFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]) )
     1684                PtrField.pb = (uint8_t *)pThis->pExtCtx + offField - sizeof(BS3REGCTX);
     1685            /** @todo other FPU fields and FPU state formats. */
    14771686            else
    14781687                return Bs3TestFailedF("Todo implement me: cbDst=%u idxField=%d offField=%#x", cbDst, idxField, offField);
    … …  
    15741783         */
    15751784        else
    1576             return Bs3TestFailedF("TODO: Implement me: cbDst=%u idxField=%d", cbDst, idxField);
     1785        {
     1786            union
     1787            {
     1788                X86FPUREG   FpuReg;
     1789                X86XMMREG   XmmReg;
     1790                X86YMMREG   YmmReg;
     1791                X86ZMMREG   ZmmReg;
     1792                uint8_t     ab[sizeof(X86ZMMREG)];
     1793                uint32_t    au32[sizeof(X86ZMMREG) / sizeof(uint32_t)];
     1794            } Value;
     1795            unsigned const offField = g_aoffBs3Cg1DstFields[idxField];
     1796
     1797            /* Copy the value into the union, doing the zero padding / extending. */
     1798            Bs3MemCpy(&Value, pbCode, cbValue);
     1799            if (cbValue < sizeof(Value))
     1800            {
     1801                if ((bOpcode & BS3CG1_CTXOP_SIGN_EXT) && (Value.ab[cbValue - 1] & 0x80))
     1802                    Bs3MemSet(&Value.ab[cbValue], 0xff, sizeof(Value) - cbValue);
     1803                else
     1804                    Bs3MemSet(&Value.ab[cbValue], 0x00, sizeof(Value) - cbValue);
     1805            }
     1806
     1807            /* Optimized access to XMM and STx registers. */
     1808            if (   pThis->pExtCtx->enmMethod != BS3EXTCTXMETHOD_ANCIENT
     1809                && offField - sizeof(BS3REGCTX) <= RT_UOFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]) )
     1810            {
     1811                /* Modify the field. */
     1812                unsigned i;
     1813                if (cbDst & 3)
     1814                    return Bs3TestFailedF("Malformed context instruction: cbDst=%u, multiple of 4", cbDst);
     1815
     1816                PtrField.pb = (uint8_t *)pThis->pExtCtx + offField - sizeof(BS3REGCTX);
     1817                i = cbDst / 4;
     1818                while (i-- > 0)
     1819                {
     1820                    switch (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK)
     1821                    {
     1822                        case BS3CG1_CTXOP_ASSIGN:   PtrField.pu32[i]  =  Value.au32[i]; break;
     1823                        case BS3CG1_CTXOP_OR:       PtrField.pu32[i] |=  Value.au32[i]; break;
     1824                        case BS3CG1_CTXOP_AND:      PtrField.pu32[i] &=  Value.au32[i]; break;
     1825                        case BS3CG1_CTXOP_AND_INV:  PtrField.pu32[i] &= ~Value.au32[i]; break;
     1826                    }
     1827                }
     1828            }
     1829            /* The YMM (AVX) and the first 16 ZMM (AVX512) registers have split storage in
     1830               the state, so they need special handling.  */
     1831            else
     1832                return Bs3TestFailedF("TODO: implement me: cbDst=%d idxField=%d (AVX and other weird state)", cbDst, idxField);
     1833
     1834        }
    15771835
    15781836        /*
    … …  
    18112069        Bs3MemFree(pThis->pbDataPg, X86_PAGE_SIZE);
    18122070    }
     2071    Bs3ExtCtxFree(pThis->pExtCtx);
     2072    Bs3ExtCtxFree(pThis->pInitialExtCtx);
    18132073}
    18142074
    … …  
    18392099    pThis->fAdvanceMnemonic   = 1;
    18402100
     2101    /* Allocate extended context structures. */
     2102    pThis->pExtCtx            = Bs3ExtCtxAlloc(0, BS3MEMKIND_TILED);
     2103    pThis->pInitialExtCtx     = Bs3ExtCtxAlloc(0, BS3MEMKIND_TILED);
     2104    if (!pThis->pExtCtx || !pThis->pInitialExtCtx)
     2105        return Bs3TestFailed("Bs3ExtCtxAlloc failed");
     2106
    18412107    /* Allocate guarded exectuable and data memory. */
    18422108    if (BS3_MODE_IS_PAGED(bMode))
    … …  
    18482114        pThis->pbDataPg = Bs3MemGuardedTestPageAlloc(enmMemKind);
    18492115        if (!pThis->pbDataPg)
    1850         {
    1851             Bs3MemGuardedTestPageFree(pThis->pbCodePg);
    18522116            return Bs3TestFailedF("Second Bs3MemGuardedTestPageAlloc(%d) failed", enmMemKind);
    1853         }
    18542117        if (   BS3_MODE_IS_64BIT_CODE(bMode)
    18552118            && (uintptr_t)pThis->pbDataPg >= _2G)
    1856         {
    1857             Bs3TestFailedF("pbDataPg=%p is above 2GB and not simple to address from 64-bit code", pThis->pbDataPg);
    1858             Bs3MemGuardedTestPageFree(pThis->pbDataPg);
    1859             Bs3MemGuardedTestPageFree(pThis->pbCodePg);
    1860             return 0;
    1861         }
     2119            return Bs3TestFailedF("pbDataPg=%p is above 2GB and not simple to address from 64-bit code", pThis->pbDataPg);
    18622120#else
    18632121        return Bs3TestFailed("WTF?! #1");
    … …  
    18712129        pThis->pbDataPg = Bs3MemAlloc(enmMemKind, X86_PAGE_SIZE);
    18722130        if (!pThis->pbDataPg)
    1873         {
    1874             Bs3MemFree(pThis->pbCodePg, X86_PAGE_SIZE);
    18752131            return Bs3TestFailedF("Second Bs3MemAlloc(%d,Pg) failed", enmMemKind);
    1876         }
    18772132    }
    18782133    pThis->uCodePgFlat = Bs3SelPtrToFlat(pThis->pbCodePg);
    … …  
    19192174#endif
    19202175
    1921     /* Create basic context for each target ring.  In protected 16-bit code we need
    1922        set up code selectors that can access pbCodePg.  ASSUMES 16-bit driver code! */
     2176    /*
     2177     * Create basic context for each target ring.
     2178     *
     2179     * In protected 16-bit code we need set up code selectors that can access
     2180     * pbCodePg.
     2181     *
     2182     * In long mode we make sure the high 32-bits of GPRs (sans RSP) have some
     2183     * bits set so we can check that the implicit clearing is tested.
     2184     */
    19232185    Bs3RegCtxSaveEx(&pThis->aInitialCtxs[pThis->iFirstRing], bMode, 1024 * 3);
    19242186#if ARCH_BITS == 64
    … …  
    19392201    pThis->aInitialCtxs[pThis->iFirstRing].r15.u |= UINT64_C(0x1515151500000000);
    19402202#endif
     2203
    19412204    if (BS3_MODE_IS_RM_OR_V86(bMode))
    19422205    {
    … …  
    21582421    {
    21592422        bRet = BS3_CMN_NM(Bs3Cg1WorkerInner)(&This);
    2160 
    2161         Bs3Cg1Destroy(&This);
    21622423        Bs3TestSubDone();
    21632424    }
     2425    Bs3Cg1Destroy(&This);
    21642426#else
    21652427    PBS3CG1STATE pThis = (PBS3CG1STATE)Bs3MemAlloc(BS3MEMKIND_REAL, sizeof(*pThis));
    21662428    if (pThis)
    21672429    {
    2168 
    21692430        if (BS3_CMN_NM(Bs3Cg1Init)(pThis, bMode))
    21702431        {
    21712432            bRet = BS3_CMN_NM(Bs3Cg1WorkerInner)(pThis);
    2172 
    2173             Bs3Cg1Destroy(pThis);
    21742433            Bs3TestSubDone();
    21752434        }
     2435        Bs3Cg1Destroy(pThis);
    21762436        Bs3MemFree(pThis, sizeof(*pThis));
    21772437    }

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h

    r66172 r66216  
    327327    BS3CG1DST_OZ_R15,
    328328
     329    /* FPU registers. */
     330    BS3CG1DST_FPU_FIRST,
     331    BS3CG1DST_FCW = BS3CG1DST_FPU_FIRST,
     332    BS3CG1DST_FSW,
     333    BS3CG1DST_FTW,
     334    BS3CG1DST_FOP,
     335    BS3CG1DST_FPUIP,
     336    BS3CG1DST_FPUCS,
     337    BS3CG1DST_FPUDP,
     338    BS3CG1DST_FPUDS,
     339    BS3CG1DST_MXCSR,
     340    BS3CG1DST_MXCSR_MASK,
     341    BS3CG1DST_ST0,
     342    BS3CG1DST_ST1,
     343    BS3CG1DST_ST2,
     344    BS3CG1DST_ST3,
     345    BS3CG1DST_ST4,
     346    BS3CG1DST_ST5,
     347    BS3CG1DST_ST6,
     348    BS3CG1DST_ST7,
     349    /* MMX registers. */
     350    BS3CG1DST_MM0,
     351    BS3CG1DST_MM1,
     352    BS3CG1DST_MM2,
     353    BS3CG1DST_MM3,
     354    BS3CG1DST_MM4,
     355    BS3CG1DST_MM5,
     356    BS3CG1DST_MM6,
     357    BS3CG1DST_MM7,
     358    /* SSE registers. */
     359    BS3CG1DST_XMM0,
     360    BS3CG1DST_XMM1,
     361    BS3CG1DST_XMM2,
     362    BS3CG1DST_XMM3,
     363    BS3CG1DST_XMM4,
     364    BS3CG1DST_XMM5,
     365    BS3CG1DST_XMM6,
     366    BS3CG1DST_XMM7,
     367    BS3CG1DST_XMM8,
     368    BS3CG1DST_XMM9,
     369    BS3CG1DST_XMM10,
     370    BS3CG1DST_XMM11,
     371    BS3CG1DST_XMM12,
     372    BS3CG1DST_XMM13,
     373    BS3CG1DST_XMM14,
     374    BS3CG1DST_XMM15,
     375    /* AVX registers. */
     376    BS3CG1DST_YMM0,
     377    BS3CG1DST_YMM1,
     378    BS3CG1DST_YMM2,
     379    BS3CG1DST_YMM3,
     380    BS3CG1DST_YMM4,
     381    BS3CG1DST_YMM5,
     382    BS3CG1DST_YMM6,
     383    BS3CG1DST_YMM7,
     384    BS3CG1DST_YMM8,
     385    BS3CG1DST_YMM9,
     386    BS3CG1DST_YMM10,
     387    BS3CG1DST_YMM11,
     388    BS3CG1DST_YMM12,
     389    BS3CG1DST_YMM13,
     390    BS3CG1DST_YMM14,
     391    BS3CG1DST_YMM15,
     392
    329393    /* Special fields: */
    330394    BS3CG1DST_SPECIAL_START,

  • trunk/src/VBox/ValidationKit/bootsectors/bs3kit/bs3kit.h

    r66214 r66216  
    26942694        /** xsave/xrstor   */
    26952695        X86XSAVEAREA    x;
     2696        /** Byte array view. */
     2697        uint8_t         ab[sizeof(X86XSAVEAREA)];
    26962698    } Ctx;
    26972699} BS3EXTCTX;
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