Changeset 66254 in vbox

Timestamp:

Mar 27, 2017 3:18:10 AM (8 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

114175

Message:

VMM: Nested Hw.virt: SVM: Update EFER and EFER.LMA on VMRUN.

File:

• trunk/src/VBox/VMM/VMMAll/HMSVMAll.cpp (modified) (6 diffs)

trunk/src/VBox/VMM/VMMAll/HMSVMAll.cpp

@@ -315 +315 @@
             }
 
+            /** @todo gPAT MSR validation? */
+
             /*
              * Copy segments from nested-guest VMCB state to the guest-CPU state.
@@ -352 +354 @@
                 return HMSvmNstGstVmExit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
             }
-            Assert(   !(uValidEfer & MSR_K6_EFER_LME)
-                   ||  VmcbNstGst.u64CR0 & X86_CR0_PG);
             bool const fSvm                     = RT_BOOL(uValidEfer & MSR_K6_EFER_SVME);
             bool const fLongModeSupported       = RT_BOOL(pVM->cpum.ro.GuestFeatures.fLongMode);
-            bool const fLongModeActiveOrEnabled = RT_BOOL(uValidEfer & (MSR_K6_EFER_LME | MSR_K6_EFER_LMA));
             bool const fLongModeEnabled         = RT_BOOL(uValidEfer & MSR_K6_EFER_LME);
             bool const fPaging                  = RT_BOOL(VmcbNstGst.u64CR0 & X86_CR0_PG);
@@ -363 +362 @@
             bool const fLongModeWithPaging      = fLongModeEnabled && fPaging;
             bool const fLongModeConformCS       = pCtx->cs.Attr.n.u1Long && pCtx->cs.Attr.n.u1DefBig;
+            /* Adjust EFER.LMA (this is normally done by the CPU when system software writes CR0). */
+            if (fLongModeWithPaging)
+                uValidEfer |= MSR_K6_EFER_LMA;
+            bool const fLongModeActiveOrEnabled = RT_BOOL(uValidEfer & (MSR_K6_EFER_LME | MSR_K6_EFER_LMA));
             if (   !fSvm
                 || (!fLongModeSupported && fLongModeActiveOrEnabled)
@@ -382 +385 @@
              * nested-guest (or the guest).
              *
-             *   - VMCPU_FF_INHIBIT_INTERRUPTS needn't be preserved as it's for a single
+             *   - VMCPU_FF_INHIBIT_INTERRUPTS need not be preserved as it's for a single
              *     instruction which is this VMRUN instruction itself.
              *
@@ -419 +422 @@
             pCtx->idtr.cbIdt = VmcbNstGst.IDTR.u32Limit;
             pCtx->idtr.pIdt  = VmcbNstGst.IDTR.u64Base;
-            pCtx->cr0        = VmcbNstGst.u64CR0;
+            pCtx->cr0        = VmcbNstGst.u64CR0;   /** @todo What about informing PGM about CR0.WP? */
             pCtx->cr4        = VmcbNstGst.u64CR4;
             pCtx->cr3        = VmcbNstGst.u64CR3;
@@ -429 +432 @@
             pCtx->rsp        = VmcbNstGst.u64RSP;
             pCtx->rip        = VmcbNstGst.u64RIP;
+            pCtx->msrEFER    = uValidEfer;
 
             /* Mask DR6, DR7 bits mandatory set/clear bits. */