Changeset 66342 in vbox for trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-decoding-1.c32

Timestamp:

Mar 29, 2017 4:22:31 PM (8 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

114278

Message:

IEM: Converted grp 9 to tables and fixed cmpxchg16b/8b prefix handling.

File:

• trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-decoding-1.c32 (modified) (7 diffs)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-decoding-1.c32

@@ -406 +406 @@
 CPUDECODE1UDTST const g_aUdTest2Byte_0f[] =
 {
-#if 1
+#if 0
     {  UD_T_EXACT, 2, { 0x0f, 0x04 }, UD_F_ANY_PFX },
     {  UD_T_EXACT, 2, { 0x0f, 0x0a }, UD_F_ANY_PFX },
@@ -536 +536 @@
     {  UD_T_MODRM_MR0, 2, { 0x0f, 0xc7 }, UD_F_ANY_PFX },
     {  UD_T_MODRM_RR0, 2, { 0x0f, 0xc7 }, UD_F_ANY_PFX },
-    //{  UD_T_MODRM_MR1, 2, { 0x0f, 0xc7 }, xxxx }, - cmpxchg8b/16b is weird, needs special testcase.
+    //{  UD_T_MODRM_MR1, 2, { 0x0f, 0xc7 }, UD_F_NOT_NO_PFX | UD_F_NOT_OZ_PFX | UD_F_NOT_RN_PFX | UD_F_NOT_RZ_PFX | UD_F_NOT_LK_PFX }, - cmpxchg8b ignores everything. @
     {  UD_T_MODRM_RR1, 2, { 0x0f, 0xc7 }, UD_F_ANY_PFX },
     {  UD_T_MODRM_MR2, 2, { 0x0f, 0xc7 }, UD_F_ANY_PFX },
@@ -546 +546 @@
     {  UD_T_MODRM_MR5, 2, { 0x0f, 0xc7 }, UD_F_ANY_PFX },
     {  UD_T_MODRM_RR5, 2, { 0x0f, 0xc7 }, UD_F_ANY_PFX },
-    //{  UD_T_MODRM_MR0, 2, { 0x0f, 0xc7 }, UD_F_NOT_OZ_PFX | UD_F_NOT_RN_PFX |  },
-    {  UD_T_MODRM_RR0, 2, { 0x0f, 0xc7 }, UD_F_ANY_PFX },
-#if 1
+    {  UD_T_MODRM_MR6, 2, { 0x0f, 0xc7 }, UD_F_NOT_NO_PFX | UD_F_NOT_OZ_PFX | UD_F_NOT_RZ_PFX }, /* f2? */
+    {  UD_T_MODRM_RR6, 2, { 0x0f, 0xc7 }, UD_F_NOT_NO_PFX | UD_F_NOT_OZ_PFX }, /* (rdrand Rv) */
+    {  UD_T_MODRM_MR7, 2, { 0x0f, 0xc7 }, UD_F_NOT_NO_PFX }, /* vmptrst Mq (f2?); */
+    {  UD_T_MODRM_RR7, 2, { 0x0f, 0xc7 }, UD_F_NOT_NO_PFX | UD_F_NOT_OZ_PFX | UD_F_NOT_RZ_PFX }, /* rdrand Rv; rdpid Rd/q (f2,66??); */
+#if 0
     {  UD_T_MODRM, 2, { 0x0f, 0xd0 }, UD_F_NOT_OZ_PFX | UD_F_NOT_RN_PFX },
     {  UD_T_MODRM, 2, { 0x0f, 0xd1 }, UD_F_NOT_NO_PFX | UD_F_NOT_OZ_PFX },
@@ -1290 +1292 @@
 
 
+#if 0
+/**
+ * Checks how prefixes affects cmpxchg8b and cmpxchg16b
+ *
+ * The thing here is that the intel opcode tables indicates that the 66 and f3
+ * prefixes encodings are reserved and causes \#UD, where AMD doesn't.  Seems
+ * though that the f2, f3 and 66 prefixes are ignored on skylake intel.  Need to
+ * make sure this is the case, also in 64-bit mode and for the 16b version.
+ */
+static void DecodeCmpXchg8bVs16b(void)
+{
+    uint8_t BS3_FAR *pbPages;
+
+    /* Check that the instructions are supported. */
+    if (   !(g_uBs3CpuDetected & BS3CPU_F_CPUID)
+        || !(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_CX8))
+    {
+        Bs3TestSkipped("not supported");
+        return;
+    }
+
+    /* Setup a guarded page. */
+    pbPages = Bs3MemGuardedTestPageAlloc(BS3MEMKIND_FLAT32);
+    if (pbPages)
+    {
+
+        Bs3MemGuardedTestPageFree(pbPages);
+    }
+    else
+        Bs3TestFailed("Failed to allocate two pages!\n");
+}
+#endif
+
+
 /**
  * Checks various prefix encodings with the MOVBE and CRC32 instructions to try
@@ -1661 +1697 @@
     Bs3TestPrintf("g_uBs3CpuDetected=%#x\n", g_uBs3CpuDetected);
 
-#if 1
+#if 0
     Bs3TestSub("CMPPS, CMPPD, CMPSS, CMPSD");
     DecodeCmppsCmppdCmpssCmpsd();
@@ -1668 +1704 @@
     DecodeMovbeVsCrc32();
 #endif
+
+    //Bs3TestSub("CMPXCHG8B/16B");
+    //DecodeCmpXchg8bVs16b();
 
 #if 1
@@ -1673 +1712 @@
     DecodeUdEdgeTest(g_aUdTest2Byte_0f, RT_ELEMENTS(g_aUdTest2Byte_0f));
 #endif
-#if 1
+#if 0
     Bs3TestSub("3 byte undefined opcodes 0f 38");
     DecodeUdEdgeTest(g_aUdTest3Byte_0f_38, RT_ELEMENTS(g_aUdTest3Byte_0f_38));