Changeset 66371 in vbox

Timestamp:

Mar 30, 2017 5:49:00 PM (8 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

114316

Message:

VMM: Nested Hw.virt: MSR and IO intercept helpers for SVM.

Location:

trunk

Files:

• include/VBox/vmm/hm.h (modified) (1 diff)
• include/VBox/vmm/hm_svm.h (modified) (3 diffs)
• src/VBox/VMM/VMMAll/HMSVMAll.cpp (modified) (4 diffs)
• src/VBox/VMM/VMMR0/HMSVMR0.cpp (modified) (1 diff)

trunk/include/VBox/vmm/hm.h

@@ -159 +159 @@
 VMM_INT_DECL(int)               HMSvmNstGstGetInterrupt(PCCPUMCTX pCtx, uint8_t *pu8Interrupt);
 VMM_INT_DECL(bool)              HMSvmNstGstIsInterruptPending(PCCPUMCTX pCtx);
-VMM_INT_DECL(VBOXSTRICTRC)      HMSvmNstGstHandleCtrlIntercept(PVMCPU pVCpu, PCPUMCTX pCtx, uint64_t uExitCode,
-                                                               uint64_t uExitInfo1,uint64_t uExitInfo2);
+VMM_INT_DECL(VBOXSTRICTRC)      HMSvmNstGstHandleCtrlIntercept(PVMCPU pVCpu, PCPUMCTX pCtx, uint64_t uExitCode, uint64_t uExitInfo1,
+                                                               uint64_t uExitInfo2);
 VMM_INT_DECL(VBOXSTRICTRC)      HMSvmNstGstHandleMsrIntercept(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t idMsr, bool fWrite);
+VMM_INT_DECL(VBOXSTRICTRC)      HMSvmNstGstHandleIOIntercept(PVMCPU pVCpu, PCPUMCTX pCtx, PCSVMIOIOEXITINFO pIoExitInfo,
+                                                             uint64_t uNextRip);
 /** @} */
 

trunk/include/VBox/vmm/hm_svm.h

@@ -93 +93 @@
  */
 #ifndef IN_REM_R3
-/** @name SVM Basic Exit Reasons.
+/** @name SVM_EXIT_XXX - SVM Basic Exit Reasons.
  * @{
  */
@@ -588 +588 @@
 
 /**
- * SVM IOIO exit structure (EXITINFO1 for IOIO intercepts).
+ * SVM IOIO exit info. structure (EXITINFO1 for IOIO intercepts).
  */
 typedef union
@@ -594 +594 @@
     struct
     {
-        uint32_t    u1Type              : 1;        /**< Bit 0: 0 = out, 1 = in */
-        uint32_t    u1Reserved          : 1;        /**< Bit 1: Reserved */
-        uint32_t    u1STR               : 1;        /**< Bit 2: String I/O (1) or not (0). */
-        uint32_t    u1REP               : 1;        /**< Bit 3: Repeat prefixed string I/O. */
-        uint32_t    u1OP8               : 1;        /**< Bit 4: 8-bit operand. */
-        uint32_t    u1OP16              : 1;        /**< Bit 5: 16-bit operand. */
-        uint32_t    u1OP32              : 1;        /**< Bit 6: 32-bit operand. */
-        uint32_t    u1ADDR16            : 1;        /**< Bit 7: 16-bit operand. */
-        uint32_t    u1ADDR32            : 1;        /**< Bit 8: 32-bit operand. */
-        uint32_t    u1ADDR64            : 1;        /**< Bit 9: 64-bit operand. */
-        uint32_t    u3SEG               : 3;        /**< BITS 12:10: Effective segment number. Added with decode assist in APM v3.17. */
+        uint32_t    u1Type              : 1;   /**< Bit 0: 0 = out, 1 = in */
+        uint32_t    u1Reserved          : 1;   /**< Bit 1: Reserved */
+        uint32_t    u1STR               : 1;   /**< Bit 2: String I/O (1) or not (0). */
+        uint32_t    u1REP               : 1;   /**< Bit 3: Repeat prefixed string I/O. */
+        uint32_t    u1OP8               : 1;   /**< Bit 4: 8-bit operand. */
+        uint32_t    u1OP16              : 1;   /**< Bit 5: 16-bit operand. */
+        uint32_t    u1OP32              : 1;   /**< Bit 6: 32-bit operand. */
+        uint32_t    u1ADDR16            : 1;   /**< Bit 7: 16-bit operand. */
+        uint32_t    u1ADDR32            : 1;   /**< Bit 8: 32-bit operand. */
+        uint32_t    u1ADDR64            : 1;   /**< Bit 9: 64-bit operand. */
+        uint32_t    u3SEG               : 3;   /**< BITS 12:10: Effective segment number. Added w/ decode assist in APM v3.17. */
         uint32_t    u3Reserved          : 3;
-        uint32_t    u16Port             : 16;       /**< Bits 31:16: Port number. */
+        uint32_t    u16Port             : 16;  /**< Bits 31:16: Port number. */
     } n;
     uint32_t    u;
-} SVMIOIOEXIT;
+} SVMIOIOEXITINFO;
+/** Pointer to an SVM IOIO exit info. structure. */
+typedef SVMIOIOEXITINFO *PSVMIOIOEXITINFO;
+/** Pointer to a const SVM IOIO exit info. structure. */
+typedef const SVMIOIOEXITINFO *PCSVMIOIOEXITINFO;
 
 /** @name SVMIOIOEXIT.u1Type

trunk/src/VBox/VMM/VMMAll/HMSVMAll.cpp

@@ -741 +741 @@
 
 /**
- * Handles nested-guest SVM intercepts and performs the \#VMEXIT if the
+ * Handles nested-guest SVM control intercepts and performs the \#VMEXIT if the
  * intercept is active.
  *
@@ -751 +751 @@
  * @retval  VERR_SVM_VMEXIT_FAILED if the intercept is active and the \#VMEXIT
  *          failed and a shutdown needs to be initiated for the geust.
+ *
+ * @param   pVCpu       The cross context virtual CPU structure.
+ * @param   pCtx        The guest-CPU context.
+ * @param   uExitCode   The SVM exit code (see SVM_EXIT_XXX).
+ * @param   uExitInfo1  The exit info. 1 field.
+ * @param   uExitInfo2  The exit info. 2 field.
  */
 VMM_INT_DECL(VBOXSTRICTRC) HMSvmNstGstHandleCtrlIntercept(PVMCPU pVCpu, PCPUMCTX pCtx, uint64_t uExitCode, uint64_t uExitInfo1,
@@ -895 +901 @@
 
 
+/**
+ * Handles nested-guest SVM IO intercepts and performs the \#VMEXIT
+ * if the intercept is active.
+ *
+ * @returns Strict VBox status code.
+ * @retval  VINF_SVM_INTERCEPT_NOT_ACTIVE if the intercept is not active or
+ *          we're not executing a nested-guest.
+ * @retval  VINF_SVM_VMEXIT if the intercept is active and the \#VMEXIT occurred
+ *          successfully.
+ * @retval  VERR_SVM_VMEXIT_FAILED if the intercept is active and the \#VMEXIT
+ *          failed and a shutdown needs to be initiated for the geust.
+ *
+ * @param   pVCpu           The cross context virtual CPU structure.
+ * @param   pCtx            The guest-CPU context.
+ * @param   pIoExitInfo     The SVM IOIO exit info. structure.
+ * @param   uNextRip        The RIP of the instruction following the IO
+ *                          instruction.
+ */
+VMM_INT_DECL(VBOXSTRICTRC) HMSvmNstGstHandleIOIntercept(PVMCPU pVCpu, PCPUMCTX pCtx, PCSVMIOIOEXITINFO pIoExitInfo,
+                                                        uint64_t uNextRip)
+{
+    /*
+     * Check if any IO accesses are being intercepted.
+     */
+    if (CPUMIsGuestSvmCtrlInterceptSet(pCtx, SVM_CTRL_INTERCEPT_IOIO_PROT))
+    {
+        Assert(CPUMIsGuestInNestedHwVirtMode(pCtx));
+
+        /*
+         * The IOPM layout:
+         * Each bit represents one 8-bit port. That makes a total of 0..65535 bits or
+         * two 4K pages. However, since it's possible to do a 32-bit port IO at port
+         * 65534 (thus accessing 4 bytes), we need 3 extra bits beyond the two 4K page.
+         *
+         * For IO instructions that access more than a single byte, the permission bits
+         * for all bytes are checked; if any bit is set to 1, the IO access is intercepted.
+         */
+        uint8_t *pbIopm = (uint8_t *)pCtx->hwvirt.svm.CTX_SUFF(pvIoBitmap);
+
+        uint16_t const u16Port     = pIoExitInfo->n.u16Port;
+        uint16_t const offIoBitmap = u16Port >> 3;
+        uint16_t const fSizeMask   = pIoExitInfo->n.u1OP32 ? 0xf : pIoExitInfo->n.u1OP16 ? 3 : 1;
+        uint8_t  const cShift      = u16Port - (offIoBitmap << 3);
+        uint16_t const fIopmMask   = (1 << cShift) | (fSizeMask << cShift);
+
+        pbIopm += offIoBitmap;
+        uint16_t const fIopmBits = *(uint16_t *)pbIopm;
+        if (fIopmBits & fIopmMask)
+            return HMSvmNstGstVmExit(pVCpu, pCtx, SVM_EXIT_IOIO, pIoExitInfo->u, uNextRip);
+    }
+    return VINF_HM_INTERCEPT_NOT_ACTIVE;
+}
+
+
+/**
+ * Handles nested-guest SVM MSR read/write intercepts and performs the \#VMEXIT
+ * if the intercept is active.
+ *
+ * @returns Strict VBox status code.
+ * @retval  VINF_SVM_INTERCEPT_NOT_ACTIVE if the intercept is not active or
+ *          we're not executing a nested-guest.
+ * @retval  VINF_SVM_VMEXIT if the intercept is active and the \#VMEXIT occurred
+ *          successfully.
+ * @retval  VERR_SVM_VMEXIT_FAILED if the intercept is active and the \#VMEXIT
+ *          failed and a shutdown needs to be initiated for the geust.
+ *
+ * @param   pVCpu       The cross context virtual CPU structure.
+ * @param   pCtx        The guest-CPU context.
+ * @param   idMsr       The MSR being accessed in the nested-guest.
+ * @param   fWrite      Whether this is an MSR write access, @c false implies an
+ *                      MSR read.
+ */
 VMM_INT_DECL(VBOXSTRICTRC) HMSvmNstGstHandleMsrIntercept(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t idMsr, bool fWrite)
 {
@@ -938 +1016 @@
 }
 
+
+/**
+ * Gets the MSR permission bitmap byte and bit offset for the specified MSR.
+ *
+ * @returns VBox status code.
+ * @param   idMsr       The MSR being requested.
+ * @param   pbOffMsrpm  Where to store the byte offset in the MSR permission
+ *                      bitmap for @a idMsr.
+ * @param   puMsrpmBit  Where to store the bit offset starting at the byte
+ *                      returned in @a pbOffMsrpm.
+ */
 VMM_INT_DECL(int) hmSvmGetMsrpmOffsetAndBit(uint32_t idMsr, uint16_t *pbOffMsrpm, uint32_t *puMsrpmBit)
 {

trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp

@@ -4762 +4762 @@
 
     /* Refer AMD spec. 15.10.2 "IN and OUT Behaviour" and Figure 15-2. "EXITINFO1 for IOIO Intercept" for the format. */
-    SVMIOIOEXIT IoExitInfo;
+    SVMIOIOEXITINFO IoExitInfo;
     IoExitInfo.u       = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
     uint32_t uIOWidth  = (IoExitInfo.u >> 4) & 0x7;