VirtualBox

Changeset 66403 in vbox for trunk/src/VBox/VMM/VMMR3


Ignore:
Timestamp:
Apr 3, 2017 3:21:26 PM (8 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
114356
Message:

CPUM: Added the MXCSR mask to the CPU database and CPUM::GuestInfo as well as the host one to CPUM::fHostMxCsrMask. Need it for correctly implementing LDMXCSR, FXRSTOR and XSTOR.

Location:
trunk/src/VBox/VMM/VMMR3
Files:
23 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/VMMR3/CPUM.cpp

    r66276 r66403  
    884884    }
    885885
     886    pVM->cpum.s.fHostMxCsrMask = CPUMR3DeterminHostMxCsrMask();
     887
    886888    PCPUMCPUIDLEAF  paLeaves;
    887889    uint32_t        cLeaves;

  • trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp

    r66331 r66403  
    550550
    551551
     552/**
     553 * Determins the host CPU MXCSR mask.
     554 *
     555 * @returns MXCSR mask.
     556 */
     557VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void)
     558{
     559    if (   ASMHasCpuId()
     560        && ASMIsValidStdRange(ASMCpuId_EAX(0))
     561        && ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_FXSR)
     562    {
     563        uint8_t volatile abBuf[sizeof(X86FXSTATE) + 64];
     564        PX86FXSTATE      pState = (PX86FXSTATE)&abBuf[64 - ((uintptr_t)&abBuf[0] & 63)];
     565        RT_ZERO(*pState);
     566        ASMFxSave(pState);
     567        if (pState->MXCSR_MASK == 0)
     568            return 0xffbf;
     569        return pState->MXCSR_MASK;
     570    }
     571    return 0;
     572}
     573
    552574
    553575/**
    … …  
    39824004             : rc;
    39834005
     4006    if (pCpum->GuestInfo.fMxCsrMask & ~pVM->cpum.s.fHostMxCsrMask)
     4007    {
     4008        LogRel(("Stripping unsupported MXCSR bits from guest mask: %#x -> %#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask,
     4009                pCpum->GuestInfo.fMxCsrMask & pVM->cpum.s.fHostMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
     4010        pCpum->GuestInfo.fMxCsrMask &= pVM->cpum.s.fHostMxCsrMask;
     4011    }
     4012    LogRel(("CPUM: MXCSR_MASK=%#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
     4013
    39844014    /** @cfgm{/CPUM/MSRs/[Name]/[First|Last|Type|Value|...],}
    39854015     * Overrides the guest MSRs.

  • trunk/src/VBox/VMM/VMMR3/CPUMR3Db.cpp

    r63820 r66403  
    5858     * the value in CPUID leaf 0x80000008 when present. */
    5959    uint8_t         cMaxPhysAddrWidth;
     60    /** The MXCSR mask. */
     61    uint32_t        fMxCsrMask;
    6062    /** Pointer to an array of CPUID leaves.  */
    6163    PCCPUMCPUIDLEAF paCpuIdLeaves;
    … …  
    6769    CPUMCPUID       DefUnknownCpuId;
    6870
    69     /** MSR mask.  Several microarchitectures ignore higher bits of the    */
     71    /** MSR mask.  Several microarchitectures ignore the higher bits of ECX in
     72     *  the RDMSR and WRMSR instructions. */
    7073    uint32_t        fMsrMask;
    7174
    … …  
    800803        if (RT_FAILURE(rc))
    801804            return rc;
     805        pInfo->fMxCsrMask = CPUMR3DeterminHostMxCsrMask();
    802806
    803807        /* Lookup database entry for MSRs. */
    … …  
    917921
    918922        pInfo->enmUnknownCpuIdMethod = pEntry->enmUnknownCpuId;
    919         pInfo->DefCpuId         = pEntry->DefUnknownCpuId;
     923        pInfo->DefCpuId              = pEntry->DefUnknownCpuId;
     924        pInfo->fMxCsrMask            = pEntry->fMxCsrMask;
    920925
    921926        LogRel(("CPUM: Using CPU DB entry '%s' (%s %#x/%#x/%#x %s)\n",
    … …  
    926931    pInfo->fMsrMask             = pEntry->fMsrMask;
    927932    pInfo->iFirstExtCpuIdLeaf   = 0; /* Set by caller. */
    928     pInfo->uPadding             = 0;
    929933    pInfo->uScalableBusFreq     = pEntry->uScalableBusFreq;
    930934    pInfo->paCpuIdLeavesR0      = NIL_RTR0PTR;

  • trunk/src/VBox/VMM/VMMR3/cpus/AMD_Athlon_64_3200.h

    r62478 r66403  
    208208    /*.fFlags           = */ 0,
    209209    /*.cMaxPhysAddrWidth= */ 40,
     210    /*.fMxCsrMask       = */ 0xffff, ///< @todo check.
    210211    /*.paCpuIdLeaves    = */ NULL_ALONE(g_aCpuIdLeaves_AMD_Athlon_64_3200),
    211212    /*.cCpuIdLeaves     = */ ZERO_ALONE(RT_ELEMENTS(g_aCpuIdLeaves_AMD_Athlon_64_3200)),

  • trunk/src/VBox/VMM/VMMR3/cpus/AMD_Athlon_64_X2_Dual_Core_4200.h

    r62478 r66403  
    216216    /*.fFlags           = */ 0,
    217217    /*.cMaxPhysAddrWidth= */ 40,
     218    /*.fMxCsrMask       = */ 0xffff,
    218219    /*.paCpuIdLeaves    = */ NULL_ALONE(g_aCpuIdLeaves_AMD_Athlon_64_X2_Dual_Core_4200),
    219220    /*.cCpuIdLeaves     = */ ZERO_ALONE(RT_ELEMENTS(g_aCpuIdLeaves_AMD_Athlon_64_X2_Dual_Core_4200)),

  • trunk/src/VBox/VMM/VMMR3/cpus/AMD_FX_8150_Eight_Core.h

    r62478 r66403  
    367367    /*.fFlags           = */ 0,
    368368    /*.cMaxPhysAddrWidth= */ 48,
     369    /*.fMxCsrMask       = */ 0x2ffff,
    369370    /*.paCpuIdLeaves    = */ NULL_ALONE(g_aCpuIdLeaves_AMD_FX_8150_Eight_Core),
    370371    /*.cCpuIdLeaves     = */ ZERO_ALONE(RT_ELEMENTS(g_aCpuIdLeaves_AMD_FX_8150_Eight_Core)),

  • trunk/src/VBox/VMM/VMMR3/cpus/AMD_Phenom_II_X6_1100T.h

    r62478 r66403  
    256256    /*.fFlags           = */ 0,
    257257    /*.cMaxPhysAddrWidth= */ 48,
     258    /*.fMxCsrMask       = */ 0x2ffff,
    258259    /*.paCpuIdLeaves    = */ NULL_ALONE(g_aCpuIdLeaves_AMD_Phenom_II_X6_1100T),
    259260    /*.cCpuIdLeaves     = */ ZERO_ALONE(RT_ELEMENTS(g_aCpuIdLeaves_AMD_Phenom_II_X6_1100T)),

  • trunk/src/VBox/VMM/VMMR3/cpus/Intel_80186.h

    r60411 r66403  
    5959    /*.fFlags           = */ CPUDB_F_EXECUTE_ALL_IN_IEM,
    6060    /*.cMaxPhysAddrWidth= */ 20,
     61    /*.fMxCsrMask       = */ 0,
    6162    /*.paCpuIdLeaves    = */ NULL_ALONE(g_aCpuIdLeaves_Intel_80186),
    6263    /*.cCpuIdLeaves     = */ ZERO_ALONE(RT_ELEMENTS(g_aCpuIdLeaves_Intel_80186)),

  • trunk/src/VBox/VMM/VMMR3/cpus/Intel_80286.h

    r60411 r66403  
    5959    /*.fFlags           = */ CPUDB_F_EXECUTE_ALL_IN_IEM,
    6060    /*.cMaxPhysAddrWidth= */ 24,
     61    /*.fMxCsrMask       = */ 0,
    6162    /*.paCpuIdLeaves    = */ NULL_ALONE(g_aCpuIdLeaves_Intel_80286),
    6263    /*.cCpuIdLeaves     = */ ZERO_ALONE(RT_ELEMENTS(g_aCpuIdLeaves_Intel_80286)),

  • trunk/src/VBox/VMM/VMMR3/cpus/Intel_80386.h

    r60664 r66403  
    5959    /*.fFlags           = */ CPUDB_F_EXECUTE_ALL_IN_IEM,
    6060    /*.cMaxPhysAddrWidth= */ 24,
     61    /*.fMxCsrMask       = */ 0,
    6162    /*.paCpuIdLeaves    = */ NULL_ALONE(g_aCpuIdLeaves_Intel_80386),
    6263    /*.cCpuIdLeaves     = */ ZERO_ALONE(RT_ELEMENTS(g_aCpuIdLeaves_Intel_80386)),

  • trunk/src/VBox/VMM/VMMR3/cpus/Intel_8086.h

    r60411 r66403  
    5959    /*.fFlags           = */ CPUDB_F_EXECUTE_ALL_IN_IEM,
    6060    /*.cMaxPhysAddrWidth= */ 20,
     61    /*.fMxCsrMask       = */ 0,
    6162    /*.paCpuIdLeaves    = */ NULL_ALONE(g_aCpuIdLeaves_Intel_8086),
    6263    /*.cCpuIdLeaves     = */ ZERO_ALONE(RT_ELEMENTS(g_aCpuIdLeaves_Intel_8086)),

  • trunk/src/VBox/VMM/VMMR3/cpus/Intel_Atom_330_1_60GHz.h

    r62478 r66403  
    194194    /*.fFlags           = */ 0,
    195195    /*.cMaxPhysAddrWidth= */ 32,
     196    /*.fMxCsrMask       = */ 0xffff,
    196197    /*.paCpuIdLeaves    = */ NULL_ALONE(g_aCpuIdLeaves_Intel_Atom_330_1_60GHz),
    197198    /*.cCpuIdLeaves     = */ ZERO_ALONE(RT_ELEMENTS(g_aCpuIdLeaves_Intel_Atom_330_1_60GHz)),

  • trunk/src/VBox/VMM/VMMR3/cpus/Intel_Core_i5_3570.h

    r62478 r66403  
    323323    /*.fFlags           = */ 0,
    324324    /*.cMaxPhysAddrWidth= */ 36,
     325    /*.fMxCsrMask       = */ 0xffff,
    325326    /*.paCpuIdLeaves    = */ NULL_ALONE(g_aCpuIdLeaves_Intel_Core_i5_3570),
    326327    /*.cCpuIdLeaves     = */ ZERO_ALONE(RT_ELEMENTS(g_aCpuIdLeaves_Intel_Core_i5_3570)),

  • trunk/src/VBox/VMM/VMMR3/cpus/Intel_Core_i7_2635QM.h

    r62478 r66403  
    316316    /*.fFlags           = */ 0,
    317317    /*.cMaxPhysAddrWidth= */ 36,
     318    /*.fMxCsrMask       = */ 0xffff,
    318319    /*.paCpuIdLeaves    = */ NULL_ALONE(g_aCpuIdLeaves_Intel_Core_i7_2635QM),
    319320    /*.cCpuIdLeaves     = */ ZERO_ALONE(RT_ELEMENTS(g_aCpuIdLeaves_Intel_Core_i7_2635QM)),

  • trunk/src/VBox/VMM/VMMR3/cpus/Intel_Core_i7_3960X.h

    r62478 r66403  
    353353    /*.fFlags           = */ 0,
    354354    /*.cMaxPhysAddrWidth= */ 46,
     355    /*.fMxCsrMask       = */ 0xffff,
    355356    /*.paCpuIdLeaves    = */ NULL_ALONE(g_aCpuIdLeaves_Intel_Core_i7_3960X),
    356357    /*.cCpuIdLeaves     = */ ZERO_ALONE(RT_ELEMENTS(g_aCpuIdLeaves_Intel_Core_i7_3960X)),

  • trunk/src/VBox/VMM/VMMR3/cpus/Intel_Core_i7_5600U.h

    r62478 r66403  
    352352    /*.fFlags           = */ 0,
    353353    /*.cMaxPhysAddrWidth= */ 39,
     354    /*.fMxCsrMask       = */ 0xffff,
    354355    /*.paCpuIdLeaves    = */ NULL_ALONE(g_aCpuIdLeaves_Intel_Core_i7_5600U),
    355356    /*.cCpuIdLeaves     = */ ZERO_ALONE(RT_ELEMENTS(g_aCpuIdLeaves_Intel_Core_i7_5600U)),

  • trunk/src/VBox/VMM/VMMR3/cpus/Intel_Core_i7_6700K.h

    r62478 r66403  
    494494    /*.fFlags           = */ 0,
    495495    /*.cMaxPhysAddrWidth= */ 39,
     496    /*.fMxCsrMask       = */ 0xffff,
    496497    /*.paCpuIdLeaves    = */ NULL_ALONE(g_aCpuIdLeaves_Intel_Core_i7_6700K),
    497498    /*.cCpuIdLeaves     = */ ZERO_ALONE(RT_ELEMENTS(g_aCpuIdLeaves_Intel_Core_i7_6700K)),

  • trunk/src/VBox/VMM/VMMR3/cpus/Intel_Pentium_4_3_00GHz.h

    r62478 r66403  
    261261    /*.fFlags           = */ 0,
    262262    /*.cMaxPhysAddrWidth= */ 36,
     263    /*.fMxCsrMask       = */ 0xffff,
    263264    /*.paCpuIdLeaves    = */ NULL_ALONE(g_aCpuIdLeaves_Intel_Pentium_4_3_00GHz),
    264265    /*.cCpuIdLeaves     = */ ZERO_ALONE(RT_ELEMENTS(g_aCpuIdLeaves_Intel_Pentium_4_3_00GHz)),

  • trunk/src/VBox/VMM/VMMR3/cpus/Intel_Pentium_M_processor_2_00GHz.h

    r62478 r66403  
    200200    /*.fFlags           = */ 0,
    201201    /*.cMaxPhysAddrWidth= */ 32,
     202    /*.fMxCsrMask       = */ 0xffbf, ///< @todo check this
    202203    /*.paCpuIdLeaves    = */ NULL_ALONE(g_aCpuIdLeaves_Intel_Pentium_M_processor_2_00GHz),
    203204    /*.cCpuIdLeaves     = */ ZERO_ALONE(RT_ELEMENTS(g_aCpuIdLeaves_Intel_Pentium_M_processor_2_00GHz)),

  • trunk/src/VBox/VMM/VMMR3/cpus/Intel_Pentium_N3530_2_16GHz.h

    r62478 r66403  
    249249    /*.fFlags           = */ 0,
    250250    /*.cMaxPhysAddrWidth= */ 36,
     251    /*.fMxCsrMask       = */ 0xffff,
    251252    /*.paCpuIdLeaves    = */ NULL_ALONE(g_aCpuIdLeaves_Intel_Pentium_N3530_2_16GHz),
    252253    /*.cCpuIdLeaves     = */ ZERO_ALONE(RT_ELEMENTS(g_aCpuIdLeaves_Intel_Pentium_N3530_2_16GHz)),

  • trunk/src/VBox/VMM/VMMR3/cpus/Intel_Xeon_X5482_3_20GHz.h

    r62478 r66403  
    229229    /*.fFlags           = */ 0,
    230230    /*.cMaxPhysAddrWidth= */ 38,
     231    /*.fMxCsrMask       = */ 0xffff,
    231232    /*.paCpuIdLeaves    = */ NULL_ALONE(g_aCpuIdLeaves_Intel_Xeon_X5482_3_20GHz),
    232233    /*.cCpuIdLeaves     = */ ZERO_ALONE(RT_ELEMENTS(g_aCpuIdLeaves_Intel_Xeon_X5482_3_20GHz)),

  • trunk/src/VBox/VMM/VMMR3/cpus/Quad_Core_AMD_Opteron_2384.h

    r62478 r66403  
    254254    /*.fFlags           = */ 0,
    255255    /*.cMaxPhysAddrWidth= */ 48,
     256    /*.fMxCsrMask       = */ 0x2ffff,
    256257    /*.paCpuIdLeaves    = */ NULL_ALONE(g_aCpuIdLeaves_Quad_Core_AMD_Opteron_2384),
    257258    /*.cCpuIdLeaves     = */ ZERO_ALONE(RT_ELEMENTS(g_aCpuIdLeaves_Quad_Core_AMD_Opteron_2384)),

  • trunk/src/VBox/VMM/VMMR3/cpus/VIA_QuadCore_L4700_1_2_GHz.h

    r62478 r66403  
    388388    /*.fFlags           = */ 0,
    389389    /*.cMaxPhysAddrWidth= */ 36,
     390    /*.fMxCsrMask       = */ 0xffff,
    390391    /*.paCpuIdLeaves    = */ NULL_ALONE(g_aCpuIdLeaves_VIA_QuadCore_L4700_1_2_GHz),
    391392    /*.cCpuIdLeaves     = */ ZERO_ALONE(RT_ELEMENTS(g_aCpuIdLeaves_VIA_QuadCore_L4700_1_2_GHz)),
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