Changeset 66419 in vbox for trunk/src/VBox/VMM/VMMAll
- Timestamp:
- Apr 4, 2017 3:49:07 PM (8 years ago)
- svn:sync-xref-src-repo-rev:
- 114379
- Location:
- trunk/src/VBox/VMM/VMMAll
- Files:
-
- 3 edited
-
IEMAllInstructionsOneByte.cpp.h (modified) (4 diffs)
-
IEMAllInstructionsPython.py (modified) (2 diffs)
-
IEMAllInstructionsTwoByte0f.cpp.h (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsOneByte.cpp.h
r66160 r66419 6173 6173 FNIEMOP_DEF(iemOp_les_Gv_Mp__vex2) 6174 6174 { 6175 /* The LES instruction is invalid 64-bit mode. In legacy and6176 compatability mode it is invalid with MOD=3.6177 The use as a VEX prefix is made possible by assigning the inverted6178 REX.R to the top MOD bit, and the top bit in the inverted register6179 specifier to the bottom MOD bit, thereby effectively limiting 32-bit6180 to accessing registers 0..7 in this VEX form. */6181 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);6182 if ( pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT6183 || (bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))6184 {6185 IEMOP_MNEMONIC(vex2_prefix, "vex2");6186 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx)6187 {6188 uint8_t bOpcode; IEM_OPCODE_GET_NEXT_U8(&bOpcode);6189 if ( ( pVCpu->iem.s.fPrefixes6190 & (IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REPZ | IEM_OP_PRF_REPNZ | IEM_OP_PRF_LOCK | IEM_OP_PRF_REX))6191 == 0)6192 {6193 pVCpu->iem.s.fPrefixes |= IEM_OP_PRF_VEX;6194 pVCpu->iem.s.uRexReg = ~bRm >> (7 - 3);6195 pVCpu->iem.s.uVex3rdReg = (~bRm >> 3) & 0xf;6196 pVCpu->iem.s.uVexLength = (bRm >> 2) & 1;6197 pVCpu->iem.s.idxPrefix = bRm & 0x3;6198 6199 return FNIEMOP_CALL(g_apfnVexMap1[(uintptr_t)bOpcode * 4 + pVCpu->iem.s.idxPrefix]);6200 }6201 6202 Log(("VEX2: Invalid prefix mix!\n"));6203 }6204 else6205 Log(("VEX2: AVX support disabled!\n"));6206 6207 /* @todo does intel completely decode the sequence with SIB/disp before \#UD? */6208 return IEMOP_RAISE_INVALID_OPCODE();6209 }6210 IEMOP_MNEMONIC(les_Gv_Mp, "les Gv,Mp");6211 return FNIEMOP_CALL_2(iemOpCommonLoadSRegAndGreg, X86_SREG_ES, bRm);6212 }6213 6214 6215 /**6216 * @opcode 0xc56217 */6218 FNIEMOP_DEF(iemOp_lds_Gv_Mp__vex3)6219 {6220 6175 /* The LDS instruction is invalid 64-bit mode. In legacy and 6221 6176 compatability mode it is invalid with MOD=3. … … 6228 6183 if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT)) 6229 6184 { 6230 IEMOP_MNEMONIC(l ds_Gv_Mp, "lds Gv,Mp");6231 return FNIEMOP_CALL_2(iemOpCommonLoadSRegAndGreg, X86_SREG_ DS, bRm);6185 IEMOP_MNEMONIC(les_Gv_Mp, "les Gv,Mp"); 6186 return FNIEMOP_CALL_2(iemOpCommonLoadSRegAndGreg, X86_SREG_ES, bRm); 6232 6187 } 6233 6188 IEMOP_HLP_NO_REAL_OR_V86_MODE(); … … 6281 6236 Log(("VEX3: AVX support disabled!\n")); 6282 6237 return IEMOP_RAISE_INVALID_OPCODE(); 6238 } 6239 6240 6241 /** 6242 * @opcode 0xc5 6243 */ 6244 FNIEMOP_DEF(iemOp_lds_Gv_Mp__vex3) 6245 { 6246 /* The LES instruction is invalid 64-bit mode. In legacy and 6247 compatability mode it is invalid with MOD=3. 6248 The use as a VEX prefix is made possible by assigning the inverted 6249 REX.R to the top MOD bit, and the top bit in the inverted register 6250 specifier to the bottom MOD bit, thereby effectively limiting 32-bit 6251 to accessing registers 0..7 in this VEX form. */ 6252 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 6253 if ( pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT 6254 || (bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT)) 6255 { 6256 IEMOP_MNEMONIC(vex2_prefix, "vex2"); 6257 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx) 6258 { 6259 uint8_t bOpcode; IEM_OPCODE_GET_NEXT_U8(&bOpcode); 6260 if ( ( pVCpu->iem.s.fPrefixes 6261 & (IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REPZ | IEM_OP_PRF_REPNZ | IEM_OP_PRF_LOCK | IEM_OP_PRF_REX)) 6262 == 0) 6263 { 6264 pVCpu->iem.s.fPrefixes |= IEM_OP_PRF_VEX; 6265 pVCpu->iem.s.uRexReg = ~bRm >> (7 - 3); 6266 pVCpu->iem.s.uVex3rdReg = (~bRm >> 3) & 0xf; 6267 pVCpu->iem.s.uVexLength = (bRm >> 2) & 1; 6268 pVCpu->iem.s.idxPrefix = bRm & 0x3; 6269 6270 return FNIEMOP_CALL(g_apfnVexMap1[(uintptr_t)bOpcode * 4 + pVCpu->iem.s.idxPrefix]); 6271 } 6272 6273 Log(("VEX2: Invalid prefix mix!\n")); 6274 } 6275 else 6276 Log(("VEX2: AVX support disabled!\n")); 6277 6278 /* @todo does intel completely decode the sequence with SIB/disp before \#UD? */ 6279 return IEMOP_RAISE_INVALID_OPCODE(); 6280 } 6281 6282 IEMOP_MNEMONIC(lds_Gv_Mp, "lds Gv,Mp"); 6283 return FNIEMOP_CALL_2(iemOpCommonLoadSRegAndGreg, X86_SREG_DS, bRm); 6283 6284 } 6284 6285 … … 11753 11754 /* 0xbc */ iemOp_eSP_Iv, iemOp_eBP_Iv, iemOp_eSI_Iv, iemOp_eDI_Iv, 11754 11755 /* 0xc0 */ iemOp_Grp2_Eb_Ib, iemOp_Grp2_Ev_Ib, iemOp_retn_Iw, iemOp_retn, 11755 /* 0xc4 */ iemOp_les_Gv_Mp__vex 2, iemOp_lds_Gv_Mp__vex3, iemOp_Grp11_Eb_Ib, iemOp_Grp11_Ev_Iz,11756 /* 0xc4 */ iemOp_les_Gv_Mp__vex3, iemOp_lds_Gv_Mp__vex2, iemOp_Grp11_Eb_Ib, iemOp_Grp11_Ev_Iz, 11756 11757 /* 0xc8 */ iemOp_enter_Iw_Ib, iemOp_leave, iemOp_retf_Iw, iemOp_retf, 11757 11758 /* 0xcc */ iemOp_int3, iemOp_int_Ib, iemOp_into, iemOp_iret, -
trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsPython.py
r66412 r66419 268 268 269 269 ## IEMFORM_XXX mappings. 270 g_kdIemForms = { # sEncoding, [ sWhere1, ... ] 271 'RM': ( 'ModR/M', [ 'reg', 'rm' ], ), 272 'RM_REG': ( 'ModR/M', [ 'reg', 'rm' ], ), 273 'RM_MEM': ( 'ModR/M', [ 'reg', 'rm' ], ), 274 'MR': ( 'ModR/M', [ 'rm', 'reg' ], ), 275 'MR_REG': ( 'ModR/M', [ 'rm', 'reg' ], ), 276 'MR_MEM': ( 'ModR/M', [ 'rm', 'reg' ], ), 277 'M': ( 'ModR/M', [ 'rm', ], ), 278 'M_REG': ( 'ModR/M', [ 'rm', ], ), 279 'M_MEM': ( 'ModR/M', [ 'rm', ], ), 280 'R': ( 'ModR/M', [ 'reg', ], ), 281 'RVM': ( 'ModR/M+VEX', [ 'reg', 'vvvv', 'rm'], ), 282 'MVR': ( 'ModR/M+VEX', [ 'rm', 'vvvv', 'reg'], ), 283 'FIXED': ( 'fixed', None, ) 270 g_kdIemForms = { # sEncoding, [ sWhere1, ... ] 271 'RM': ( 'ModR/M', [ 'reg', 'rm' ], ), 272 'RM_REG': ( 'ModR/M', [ 'reg', 'rm' ], ), 273 'RM_MEM': ( 'ModR/M', [ 'reg', 'rm' ], ), 274 'MR': ( 'ModR/M', [ 'rm', 'reg' ], ), 275 'MR_REG': ( 'ModR/M', [ 'rm', 'reg' ], ), 276 'MR_MEM': ( 'ModR/M', [ 'rm', 'reg' ], ), 277 'M': ( 'ModR/M', [ 'rm', ], ), 278 'M_REG': ( 'ModR/M', [ 'rm', ], ), 279 'M_MEM': ( 'ModR/M', [ 'rm', ], ), 280 'R': ( 'ModR/M', [ 'reg', ], ), 281 282 'VEX_RM': ( 'VEX.ModR/M', [ 'reg', 'rm' ], ), 283 'VEX_RM_REG': ( 'VEX.ModR/M', [ 'reg', 'rm' ], ), 284 'VEX_RM_MEM': ( 'VEX.ModR/M', [ 'reg', 'rm' ], ), 285 'VEX_MR': ( 'VEX.ModR/M', [ 'rm', 'reg' ], ), 286 'VEX_MR_REG': ( 'VEX.ModR/M', [ 'rm', 'reg' ], ), 287 'VEX_MR_MEM': ( 'VEX.ModR/M', [ 'rm', 'reg' ], ), 288 'VEX_M': ( 'VEX.ModR/M', [ 'rm', ], ), 289 'VEX_M_REG': ( 'VEX.ModR/M', [ 'rm', ], ), 290 'VEX_M_MEM': ( 'VEX.ModR/M', [ 'rm', ], ), 291 'VEX_R': ( 'VEX.ModR/M', [ 'reg', ], ), 292 'VEX_RVM': ( 'VEX.ModR/M', [ 'reg', 'vvvv', 'rm'], ), 293 'VEX_MVR': ( 'VEX.ModR/M', [ 'rm', 'vvvv', 'reg'], ), 294 295 'FIXED': ( 'fixed', None, ) 284 296 }; 285 297 … … 313 325 ## Valid values for \@openc 314 326 g_kdEncodings = { 315 'ModR/M': [ 'BS3CG1ENC_MODRM', ], ##< ModR/M 316 'fixed': [ 'BS3CG1ENC_FIXED', ], ##< Fixed encoding (address, registers, etc). 317 'prefix': [ None, ], ##< Prefix 327 'ModR/M': [ 'BS3CG1ENC_MODRM', ], ##< ModR/M 328 'VEX.ModR/M': [ 'BS3CG1ENC_VEX_MODRM', ], ##< VEX...ModR/M 329 'fixed': [ 'BS3CG1ENC_FIXED', ], ##< Fixed encoding (address, registers, etc). 330 'prefix': [ None, ], ##< Prefix 318 331 }; 319 332 -
trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h
r66414 r66419 5903 5903 * @opcode !11/3 5904 5904 * @oppfx none 5905 * @opcpuid sse5905 * @opcpuid avx 5906 5906 * @opgroup og_avx_mxcsrsm 5907 * @optest ignmxcsr=0 -> op1=05908 * @optest ignmxcsr=0x2083 -> op1=0x20835907 * @optest mxcsr=0 -> op1=0 5908 * @optest mxcsr=0x2083 -> op1=0x2083 5909 5909 * @optestign mxcsr=0x2084 cr0|=ts -> value.xcpt=0x7 5910 5910 * @optestign mxcsr=0x2085 cr0|=em -> value.xcpt=0x6 … … 5915 5915 * @optestign mxcsr=0x208a cr0|=ts,em cr4&~=osfxsr -> value.xcpt=0x6 5916 5916 * @optestign mxcsr=0x208b cr0|=ts,em,mp cr4&~=osfxsr -> value.xcpt=0x6 5917 * @oponlytest 5917 5918 */ 5918 5919 FNIEMOP_DEF_1(iemOp_VGrp15_vstmxcsr, uint8_t, bRm) 5919 5920 { 5920 IEMOP_MNEMONIC1( M_MEM, VSTMXCSR, vstmxcsr, MdWO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);5921 IEMOP_MNEMONIC1(VEX_M_MEM, VSTMXCSR, vstmxcsr, MdWO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE); 5921 5922 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx) 5922 5923 return IEMOP_RAISE_INVALID_OPCODE();
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