Index: /trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp.h
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp.h	(revision 66461)
+++ /trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp.h	(revision 66462)
@@ -180,4 +180,26 @@
     uint32_t fEFlags = pCtx->eflags.u;
     iemAImpl_test_u8(&u8Result, u8Result, &fEFlags);
+    pCtx->eflags.u &= ~(fToUpdate | fUndefined);
+    pCtx->eflags.u |= (fToUpdate | fUndefined) & fEFlags;
+#ifdef IEM_VERIFICATION_MODE_FULL
+    pVCpu->iem.s.fUndefinedEFlags |= fUndefined;
+#endif
+}
+
+
+/**
+ * Updates the specified flags according to a 16-bit result.
+ *
+ * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
+ * @param   u16Result           The result to set the flags according to.
+ * @param   fToUpdate           The flags to update.
+ * @param   fUndefined          The flags that are specified as undefined.
+ */
+static void iemHlpUpdateArithEFlagsU16(PVMCPU pVCpu, uint16_t u16Result, uint32_t fToUpdate, uint32_t fUndefined)
+{
+    PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
+
+    uint32_t fEFlags = pCtx->eflags.u;
+    iemAImpl_test_u16(&u16Result, u16Result, &fEFlags);
     pCtx->eflags.u &= ~(fToUpdate | fUndefined);
     pCtx->eflags.u |= (fToUpdate | fUndefined) & fEFlags;
@@ -6488,20 +6510,42 @@
     PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
 
-    uint8_t const uMaskedAl = pCtx->al & 0xf;
-    if (   pCtx->eflags.Bits.u1AF
-        || uMaskedAl >= 10)
-    {
-        pCtx->ax = (pCtx->ax + UINT16_C(0x106)) & UINT16_C(0xff0f);
-        pCtx->eflags.Bits.u1AF = 1;
-        pCtx->eflags.Bits.u1CF = 1;
+    if (IEM_IS_GUEST_CPU_AMD(pVCpu))
+    {
+        if (   pCtx->eflags.Bits.u1AF
+            || (pCtx->ax & 0xf) >= 10)
+        {
+            iemAImpl_add_u16(&pCtx->ax, 0x106, &pCtx->eflags.u32);
+            pCtx->eflags.Bits.u1AF = 1;
+            pCtx->eflags.Bits.u1CF = 1;
+#ifdef IEM_VERIFICATION_MODE_FULL
+            pVCpu->iem.s.fUndefinedEFlags |= X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF;
+#endif
+        }
+        else
+        {
+            iemHlpUpdateArithEFlagsU16(pVCpu, pCtx->ax, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
+            pCtx->eflags.Bits.u1AF = 0;
+            pCtx->eflags.Bits.u1CF = 0;
+        }
+        pCtx->ax &= UINT16_C(0xff0f);
     }
     else
     {
-        pCtx->al = uMaskedAl;
-        pCtx->eflags.Bits.u1AF = 0;
-        pCtx->eflags.Bits.u1CF = 0;
-    }
-
-    iemHlpUpdateArithEFlagsU8(pVCpu, pCtx->al, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
+        if (   pCtx->eflags.Bits.u1AF
+            || (pCtx->ax & 0xf) >= 10)
+        {
+            pCtx->ax += UINT16_C(0x106);
+            pCtx->eflags.Bits.u1AF = 1;
+            pCtx->eflags.Bits.u1CF = 1;
+        }
+        else
+        {
+            pCtx->eflags.Bits.u1AF = 0;
+            pCtx->eflags.Bits.u1CF = 0;
+        }
+        pCtx->ax &= UINT16_C(0xff0f);
+        iemHlpUpdateArithEFlagsU8(pVCpu, pCtx->al, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
+    }
+
     iemRegAddToRipAndClearRF(pVCpu, cbInstr);
     return VINF_SUCCESS;
@@ -6516,21 +6560,42 @@
     PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
 
-    uint8_t const uMaskedAl = pCtx->al & 0xf;
-    if (   pCtx->eflags.Bits.u1AF
-        || uMaskedAl >= 10)
-    {
-        pCtx->ax  = (pCtx->ax - 6) & UINT16_C(0xff0f);
-        pCtx->ah -= 1;
-        pCtx->eflags.Bits.u1AF = 1;
-        pCtx->eflags.Bits.u1CF = 1;
+    if (IEM_IS_GUEST_CPU_AMD(pVCpu))
+    {
+        if (   pCtx->eflags.Bits.u1AF
+            || (pCtx->ax & 0xf) >= 10)
+        {
+            iemAImpl_sub_u16(&pCtx->ax, 0x106, &pCtx->eflags.u32);
+            pCtx->eflags.Bits.u1AF = 1;
+            pCtx->eflags.Bits.u1CF = 1;
+#ifdef IEM_VERIFICATION_MODE_FULL
+            pVCpu->iem.s.fUndefinedEFlags |= X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF;
+#endif
+        }
+        else
+        {
+            iemHlpUpdateArithEFlagsU16(pVCpu, pCtx->ax, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
+            pCtx->eflags.Bits.u1AF = 0;
+            pCtx->eflags.Bits.u1CF = 0;
+        }
+        pCtx->ax &= UINT16_C(0xff0f);
     }
     else
     {
-        pCtx->al = uMaskedAl;
-        pCtx->eflags.Bits.u1AF = 0;
-        pCtx->eflags.Bits.u1CF = 0;
-    }
-
-    iemHlpUpdateArithEFlagsU8(pVCpu, pCtx->al, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
+        if (   pCtx->eflags.Bits.u1AF
+            || (pCtx->ax & 0xf) >= 10)
+        {
+            pCtx->ax -= UINT16_C(0x106);
+            pCtx->eflags.Bits.u1AF = 1;
+            pCtx->eflags.Bits.u1CF = 1;
+        }
+        else
+        {
+            pCtx->eflags.Bits.u1AF = 0;
+            pCtx->eflags.Bits.u1CF = 0;
+        }
+        pCtx->ax &= UINT16_C(0xff0f);
+        iemHlpUpdateArithEFlagsU8(pVCpu, pCtx->al, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
+    }
+
     iemRegAddToRipAndClearRF(pVCpu, cbInstr);
     return VINF_SUCCESS;
Index: /trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsOneByte.cpp.h
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsOneByte.cpp.h	(revision 66461)
+++ /trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsOneByte.cpp.h	(revision 66462)
@@ -903,22 +903,35 @@
  * @opflundef   pf,zf,sf,of
  * @opgroup     og_gen_arith_dec
- * @optest      efl&~=af ax=9      -> efl&|=nc,po,na,nz,pl,nv
- * @optest      efl&~=af ax=0      -> efl&|=nc,po,na,zf,pl,nv
- * @optest      efl&~=af ax=0x00f0 -> ax=0x0000 efl&|=nc,po,na,zf,pl,nv
- * @optest      efl&~=af ax=0x00f9 -> ax=0x0009 efl&|=nc,po,na,nz,pl,nv
- * @optest      efl|=af  ax=0      -> ax=0x0106 efl&|=cf,po,af,nz,pl,nv
- * @optest      efl|=af  ax=0x0100 -> ax=0x0206 efl&|=cf,po,af,nz,pl,nv
- * @optest      efl|=af  ax=0x000a -> ax=0x0100 efl&|=cf,po,af,zf,pl,nv
- * @optest      efl|=af  ax=0x010a -> ax=0x0200 efl&|=cf,po,af,zf,pl,nv
- * @optest      efl|=af  ax=0x0f0a -> ax=0x1000 efl&|=cf,po,af,zf,pl,nv
- * @optest      efl|=af  ax=0x7f0a -> ax=0x8000 efl&|=cf,po,af,zf,pl,nv
- * @optest      efl|=af  ax=0xff0a -> ax=0x0000 efl&|=cf,po,af,zf,pl,nv
- * @optest      efl&~=af ax=0xff0a -> ax=0x0000 efl&|=cf,po,af,zf,pl,nv
- * @optest      efl&~=af ax=0x000b -> ax=0x0101 efl&|=cf,pe,af,nz,pl,nv
- * @optest      efl&~=af ax=0x000c -> ax=0x0102 efl&|=cf,pe,af,nz,pl,nv
- * @optest      efl&~=af ax=0x000d -> ax=0x0103 efl&|=cf,po,af,nz,pl,nv
- * @optest      efl&~=af ax=0x000e -> ax=0x0104 efl&|=cf,pe,af,nz,pl,nv
- * @optest      efl&~=af ax=0x000f -> ax=0x0105 efl&|=cf,po,af,nz,pl,nv
- * @optest      efl&~=af ax=0x020f -> ax=0x0305 efl&|=cf,po,af,nz,pl,nv
+ * @optest              efl&~=af ax=9      -> efl&|=nc,po,na,nz,pl,nv
+ * @optest              efl&~=af ax=0      -> efl&|=nc,po,na,zf,pl,nv
+ * @optest      intel / efl&~=af ax=0x00f0 -> ax=0x0000 efl&|=nc,po,na,zf,pl,nv
+ * @optest      amd   / efl&~=af ax=0x00f0 -> ax=0x0000 efl&|=nc,po,na,nz,pl,nv
+ * @optest              efl&~=af ax=0x00f9 -> ax=0x0009 efl&|=nc,po,na,nz,pl,nv
+ * @optest              efl|=af  ax=0      -> ax=0x0106 efl&|=cf,po,af,nz,pl,nv
+ * @optest              efl|=af  ax=0x0100 -> ax=0x0206 efl&|=cf,po,af,nz,pl,nv
+ * @optest      intel / efl|=af  ax=0x000a -> ax=0x0100 efl&|=cf,po,af,zf,pl,nv
+ * @optest      amd   / efl|=af  ax=0x000a -> ax=0x0100 efl&|=cf,pe,af,nz,pl,nv
+ * @optest      intel / efl|=af  ax=0x010a -> ax=0x0200 efl&|=cf,po,af,zf,pl,nv
+ * @optest      amd   / efl|=af  ax=0x010a -> ax=0x0200 efl&|=cf,pe,af,nz,pl,nv
+ * @optest      intel / efl|=af  ax=0x0f0a -> ax=0x1000 efl&|=cf,po,af,zf,pl,nv
+ * @optest      amd   / efl|=af  ax=0x0f0a -> ax=0x1000 efl&|=cf,pe,af,nz,pl,nv
+ * @optest      intel / efl|=af  ax=0x7f0a -> ax=0x8000 efl&|=cf,po,af,zf,pl,nv
+ * @optest      amd   / efl|=af  ax=0x7f0a -> ax=0x8000 efl&|=cf,pe,af,nz,ng,ov
+ * @optest      intel / efl|=af  ax=0xff0a -> ax=0x0000 efl&|=cf,po,af,zf,pl,nv
+ * @optest      amd   / efl|=af  ax=0xff0a -> ax=0x0000 efl&|=cf,pe,af,nz,pl,nv
+ * @optest      intel / efl&~=af ax=0xff0a -> ax=0x0000 efl&|=cf,po,af,zf,pl,nv
+ * @optest      amd   / efl&~=af ax=0xff0a -> ax=0x0000 efl&|=cf,pe,af,nz,pl,nv
+ * @optest      intel / efl&~=af ax=0x000b -> ax=0x0101 efl&|=cf,pe,af,nz,pl,nv
+ * @optest      amd   / efl&~=af ax=0x000b -> ax=0x0101 efl&|=cf,po,af,nz,pl,nv
+ * @optest      intel / efl&~=af ax=0x000c -> ax=0x0102 efl&|=cf,pe,af,nz,pl,nv
+ * @optest      amd   / efl&~=af ax=0x000c -> ax=0x0102 efl&|=cf,po,af,nz,pl,nv
+ * @optest      intel / efl&~=af ax=0x000d -> ax=0x0103 efl&|=cf,po,af,nz,pl,nv
+ * @optest      amd   / efl&~=af ax=0x000d -> ax=0x0103 efl&|=cf,pe,af,nz,pl,nv
+ * @optest      intel / efl&~=af ax=0x000e -> ax=0x0104 efl&|=cf,pe,af,nz,pl,nv
+ * @optest      amd   / efl&~=af ax=0x000e -> ax=0x0104 efl&|=cf,po,af,nz,pl,nv
+ * @optest      intel / efl&~=af ax=0x000f -> ax=0x0105 efl&|=cf,po,af,nz,pl,nv
+ * @optest      amd   / efl&~=af ax=0x000f -> ax=0x0105 efl&|=cf,pe,af,nz,pl,nv
+ * @optest      intel / efl&~=af ax=0x020f -> ax=0x0305 efl&|=cf,po,af,nz,pl,nv
+ * @optest      amd   / efl&~=af ax=0x020f -> ax=0x0305 efl&|=cf,pe,af,nz,pl,nv
  */
 FNIEMOP_DEF(iemOp_aaa)
@@ -1013,23 +1026,39 @@
  * @opflundef   pf,zf,sf,of
  * @opgroup     og_gen_arith_dec
- * @optest      efl&~=af ax=0x0009 -> efl&|=nc,po,na,nz,pl,nv
- * @optest      efl&~=af ax=0x0000 -> efl&|=nc,po,na,zf,pl,nv
- * @optest      efl&~=af ax=0x00f0 -> ax=0x0000 efl&|=nc,po,na,zf,pl,nv
- * @optest      efl&~=af ax=0x00f9 -> ax=0x0009 efl&|=nc,po,na,nz,pl,nv
- * @optest      efl|=af  ax=0x0000 -> ax=0xfe0a efl&|=cf,po,af,nz,pl,nv
- * @optest      efl|=af  ax=0x0100 -> ax=0xff0a efl&|=cf,po,af,nz,pl,nv
- * @optest      efl|=af  ax=0x000a -> ax=0xff04 efl&|=cf,pe,af,nz,pl,nv
- * @optest      efl|=af  ax=0x010a -> ax=0x0004 efl&|=cf,pe,af,nz,pl,nv
- * @optest      efl|=af  ax=0x020a -> ax=0x0104 efl&|=cf,pe,af,nz,pl,nv
- * @optest      efl|=af  ax=0x0f0a -> ax=0x0e04 efl&|=cf,pe,af,nz,pl,nv
- * @optest      efl|=af  ax=0x7f0a -> ax=0x7e04 efl&|=cf,pe,af,nz,pl,nv
- * @optest      efl|=af  ax=0xff0a -> ax=0xfe04 efl&|=cf,pe,af,nz,pl,nv
- * @optest      efl&~=af ax=0xff0a -> ax=0xfe04 efl&|=cf,pe,af,nz,pl,nv
- * @optest      efl&~=af ax=0xff09 -> ax=0xff09 efl&|=nc,po,na,nz,pl,nv
- * @optest      efl&~=af ax=0x000b -> ax=0xff05 efl&|=cf,po,af,nz,pl,nv
- * @optest      efl&~=af ax=0x000c -> ax=0xff06 efl&|=cf,po,af,nz,pl,nv
- * @optest      efl&~=af ax=0x000d -> ax=0xff07 efl&|=cf,pe,af,nz,pl,nv
- * @optest      efl&~=af ax=0x000e -> ax=0xff08 efl&|=cf,pe,af,nz,pl,nv
- * @optest      efl&~=af ax=0x000f -> ax=0xff09 efl&|=cf,po,af,nz,pl,nv
+ * @optest            / efl&~=af ax=0x0009 -> efl&|=nc,po,na,nz,pl,nv
+ * @optest            / efl&~=af ax=0x0000 -> efl&|=nc,po,na,zf,pl,nv
+ * @optest      intel / efl&~=af ax=0x00f0 -> ax=0x0000 efl&|=nc,po,na,zf,pl,nv
+ * @optest      amd   / efl&~=af ax=0x00f0 -> ax=0x0000 efl&|=nc,po,na,nz,pl,nv
+ * @optest            / efl&~=af ax=0x00f9 -> ax=0x0009 efl&|=nc,po,na,nz,pl,nv
+ * @optest      intel / efl|=af  ax=0x0000 -> ax=0xfe0a efl&|=cf,po,af,nz,pl,nv
+ * @optest      amd   / efl|=af  ax=0x0000 -> ax=0xfe0a efl&|=cf,po,af,nz,ng,nv
+ * @optest      intel / efl|=af  ax=0x0100 -> ax=0xff0a efl&|=cf,po,af,nz,pl,nv
+ * @optest8     amd   / efl|=af  ax=0x0100 -> ax=0xff0a efl&|=cf,po,af,nz,ng,nv
+ * @optest      intel / efl|=af  ax=0x000a -> ax=0xff04 efl&|=cf,pe,af,nz,pl,nv
+ * @optest10    amd   / efl|=af  ax=0x000a -> ax=0xff04 efl&|=cf,pe,af,nz,ng,nv
+ * @optest            / efl|=af  ax=0x010a -> ax=0x0004 efl&|=cf,pe,af,nz,pl,nv
+ * @optest            / efl|=af  ax=0x020a -> ax=0x0104 efl&|=cf,pe,af,nz,pl,nv
+ * @optest            / efl|=af  ax=0x0f0a -> ax=0x0e04 efl&|=cf,pe,af,nz,pl,nv
+ * @optest            / efl|=af  ax=0x7f0a -> ax=0x7e04 efl&|=cf,pe,af,nz,pl,nv
+ * @optest      intel / efl|=af  ax=0xff0a -> ax=0xfe04 efl&|=cf,pe,af,nz,pl,nv
+ * @optest      amd   / efl|=af  ax=0xff0a -> ax=0xfe04 efl&|=cf,pe,af,nz,ng,nv
+ * @optest      intel / efl&~=af ax=0xff0a -> ax=0xfe04 efl&|=cf,pe,af,nz,pl,nv
+ * @optest      amd   / efl&~=af ax=0xff0a -> ax=0xfe04 efl&|=cf,pe,af,nz,ng,nv
+ * @optest      intel / efl&~=af ax=0xff09 -> ax=0xff09 efl&|=nc,po,na,nz,pl,nv
+ * @optest      amd   / efl&~=af ax=0xff09 -> ax=0xff09 efl&|=nc,po,na,nz,ng,nv
+ * @optest      intel / efl&~=af ax=0x000b -> ax=0xff05 efl&|=cf,po,af,nz,pl,nv
+ * @optest22    amd   / efl&~=af ax=0x000b -> ax=0xff05 efl&|=cf,po,af,nz,ng,nv
+ * @optest      intel / efl&~=af ax=0x000c -> ax=0xff06 efl&|=cf,po,af,nz,pl,nv
+ * @optest24    amd   / efl&~=af ax=0x000c -> ax=0xff06 efl&|=cf,po,af,nz,ng,nv
+ * @optest      intel / efl&~=af ax=0x000d -> ax=0xff07 efl&|=cf,pe,af,nz,pl,nv
+ * @optest26    amd   / efl&~=af ax=0x000d -> ax=0xff07 efl&|=cf,pe,af,nz,ng,nv
+ * @optest      intel / efl&~=af ax=0x000e -> ax=0xff08 efl&|=cf,pe,af,nz,pl,nv
+ * @optest28    amd   / efl&~=af ax=0x000e -> ax=0xff08 efl&|=cf,pe,af,nz,ng,nv
+ * @optest      intel / efl&~=af ax=0x000f -> ax=0xff09 efl&|=cf,po,af,nz,pl,nv
+ * @optest30    amd   / efl&~=af ax=0x000f -> ax=0xff09 efl&|=cf,po,af,nz,ng,nv
+ * @optest31    intel / efl&~=af ax=0x00fa -> ax=0xff04 efl&|=cf,pe,af,nz,pl,nv
+ * @optest32    amd   / efl&~=af ax=0x00fa -> ax=0xff04 efl&|=cf,pe,af,nz,ng,nv
+ * @optest33    intel / efl&~=af ax=0xfffa -> ax=0xfe04 efl&|=cf,pe,af,nz,pl,nv
+ * @optest34    amd   / efl&~=af ax=0xfffa -> ax=0xfe04 efl&|=cf,pe,af,nz,ng,nv
  */
 FNIEMOP_DEF(iemOp_aas)
Index: /trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsPython.py
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsPython.py	(revision 66461)
+++ /trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsPython.py	(revision 66462)
@@ -1269,5 +1269,5 @@
         self.fUnused        = False;    ##< Unused instruction.
         self.fInvalid       = False;    ##< Invalid instruction (like UD2).
-        self.sInvalidStyle  = None;     ##< Invalid behviour style
+        self.sInvalidStyle  = None;     ##< Invalid behviour style (g_kdInvalidStyles),
         self.sXcptType      = None;     ##< Exception type (g_kdXcptTypes).
         ## @}
@@ -1557,4 +1557,5 @@
             '@optestignore': self.parseTagOpTestIgnore,
             '@opcopytests': self.parseTagOpCopyTests,
+            '@oponly':      self.parseTagOpOnlyTest,
             '@oponlytest':  self.parseTagOpOnlyTest,
             '@opxcpttype':  self.parseTagOpXcptType,
@@ -1563,4 +1564,7 @@
             '@opdone':      self.parseTagOpDone,
         };
+        for i in range(48):
+            self.dTagHandlers['@optest%u' % (i,)]   = self.parseTagOpTestNum;
+            self.dTagHandlers['@optest[%u]' % (i,)] = self.parseTagOpTestNum;
 
         self.asErrors = [];
@@ -2490,4 +2494,20 @@
         return True;
 
+    def parseTagOpTestNum(self, sTag, aasSections, iTagLine, iEndLine):
+        """
+        Numbered \@optest tag.  Either \@optest42 or \@optest[42].
+        """
+        oInstr = self.ensureInstructionForOpTag(iTagLine);
+
+        iTest = 0;
+        if sTag[-1] == ']':
+            iTest = int(sTag[8:-1]);
+        else:
+            iTest = int(sTag[7:]);
+
+        if iTest != len(oInstr.aoTests):
+            self.errorComment(iTagLine, '%s: incorrect test number: %u, actual %u' % (sTag, iTest, len(oInstr.aoTests),));
+        return self.parseTagOpTest(sTag, aasSections, iTagLine, iEndLine);
+
     def parseTagOpTestIgnore(self, sTag, aasSections, iTagLine, iEndLine):
         """
@@ -2533,5 +2553,5 @@
     def parseTagOpOnlyTest(self, sTag, aasSections, iTagLine, iEndLine):
         """
-        Tag:        \@oponlytest
+        Tag:        \@oponlytest | \@oponly
         Value:      none
 
Index: /trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h	(revision 66461)
+++ /trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h	(revision 66462)
@@ -5938,5 +5938,4 @@
  *              APMv4 rev 3.17 page 509.
  * @todo        Test this instruction on AMD Ryzen.
- * @oponlytest
  */
 FNIEMOP_DEF_1(iemOp_VGrp15_vstmxcsr,  uint8_t, bRm)
@@ -6786,5 +6785,5 @@
  * @opcode      0xb9
  * @opinvalid   intel-modrm
- * @optest      op1=1 op2=2 ->
+ * @optest      ->
  */
 FNIEMOP_DEF(iemOp_Grp10)
@@ -6794,5 +6793,4 @@
      * too. See bs3-cpu-decoder-1.c32.  So, we can forward to iemOp_InvalidNeedRM.
      */
-    /** @todo fix bs3-cpu-generated-1 to deal with this on AMD! */
     Log(("iemOp_Grp10 aka UD1 -> #UD\n"));
     IEMOP_MNEMONIC2EX(ud1, "ud1", RM, UD1, ud1, Gb, Eb, DISOPTYPE_INVALID, IEMOPHINT_IGNORES_OP_SIZE); /* just picked Gb,Eb here. */
Index: /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-data.py
===================================================================
--- /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-data.py	(revision 66461)
+++ /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-data.py	(revision 66462)
@@ -315,4 +315,6 @@
         elif oInstr.fInvalid:
             self.asFlags.append('BS3CG1INSTR_F_INVALID');
+        if oInstr.sInvalidStyle and oInstr.sInvalidStyle.startswith('intel-'):
+            self.asFlags.append('BS3CG1INSTR_F_INTEL_DECODES_INVALID');
 
         self.fAdvanceMnemonic   = True; ##< Set by the caller.
@@ -350,8 +352,11 @@
     def getInstructionEntry(self):
         """ Returns an array of BS3CG1INSTR member initializers. """
+        sOperands = ', '.join([oOp.sType for oOp in self.oInstr.aoOperands]);
+        if sOperands:
+            sOperands = ' /* ' + sOperands + ' */';
         return [
-            '        /* cbOpcodes = */        %s,' % (len(self.asOpcodes),),
-            '        /* cOperands = */        %s,' % (len(self.oInstr.aoOperands),),
-            '        /* cchMnemonic = */      %s,' % (len(self.oInstr.sMnemonic),),
+            '        /* cbOpcodes = */        %s, /* %s */' % (len(self.asOpcodes), ' '.join(self.asOpcodes),),
+            '        /* cOperands = */        %s,%s' % (len(self.oInstr.aoOperands), sOperands,),
+            '        /* cchMnemonic = */      %s, /* %s */' % (len(self.oInstr.sMnemonic), self.oInstr.sMnemonic,),
             '        /* fAdvanceMnemonic = */ %s,' % ('true' if self.fAdvanceMnemonic else 'false',),
             '        /* offTests = */         %s,' % (self.oTests.offTests,),
Index: /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c
===================================================================
--- /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c	(revision 66461)
+++ /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c	(revision 66462)
@@ -1264,5 +1264,4 @@
         {
             BS3CG1_DPRINTF(("Bs3MemSet(%p,%#x,%#x)\n", &pThis->pbDataPg[X86_PAGE_SIZE - cbOp - cbMissalign], 0xcc, cbOp - cbMissalign));
-            ASMHalt();
             Bs3MemSet(&pThis->pbDataPg[X86_PAGE_SIZE - cbOp - cbMissalign], 0xcc, cbOp - cbMissalign);
             break;
@@ -2201,5 +2200,4 @@
 
         default:
-            ASMHalt();
             Bs3TestFailedF("Invalid/unimplemented enmEncoding for instruction #%RU32 (%.*s): %d",
                            pThis->iInstr, pThis->cchMnemonic, pThis->pchMnemonic, pThis->enmEncoding);
@@ -2207,4 +2205,24 @@
     }
     return true;
+}
+
+
+/**
+ * Calculates the appropriate non-intel invalid instruction encoding.
+ *
+ * @returns the encoding to use instead.
+ * @param   enmEncoding         The intel invalid instruction encoding.
+ */
+static BS3CG1ENC Bs3Cg1CalcNoneIntelInvalidEncoding(BS3CG1ENC enmEncoding)
+{
+    switch (enmEncoding)
+    {
+        case BS3CG1ENC_MODRM_Gb_Eb:
+        case BS3CG1ENC_FIXED:
+            return BS3CG1ENC_FIXED;
+        default:
+            Bs3TestFailedF("Bs3Cg1CalcNoneIntelInvalidEncoding: Unsupported encoding: %d\n", enmEncoding);
+            return BS3CG1ENC_FIXED;
+    }
 }
 
@@ -3508,4 +3526,11 @@
         }
 
+        /* Switch the encoder for some of the invalid instructions on non-intel CPUs. */
+        if (   (pThis->fFlags & BS3CG1INSTR_F_INTEL_DECODES_INVALID)
+            && pThis->bCpuVendor != BS3CPUVENDOR_INTEL
+            && (   (pThis->fFlags & (BS3CG1INSTR_F_UNUSED | BS3CG1INSTR_F_INVALID))
+                || (BS3_MODE_IS_64BIT_CODE(pThis->bMode) && (pThis->fFlags & BS3CG1INSTR_F_INVALID_64BIT)) ) )
+            pThis->enmEncoding = Bs3Cg1CalcNoneIntelInvalidEncoding(pThis->enmEncoding);
+
         /*
          * Check if the CPU supports the instruction.
Index: /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h
===================================================================
--- /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h	(revision 66461)
+++ /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h	(revision 66462)
@@ -243,11 +243,14 @@
  * @{ */
 /** Defaults to SS rather than DS. */
-#define BS3CG1INSTR_F_DEF_SS            UINT32_C(0x00000001)
+#define BS3CG1INSTR_F_DEF_SS                UINT32_C(0x00000001)
 /** Invalid instruction in 64-bit mode. */
-#define BS3CG1INSTR_F_INVALID_64BIT     UINT32_C(0x00000002)
+#define BS3CG1INSTR_F_INVALID_64BIT         UINT32_C(0x00000002)
 /** Unused instruction. */
-#define BS3CG1INSTR_F_UNUSED            UINT32_C(0x00000004)
+#define BS3CG1INSTR_F_UNUSED                UINT32_C(0x00000004)
 /** Invalid instruction. */
-#define BS3CG1INSTR_F_INVALID           UINT32_C(0x00000008)
+#define BS3CG1INSTR_F_INVALID               UINT32_C(0x00000008)
+/** Only intel does full ModR/M(, ++) decoding for invalid instruction.
+ * Always used with BS3CG1INSTR_F_INVALID or BS3CG1INSTR_F_UNUSED. */
+#define BS3CG1INSTR_F_INTEL_DECODES_INVALID UINT32_C(0x00000010)
 /** @} */
 
