Index: /trunk/src/VBox/VMM/VMMAll/IEMAllInstructions.cpp.h
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/IEMAllInstructions.cpp.h	(revision 66462)
+++ /trunk/src/VBox/VMM/VMMAll/IEMAllInstructions.cpp.h	(revision 66463)
@@ -549,4 +549,23 @@
 
 
+/** Invalid with RM byte where both AMD and Intel decodes any additional
+ *  address encoding bytes. */
+FNIEMOPRM_DEF(iemOp_InvalidWithRMAllNeeded)
+{
+    IEMOP_MNEMONIC(InvalidWithRMAllNeeded, "InvalidWithRMAllNeeded");
+#ifndef TST_IEM_CHECK_MC
+    if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
+    {
+        RTGCPTR      GCPtrEff;
+        VBOXSTRICTRC rcStrict = iemOpHlpCalcRmEffAddr(pVCpu, bRm, 0, &GCPtrEff);
+        if (rcStrict != VINF_SUCCESS)
+            return rcStrict;
+    }
+#endif
+    IEMOP_HLP_DONE_DECODING();
+    return IEMOP_RAISE_INVALID_OPCODE();
+}
+
+
 /** Invalid with RM byte where intel requires 8-byte immediate.
  * Intel will also need SIB and displacement if bRm indicates memory. */
@@ -614,4 +633,23 @@
 
 
+/** Invalid opcode where both AMD and Intel requires Mod R/M sequence. */
+FNIEMOP_DEF(iemOp_InvalidAllNeedRM)
+{
+    IEMOP_MNEMONIC(InvalidAllNeedRM, "InvalidAllNeedRM");
+    uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); RT_NOREF(bRm);
+#ifndef TST_IEM_CHECK_MC
+    if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
+    {
+        RTGCPTR      GCPtrEff;
+        VBOXSTRICTRC rcStrict = iemOpHlpCalcRmEffAddr(pVCpu, bRm, 0, &GCPtrEff);
+        if (rcStrict != VINF_SUCCESS)
+            return rcStrict;
+    }
+#endif
+    IEMOP_HLP_DONE_DECODING();
+    return IEMOP_RAISE_INVALID_OPCODE();
+}
+
+
 /** Invalid opcode where intel requires Mod R/M sequence and 8-byte
  *  immediate. */
Index: /trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsOneByte.cpp.h
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsOneByte.cpp.h	(revision 66462)
+++ /trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsOneByte.cpp.h	(revision 66463)
@@ -1974,5 +1974,5 @@
         {
             Log(("evex not supported by the guest CPU!\n"));
-            return FNIEMOP_CALL(iemOp_InvalidNeedRM);
+            return FNIEMOP_CALL(iemOp_InvalidAllNeedRM);
         }
         IEM_OPCODE_GET_NEXT_U8(&bRm);
Index: /trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h	(revision 66462)
+++ /trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h	(revision 66463)
@@ -6028,5 +6028,5 @@
     IEMOP_MNEMONIC1(M_MEM, CLFLUSH, clflush, MbRO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
     if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fClFlush)
-        return IEMOP_RAISE_INVALID_OPCODE();
+        return FNIEMOP_CALL_1(iemOp_InvalidWithRMAllNeeded, bRm);
 
     IEM_MC_BEGIN(2, 0);
@@ -6053,5 +6053,5 @@
     IEMOP_MNEMONIC1(M_MEM, CLFLUSHOPT, clflushopt, MbRO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
     if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fClFlushOpt)
-        return IEMOP_RAISE_INVALID_OPCODE();
+        return FNIEMOP_CALL_1(iemOp_InvalidWithRMAllNeeded, bRm);
 
     IEM_MC_BEGIN(2, 0);
Index: /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c
===================================================================
--- /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c	(revision 66462)
+++ /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c	(revision 66463)
@@ -121,4 +121,7 @@
     /** The encoding. */
     BS3CG1ENC               enmEncoding;
+    /** The non-invalid encoding.  This differs from enmEncoding when
+     * Bs3Cg1CalcNoneIntelInvalidEncoding has been called. */
+    BS3CG1ENC               enmEncodingNonInvalid;
     /** The CPU test / CPU ID. */
     BS3CG1CPU               enmCpuTest;
@@ -2219,4 +2222,5 @@
     {
         case BS3CG1ENC_MODRM_Gb_Eb:
+        case BS3CG1ENC_MODRM_Gv_Ma:
         case BS3CG1ENC_FIXED:
             return BS3CG1ENC_FIXED;
@@ -2703,4 +2707,6 @@
 
                     default:
+                        if (pThis->enmEncoding != pThis->enmEncodingNonInvalid)
+                            goto l_advance_to_next;
                         return Bs3TestFailedF("Internal error: cbDst=%u idxField=%d (%d) offField=%#x: enmLocation=%u off=%#x idxField=%u",
                                               cbDst, idxField, idxOp, offField, pThis->aOperands[idxOp].enmLocation,
@@ -2917,4 +2923,5 @@
          * Advance to the next instruction.
          */
+l_advance_to_next:
         pbCode += cbValue;
         cbLeft -= cbValue;
@@ -3497,17 +3504,18 @@
          */
         PCBS3CG1INSTR pInstr = &g_aBs3Cg1Instructions[iInstr];
-        pThis->iInstr          = iInstr;
-        pThis->pTestHdr        = (PCBS3CG1TESTHDR)&g_abBs3Cg1Tests[pInstr->offTests];
-        pThis->fFlags          = pInstr->fFlags;
-        pThis->enmEncoding     = (BS3CG1ENC)pInstr->enmEncoding;
-        pThis->enmCpuTest      = (BS3CG1CPU)pInstr->enmCpuTest;
-        pThis->enmPrefixKind   = (BS3CG1PFXKIND)pInstr->enmPrefixKind;
-        pThis->enmXcptType     = (BS3CG1XCPTTYPE)pInstr->enmXcptType;
-        pThis->cchMnemonic     = pInstr->cchMnemonic;
+        pThis->iInstr                   = iInstr;
+        pThis->pTestHdr                 = (PCBS3CG1TESTHDR)&g_abBs3Cg1Tests[pInstr->offTests];
+        pThis->fFlags                   = pInstr->fFlags;
+        pThis->enmEncoding              = (BS3CG1ENC)pInstr->enmEncoding;
+        pThis->enmEncodingNonInvalid    = (BS3CG1ENC)pInstr->enmEncoding;
+        pThis->enmCpuTest               = (BS3CG1CPU)pInstr->enmCpuTest;
+        pThis->enmPrefixKind            = (BS3CG1PFXKIND)pInstr->enmPrefixKind;
+        pThis->enmXcptType              = (BS3CG1XCPTTYPE)pInstr->enmXcptType;
+        pThis->cchMnemonic              = pInstr->cchMnemonic;
         if (pThis->fAdvanceMnemonic)
             Bs3TestSubF("%s / %.*s", pThis->pszModeShort, pThis->cchMnemonic, pThis->pchMnemonic);
-        pThis->fAdvanceMnemonic = pInstr->fAdvanceMnemonic;
-        pThis->cOperands       = pInstr->cOperands;
-        pThis->cbOpcodes       = pInstr->cbOpcodes;
+        pThis->fAdvanceMnemonic         = pInstr->fAdvanceMnemonic;
+        pThis->cOperands                = pInstr->cOperands;
+        pThis->cbOpcodes                = pInstr->cbOpcodes;
         switch (pThis->cOperands)
         {
@@ -3517,5 +3525,4 @@
             case 1: pThis->aenmOperands[0] = (BS3CG1OP)pThis->pabOperands[0];
         }
-
         switch (pThis->cbOpcodes)
         {
@@ -3526,11 +3533,4 @@
         }
 
-        /* Switch the encoder for some of the invalid instructions on non-intel CPUs. */
-        if (   (pThis->fFlags & BS3CG1INSTR_F_INTEL_DECODES_INVALID)
-            && pThis->bCpuVendor != BS3CPUVENDOR_INTEL
-            && (   (pThis->fFlags & (BS3CG1INSTR_F_UNUSED | BS3CG1INSTR_F_INVALID))
-                || (BS3_MODE_IS_64BIT_CODE(pThis->bMode) && (pThis->fFlags & BS3CG1INSTR_F_INVALID_64BIT)) ) )
-            pThis->enmEncoding = Bs3Cg1CalcNoneIntelInvalidEncoding(pThis->enmEncoding);
-
         /*
          * Check if the CPU supports the instruction.
@@ -3539,4 +3539,12 @@
             || (pThis->fFlags & (BS3CG1INSTR_F_UNUSED | BS3CG1INSTR_F_INVALID)))
             fOuterInvalidInstr = true;
+
+        /* Switch the encoder for some of the invalid instructions on non-intel CPUs. */
+        if (   (pThis->fFlags & BS3CG1INSTR_F_INTEL_DECODES_INVALID)
+            && pThis->bCpuVendor != BS3CPUVENDOR_INTEL
+            && (   (pThis->fFlags & (BS3CG1INSTR_F_UNUSED | BS3CG1INSTR_F_INVALID))
+                || (BS3_MODE_IS_64BIT_CODE(pThis->bMode) && (pThis->fFlags & BS3CG1INSTR_F_INVALID_64BIT))
+                || fOuterInvalidInstr ) )
+            pThis->enmEncoding = Bs3Cg1CalcNoneIntelInvalidEncoding(pThis->enmEncoding);
 
         for (iCpuSetup = 0;; iCpuSetup++)
@@ -3705,5 +3713,5 @@
 #if 0
     /* (for debugging) */
-    if (bMode != BS3_MODE_PPV86)
+    if (bMode < BS3_MODE_LM16)
         return BS3TESTDOMODE_SKIPPED;
 #endif
