VirtualBox

Changeset 66464 in vbox


Ignore:
Timestamp:
Apr 6, 2017 7:22:01 PM (8 years ago)
Author:
vboxsync
Message:

IEM: Implemented movss Vss,Wss (f3 0f 10).

Location:
trunk
Files:
6 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/VBox/disopcode.h

    r66457 r66464  
    10661066#define OP_PARM_UqHi            OP_PARM_Uq
    10671067#define OP_PARM_WqZxReg         OP_PARM_Wq              /**< Annotates that register targets get their upper bits cleared. */
     1068#define OP_PARM_VssZxReg        OP_PARM_Vss             /**< Annotates that register targets get their upper bits cleared. */
    10681069#define OP_PARM_MbRO            OP_PARM_Mb              /**< Annotates read only memory byte operand. */
    10691070#define OP_PARM_MdRO            OP_PARM_Md              /**< Annotates read only memory byte operand. */

  • trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsPython.py

    r66462 r66464  
    241241    'Gv':   ( 'IDX_UseModRM',       'reg',    '%Gv',  'Gv',      ),
    242242    'Vss':  ( 'IDX_UseModRM',       'reg',    '%Vss', 'Vss',     ),
     243    'VssZxReg': ( 'IDX_UseModRM',   'reg',    '%Vss', 'Vss',     ),
    243244    'Vsd':  ( 'IDX_UseModRM',       'reg',    '%Vsd', 'Vsd',     ),
    244245    'Vps':  ( 'IDX_UseModRM',       'reg',    '%Vps', 'Vps',     ),

  • trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h

    r66463 r66464  
    10701070/** Opcode 0x66 0x0f 0x10 - vmovupd Vpd, Wpd */
    10711071FNIEMOP_STUB(iemOp_vmovupd_Vpd_Wpd);
    1072 /** Opcode 0xf3 0x0f 0x10 - vmovss Vx, Hx, Wss */
    1073 FNIEMOP_STUB(iemOp_vmovss_Vx_Hx_Wss); //NEXT!!
     1072
     1073
     1074/**
     1075 * @opcode      0x10
     1076 * @oppfx       0xf3
     1077 * @opcpuid     sse
     1078 * @opgroup     og_sse_simdfp_datamove
     1079 * @opxcpttype  5
     1080 * @optest      op1=1 op2=2 -> op1=2
     1081 * @optest      op1=0 op2=-22 -> op1=-22
     1082 * @oponly
     1083 */
     1084FNIEMOP_DEF(iemOp_movss_Vss_Wss)
     1085{
     1086    IEMOP_MNEMONIC2(RM, MOVSS, movss, VssZxReg, Wss, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
     1087    uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
     1088    if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
     1089    {
     1090        /*
     1091         * Register, register.
     1092         */
     1093        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     1094        IEM_MC_BEGIN(0, 1);
     1095        IEM_MC_LOCAL(uint32_t,                  uSrc);
     1096
     1097        IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
     1098        IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
     1099        IEM_MC_FETCH_XREG_U32(uSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
     1100        IEM_MC_STORE_XREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
     1101
     1102        IEM_MC_ADVANCE_RIP();
     1103        IEM_MC_END();
     1104    }
     1105    else
     1106    {
     1107        /*
     1108         * Memory, register.
     1109         */
     1110        IEM_MC_BEGIN(0, 2);
     1111        IEM_MC_LOCAL(uint32_t,                  uSrc);
     1112        IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
     1113
     1114        IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
     1115        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
     1116        IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
     1117        IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
     1118
     1119        IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
     1120        IEM_MC_STORE_XREG_U32_ZX_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
     1121
     1122        IEM_MC_ADVANCE_RIP();
     1123        IEM_MC_END();
     1124    }
     1125    return VINF_SUCCESS;
     1126}
     1127
     1128
     1129/** Opcode VEX 0xf3 0x0f 0x10 - vmovsd Vx, Hx, Wsd */
     1130FNIEMOP_STUB(iemOp_vmovss_Vx_Hx_Wss);
     1131
    10741132/** Opcode 0xf2 0x0f 0x10 - vmovsd Vx, Hx, Wsd */
    10751133FNIEMOP_STUB(iemOp_vmovsd_Vx_Hx_Wsd);
    … …  
    83688426    /* 0x0f */  IEMOP_X4(iemOp_3Dnow),
    83698427
    8370     /* 0x10 */  iemOp_vmovups_Vps_Wps,      iemOp_vmovupd_Vpd_Wpd,      iemOp_vmovss_Vx_Hx_Wss,     iemOp_vmovsd_Vx_Hx_Wsd,
     8428    /* 0x10 */  iemOp_vmovups_Vps_Wps,      iemOp_vmovupd_Vpd_Wpd,      iemOp_movss_Vss_Wss,        iemOp_vmovsd_Vx_Hx_Wsd,
    83718429    /* 0x11 */  iemOp_vmovups_Wps_Vps,      iemOp_vmovupd_Wpd_Vpd,      iemOp_vmovss_Wss_Hx_Vss,    iemOp_vmovsd_Wsd_Hx_Vsd,
    83728430    /* 0x12 */  iemOp_vmovlps_Vq_Hq_Mq__vmovhlps, iemOp_vmovlpd_Vq_Hq_Mq, iemOp_vmovsldup_Vx_Wx,    iemOp_vmovddup_Vx_Wx,

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c

    r66463 r66464  
    513513    /* [BS3CG1DST_XMM14_DW0] = */   4,
    514514    /* [BS3CG1DST_XMM15_DW0] = */   4,
     515    /* [BS3CG1DST_XMM0_DW0_ZX] = */ 4,
     516    /* [BS3CG1DST_XMM1_DW0_ZX] = */ 4,
     517    /* [BS3CG1DST_XMM2_DW0_ZX] = */ 4,
     518    /* [BS3CG1DST_XMM3_DW0_ZX] = */ 4,
     519    /* [BS3CG1DST_XMM4_DW0_ZX] = */ 4,
     520    /* [BS3CG1DST_XMM5_DW0_ZX] = */ 4,
     521    /* [BS3CG1DST_XMM6_DW0_ZX] = */ 4,
     522    /* [BS3CG1DST_XMM7_DW0_ZX] = */ 4,
     523    /* [BS3CG1DST_XMM8_DW0_ZX] = */ 4,
     524    /* [BS3CG1DST_XMM9_DW0_ZX] = */ 4,
     525    /* [BS3CG1DST_XMM10_DW0_ZX] =*/ 4,
     526    /* [BS3CG1DST_XMM11_DW0_ZX] =*/ 4,
     527    /* [BS3CG1DST_XMM12_DW0_ZX] =*/ 4,
     528    /* [BS3CG1DST_XMM13_DW0_ZX] =*/ 4,
     529    /* [BS3CG1DST_XMM14_DW0_ZX] =*/ 4,
     530    /* [BS3CG1DST_XMM15_DW0_ZX] =*/ 4,
    515531    /* [BS3CG1DST_YMM0] = */        32,
    516532    /* [BS3CG1DST_YMM1] = */        32,
    … …  
    745761    /* [BS3CG1DST_XMM14_DW0] = */   sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]),
    746762    /* [BS3CG1DST_XMM15_DW0] = */   sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]),
     763    /* [BS3CG1DST_XMM0_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0]),
     764    /* [BS3CG1DST_XMM1_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1]),
     765    /* [BS3CG1DST_XMM2_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2]),
     766    /* [BS3CG1DST_XMM3_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3]),
     767    /* [BS3CG1DST_XMM4_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4]),
     768    /* [BS3CG1DST_XMM5_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5]),
     769    /* [BS3CG1DST_XMM6_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6]),
     770    /* [BS3CG1DST_XMM7_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7]),
     771    /* [BS3CG1DST_XMM8_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8]),
     772    /* [BS3CG1DST_XMM9_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9]),
     773    /* [BS3CG1DST_XMM10_DW0_ZX] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10]),
     774    /* [BS3CG1DST_XMM11_DW0_ZX] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11]),
     775    /* [BS3CG1DST_XMM12_DW0_ZX] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12]),
     776    /* [BS3CG1DST_XMM13_DW0_ZX] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13]),
     777    /* [BS3CG1DST_XMM14_DW0_ZX] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]),
     778    /* [BS3CG1DST_XMM15_DW0_ZX] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]),
    747779
    748780    /* [BS3CG1DST_YMM0] = */        ~0U,
    … …  
    9771009    { "XMM14_DW0" },
    9781010    { "XMM15_DW0" },
     1011    { "XMM0_DW0_ZX" },
     1012    { "XMM1_DW0_ZX" },
     1013    { "XMM2_DW0_ZX" },
     1014    { "XMM3_DW0_ZX" },
     1015    { "XMM4_DW0_ZX" },
     1016    { "XMM5_DW0_ZX" },
     1017    { "XMM6_DW0_ZX" },
     1018    { "XMM7_DW0_ZX" },
     1019    { "XMM8_DW0_ZX" },
     1020    { "XMM9_DW0_ZX" },
     1021    { "XMM10_DW0_ZX" },
     1022    { "XMM11_DW0_ZX" },
     1023    { "XMM12_DW0_ZX" },
     1024    { "XMM13_DW0_ZX" },
     1025    { "XMM14_DW0_ZX" },
     1026    { "XMM15_DW0_ZX" },
    9791027    { "YMM0" },
    9801028    { "YMM1" },
    … …  
    16121660
    16131661
     1662static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VssZxReg_Wss(PBS3CG1STATE pThis, unsigned iEncoding)
     1663{
     1664    unsigned off;
     1665    if (iEncoding == 0)
     1666    {
     1667        off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
     1668        pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 1, 0);
     1669        pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM0_LO;
     1670        pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM1_DW0_ZX;
     1671    }
     1672    else if (iEncoding == 1)
     1673    {
     1674        pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2_DW0_ZX;
     1675        off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
     1676        off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /*iReg*/, 4, 0, BS3CG1OPLOC_MEM);
     1677    }
     1678    else if (iEncoding == 2)
     1679    {
     1680        pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3_DW0_ZX;
     1681        off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
     1682        off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /*iReg*/, 4, 1 /*cbMissalign*/, BS3CG1OPLOC_MEM);
     1683    }
     1684    else
     1685        return 0;
     1686    pThis->cbCurInstr = off;
     1687    return iEncoding + 1;
     1688}
     1689
     1690
    16141691static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Gv_Ma(PBS3CG1STATE pThis, unsigned iEncoding)
    16151692{
    … …  
    19922069        case BS3CG1ENC_MODRM_Vdq_Wdq:
    19932070            return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Vdq_Wdq(pThis, iEncoding);
     2071        case BS3CG1ENC_MODRM_VssZxReg_Wss:
     2072            return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VssZxReg_Wss(pThis, iEncoding);
    19942073
    19952074        case BS3CG1ENC_MODRM_Gv_Ma:
    … …  
    21542233            pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
    21552234            pThis->aOperands[1].enmLocation = BS3CG1OPLOC_MEM;
     2235            break;
     2236
     2237        case BS3CG1ENC_MODRM_VssZxReg_Wss:
     2238            pThis->iRmOp             = 1;
     2239            pThis->iRegOp            = 0;
     2240            pThis->aOperands[0].cbOp = 4;
     2241            pThis->aOperands[1].cbOp = 4;
     2242            pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
     2243            pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
    21562244            break;
    21572245
    … …  
    27872875
    27882876                case 4:
    2789                     if (offField <= RT_OFFSETOF(BS3REGCTX, r15)) /* Clear the top dword. */
     2877                    if ((unsigned)(idxField - BS3CG1DST_XMM0_DW0_ZX) <= (unsigned)(BS3CG1DST_XMM15_DW0_ZX - BS3CG1DST_XMM0_DW0_ZX))
     2878                    {
     2879                        PtrField.pu32[1] = 0;
     2880                        PtrField.pu64[1] = 0;
     2881                    }
     2882                    else if (offField <= RT_OFFSETOF(BS3REGCTX, r15)) /* Clear the top dword. */
    27902883                        PtrField.pu32[1] = 0;
    27912884                    switch (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK)
    … …  
    30853178                    if (   pResult->Ctx.x87.aXMM[i].au64[0] != pExpect->Ctx.x87.aXMM[i].au64[0]
    30863179                        || pResult->Ctx.x87.aXMM[i].au64[1] != pExpect->Ctx.x87.aXMM[i].au64[1])
    3087                         fOkay = Bs3TestFailedF("XMM%u: %#010RX64'%08RX64, expected %#010RX64'%08RX64", i,
     3180                        fOkay = Bs3TestFailedF("XMM%u: %#010RX64'%016RX64, expected %#010RX64'%08RX64", i,
     3181                                               pResult->Ctx.x87.aXMM[i].au64[1],
    30883182                                               pResult->Ctx.x87.aXMM[i].au64[0],
    3089                                                pResult->Ctx.x87.aXMM[i].au64[1],
    3090                                                pExpect->Ctx.x87.aXMM[i].au64[0],
    3091                                                pExpect->Ctx.x87.aXMM[i].au64[1]);
     3183                                               pExpect->Ctx.x87.aXMM[i].au64[1],
     3184                                               pExpect->Ctx.x87.aXMM[i].au64[0]);
    30923185            }
    30933186            else
    … …  
    37133806#if 0
    37143807    /* (for debugging) */
    3715     if (bMode < BS3_MODE_LM16)
     3808    if (bMode != BS3_MODE_PP32)
    37163809        return BS3TESTDOMODE_SKIPPED;
    37173810#endif
    … …  
    37263819#if 0
    37273820    /* (for debugging) */
    3728     if (bMode >= BS3_MODE_LM64)
     3821    //if (bMode == BS3_MODE_PP32)
    37293822    {
    37303823        Bs3TestTerm();

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h

    r66462 r66464  
    5656    BS3CG1OP_UqHi,
    5757    BS3CG1OP_Vss,
     58    BS3CG1OP_VssZxReg,
    5859    BS3CG1OP_Vsd,
    5960    BS3CG1OP_Vps,
    … …  
    104105    BS3CG1ENC_MODRM_Vq_Mq,
    105106    BS3CG1ENC_MODRM_Vdq_Wdq,
     107    BS3CG1ENC_MODRM_VssZxReg_Wss,
    106108    BS3CG1ENC_MODRM_MbRO,
    107109    BS3CG1ENC_MODRM_MdRO,
    … …  
    532534    BS3CG1DST_XMM14_DW0,
    533535    BS3CG1DST_XMM15_DW0,
     536    BS3CG1DST_XMM0_DW0_ZX,
     537    BS3CG1DST_XMM1_DW0_ZX,
     538    BS3CG1DST_XMM2_DW0_ZX,
     539    BS3CG1DST_XMM3_DW0_ZX,
     540    BS3CG1DST_XMM4_DW0_ZX,
     541    BS3CG1DST_XMM5_DW0_ZX,
     542    BS3CG1DST_XMM6_DW0_ZX,
     543    BS3CG1DST_XMM7_DW0_ZX,
     544    BS3CG1DST_XMM8_DW0_ZX,
     545    BS3CG1DST_XMM9_DW0_ZX,
     546    BS3CG1DST_XMM10_DW0_ZX,
     547    BS3CG1DST_XMM11_DW0_ZX,
     548    BS3CG1DST_XMM12_DW0_ZX,
     549    BS3CG1DST_XMM13_DW0_ZX,
     550    BS3CG1DST_XMM14_DW0_ZX,
     551    BS3CG1DST_XMM15_DW0_ZX,
    534552    /* AVX registers. */
    535553    BS3CG1DST_YMM0,

  • trunk/src/VBox/ValidationKit/bootsectors/bs3kit/bs3-cmn-StrFormatV.c

    r62484 r66464  
    215215#if ARCH_BITS != 64
    216216    /* Avoid 64-bit division by formatting 64-bit numbers as hex if they're higher than _4G. */
    217     if (   pState->uBase == 10
    218         && !(uValue >> 32)) /* uValue <= UINT32_MAX does not work, trouble with 64-bit compile time math! */
    219         return bs3StrFormatU32(pState, uValue);
    220     pState->fFlags |= STR_F_SPECIAL;
    221     pState->uBase = 16;
     217    if (pState->uBase == 10)
     218    {
     219        if (!(uValue >> 32)) /* uValue <= UINT32_MAX does not work, trouble with 64-bit compile time math! */
     220            return bs3StrFormatU32(pState, uValue);
     221        pState->fFlags |= STR_F_SPECIAL;
     222        pState->uBase   = 16;
     223    }
    222224#endif
    223225
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