VirtualBox

Changeset 66581 in vbox for trunk/include


Ignore:
Timestamp:
Apr 17, 2017 3:00:00 AM (8 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
114608
Message:

VMM: Nested Hw.virt: Implemented various SVM intercepts in IEM, addressed some todos.

Location:
trunk/include
Files:
7 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/VBox/vmm/cpum.h

    r66403 r66581  
    10421042    uint32_t        fPadding : 23;
    10431043
    1044     /** Hardware virtualization features.
    1045      *
    1046      *  @todo r=bird: Please drop the unions and flatten this as much as possible.
    1047      *        Prefix the names with 'Svm' 'Vmx' if there is any confusion. Group the
    1048      *        flags into common and specific bunches.
    1049      *
    1050      */
    1051     union
    1052     {
    1053         /** SVM features.  */
    1054         struct
    1055         {
    1056             /** Features as reported by CPUID 0x8000000a.EDX.  */
    1057             union
    1058             {
    1059                 struct
    1060                 {
    1061                     uint32_t fNestedPaging         : 1;
    1062                     uint32_t fLbrVirt              : 1;
    1063                     uint32_t fSvmLock              : 1;
    1064                     uint32_t fNextRipSave          : 1;
    1065                     uint32_t fTscRateMsr           : 1;
    1066                     uint32_t fVmcbClean            : 1;
    1067                     uint32_t fFlusbByAsid          : 1;
    1068                     uint32_t fDecodeAssist         : 1;
    1069                     uint32_t u2Reserved0           : 2;
    1070                     uint32_t fPauseFilter          : 1;
    1071                     uint32_t u1Reserved0           : 1;
    1072                     uint32_t fPauseFilterThreshold : 1;
    1073                     uint32_t fAvic                 : 1;
    1074                     uint32_t u18Reserved0          : 18;
    1075                 } n;
    1076                 uint32_t    u;
    1077             } feat;
    1078             /** Maximum supported ASID. */
    1079             uint32_t        uMaxAsid;
    1080         } svm;
    1081 
    1082         /** VMX features. */
    1083         struct
    1084         {
    1085             uint32_t    uDummy1;
    1086             uint32_t    uDummy2;
    1087         } vmx;
    1088     } CPUM_UNION_NM(hwvirt);
     1044    /** SVM: Supports Nested-paging. */
     1045    uint32_t        fSvmNestedPaging : 1;
     1046    /** SVM: Support LBR (Last Branch Record) virtualization. */
     1047    uint32_t        fSvmLbrVirt : 1;
     1048    /** SVM: Supports SVM lock. */
     1049    uint32_t        fSvmSvmLock : 1;
     1050    /** SVM: Supports Next RIP save. */
     1051    uint32_t        fSvmNextRipSave : 1;
     1052    /** SVM: Supports TSC rate MSR. */
     1053    uint32_t        fSvmTscRateMsr : 1;
     1054    /** SVM: Supports VMCB clean bits. */
     1055    uint32_t        fSvmVmcbClean : 1;
     1056    /** SVM: Supports Flush-by-ASID. */
     1057    uint32_t        fSvmFlusbByAsid : 1;
     1058    /** SVM: Supports decode assist. */
     1059    uint32_t        fSvmDecodeAssist : 1;
     1060    /** SVM: Supports Pause filter. */
     1061    uint32_t        fSvmPauseFilter : 1;
     1062    /** SVM: Supports Pause filter threshold. */
     1063    uint32_t        fSvmPauseFilterThreshold : 1;
     1064    /** SVM: Supports AVIC (Advanced Virtual Interrupt Controller). */
     1065    uint32_t        fSvmAvic : 1;
     1066    /** SVM: Padding / reserved for future features. */
     1067    uint32_t        fSvmPadding0 : 21;
     1068    /** SVM: Maximum supported ASID. */
     1069    uint32_t        uSvmMaxAsid;
     1070
     1071    /** @todo VMX features. */
    10891072    uint32_t        auPadding[1];
    10901073} CPUMFEATURES;
    … …  
    13961379 * @returns true if in intercept is active, false otherwise.
    13971380 * @param   pCtx        Pointer to the context.
    1398  * @param   enmXcpt     The exception.
    1399  */
    1400 DECLINLINE(bool) CPUMIsGuestSvmXcptInterceptSet(PCCPUMCTX pCtx, X86XCPT enmXcpt)
    1401 {
    1402     return RT_BOOL(pCtx->hwvirt.svm.VmcbCtrl.u32InterceptXcpt & enmXcpt);
     1381 * @param   uVector     The exception / interrupt vector.
     1382 */
     1383DECLINLINE(bool) CPUMIsGuestSvmXcptInterceptSet(PCCPUMCTX pCtx, uint8_t uVector)
     1384{
     1385    Assert(uVector < 32);
     1386    return RT_BOOL(pCtx->hwvirt.svm.VmcbCtrl.u32InterceptXcpt & (UINT32_C(1) << uVector));
    14031387}
    14041388
    … …  
    15541538VMMDECL(uint32_t)       CPUMGetGuestMxCsrMask(PVM pVM);
    15551539VMMDECL(uint64_t)       CPUMGetGuestScalableBusFrequency(PVM pVM);
    1556 VMMDECL(int)            CPUMGetValidateEfer(PVM pVM, uint64_t uCr0, uint64_t uOldEfer, uint64_t uNewEfer,
    1557                                             uint64_t *puValidEfer);
     1540VMMDECL(int)            CPUMQueryValidatedGuestEfer(PVM pVM, uint64_t uCr0, uint64_t uOldEfer, uint64_t uNewEfer,
     1541                                                    uint64_t *puValidEfer);
    15581542
    15591543/** @name Typical scalable bus frequency values.

  • trunk/include/VBox/vmm/cpum.mac

    r66276 r66581  
    258258    .abPadding          resb    12
    259259%endif
    260     .hwvirt.svm.uMsrHSavePa         resq    1
    261     .hwvirt.svm.GCPhysVmcb          resq    1
    262     .hwvirt.svm.VmcbCtrl            resb  256
    263     .hwvirt.svm.HostState           resb  184
    264     .hwvirt.svm.fGif                resb    1
    265     .hwvirt.svm.abPadding0          resb    7
    266     .hwvirt.svm.pvMsrBitmapR0       RTR0PTR_RES 1
    267     .hwvirt.svm.pvMsrBitmapR3       RTR3PTR_RES 1
    268     .hwvirt.svm.pvIoBitmapR0        RTR0PTR_RES 1
    269     .hwvirt.svm.pvIoBitmapR3        RTR3PTR_RES 1
     260    .hwvirt.svm.uMsrHSavePa              resq    1
     261    .hwvirt.svm.GCPhysVmcb               resq    1
     262    .hwvirt.svm.VmcbCtrl                 resb  256
     263    .hwvirt.svm.HostState                resb  184
     264    .hwvirt.svm.fGif                     resb    1
     265    .hwvirt.svm.cPauseFilter             resw    1
     266    .hwvirt.svm.cPauseFilterThreshold    resw    1
     267    .hwvirt.svm.abPadding0               resb    3
     268    .hwvirt.svm.pvMsrBitmapR0            RTR0PTR_RES 1
     269    .hwvirt.svm.pvMsrBitmapR3            RTR3PTR_RES 1
     270    .hwvirt.svm.pvIoBitmapR0             RTR0PTR_RES 1
     271    .hwvirt.svm.pvIoBitmapR3             RTR3PTR_RES 1
    270272%if HC_ARCH_BITS == 32
    271     .hwvirt.svm.abPadding1          resb   16
    272 %endif
    273     .hwvirt.fLocalForcedActions     resd    1
     273    .hwvirt.svm.abPadding1               resb   16
     274%endif
     275    .hwvirt.fLocalForcedActions          resd    1
    274276    alignb 64
    275277endstruc

  • trunk/include/VBox/vmm/cpumctx.h

    r66277 r66581  
    485485                /** 1184 - Global interrupt flag. */
    486486                uint8_t             fGif;
    487                 /** 1185 - Padding. */
    488                 uint8_t             abPadding0[7];
     487                /** 1185 - Pause filter count. */
     488                uint16_t            cPauseFilter;
     489                /** 1187 - Pause filter count. */
     490                uint16_t            cPauseFilterThreshold;
     491                /** 1189 - Padding. */
     492                uint8_t             abPadding0[3];
    489493                /** 1192 - MSR permission bitmap - R0 ptr. */
    490494                R0PTRTYPE(void *)   pvMsrBitmapR0;
    … …  
    567571AssertCompileMemberOffset(CPUMCTX,                 aoffXState, HC_ARCH_BITS == 64 ? 596 : 588);
    568572AssertCompileMemberOffset(CPUMCTX, hwvirt, 728);
    569 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.uMsrHSavePa,      728);
    570 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.GCPhysVmcb,       736);
    571 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.VmcbCtrl,         744);
    572 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.HostState,       1000);
    573 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.fGif,            1184);
    574 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.pvMsrBitmapR0,   1192);
    575 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.pvMsrBitmapR3,   HC_ARCH_BITS == 64 ? 1200 : 1196);
    576 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.pvIoBitmapR0,    HC_ARCH_BITS == 64 ? 1208 : 1200);
    577 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.pvIoBitmapR3,    HC_ARCH_BITS == 64 ? 1216 : 1204);
    578 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) fLocalForcedActions, 1224);
     573AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.uMsrHSavePa,            728);
     574AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.GCPhysVmcb,             736);
     575AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.VmcbCtrl,               744);
     576AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.HostState,             1000);
     577AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.fGif,                  1184);
     578AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.cPauseFilter,          1185);
     579AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.cPauseFilterThreshold, 1187);
     580AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.pvMsrBitmapR0,         1192);
     581AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.pvMsrBitmapR3,         HC_ARCH_BITS == 64 ? 1200 : 1196);
     582AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.pvIoBitmapR0,          HC_ARCH_BITS == 64 ? 1208 : 1200);
     583AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.pvIoBitmapR3,          HC_ARCH_BITS == 64 ? 1216 : 1204);
     584AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) fLocalForcedActions,       1224);
    579585
    580586AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_NM(g.) aGRegs);

  • trunk/include/VBox/vmm/em.h

    r65792 r66581  
    199199VMM_INT_DECL(bool)              EMMonitorWaitShouldContinue(PVMCPU pVCpu, PCPUMCTX pCtx);
    200200VMM_INT_DECL(int)               EMMonitorWaitPrepare(PVMCPU pVCpu, uint64_t rax, uint64_t rcx, uint64_t rdx, RTGCPHYS GCPhys);
     201VMM_INT_DECL(bool)              EMMonitorIsArmed(PVMCPU pVCpu);
    201202VMM_INT_DECL(int)               EMMonitorWaitPerform(PVMCPU pVCpu, uint64_t rax, uint64_t rcx);
    202203VMM_INT_DECL(int)               EMUnhaltAndWakeUp(PVM pVM, PVMCPU pVCpuDst);

  • trunk/include/VBox/vmm/hm_svm.h

    r66373 r66581  
    4545 * @{
    4646 */
    47 
    48 /** @name SVM features for cpuid 0x8000000a
    49  * @{
    50  */
    51 /** Bit 0 - NP - Nested Paging supported. */
    52 #define AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING             RT_BIT(0)
    53 /** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
    54 #define AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT                  RT_BIT(1)
    55 /** Bit 2 - SVML - SVM locking bit supported. */
    56 #define AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK                  RT_BIT(2)
    57 /** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
    58 #define AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE                 RT_BIT(3)
    59 /** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
    60 #define AMD_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR              RT_BIT(4)
    61 /** Bit 5 - VmcbClean - Support VMCB clean bits. */
    62 #define AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN                RT_BIT(5)
    63 /** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
    64  *  VMCB.TLB_Control is supported. */
    65 #define AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID             RT_BIT(6)
    66 /** Bit 7 - DecodeAssist - Indicate decode assist is supported. */
    67 #define AMD_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST             RT_BIT(7)
    68 /** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
    69 #define AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER              RT_BIT(10)
    70 /** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
    71  *  intercept filter cycle count threshold. */
    72 #define AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD    RT_BIT(12)
    73 /** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
    74 #define AMD_CPUID_SVM_FEATURE_EDX_AVIC                      RT_BIT(13)
    75 /** @} */
    7647
    7748/** @name SVM generic / convenient defines.
    … …  
    326297/** @} */
    327298
     299/** @name SVMVMCB.u64ExitInfo1 for Mov CRX accesses.
     300 * @{
     301 */
     302/** The access was via Mov CRx instruction bit number. */
     303#define SVM_EXIT1_MOV_CRX_MASK                RT_BIT_64(63)
     304/** @} */
     305
    328306
    329307/** @name SVMVMCB.ctrl.u64InterceptCtrl
    … …  
    601579        uint32_t    u1OP16              : 1;   /**< Bit 5: 16-bit operand. */
    602580        uint32_t    u1OP32              : 1;   /**< Bit 6: 32-bit operand. */
    603         uint32_t    u1ADDR16            : 1;   /**< Bit 7: 16-bit operand. */
    604         uint32_t    u1ADDR32            : 1;   /**< Bit 8: 32-bit operand. */
    605         uint32_t    u1ADDR64            : 1;   /**< Bit 9: 64-bit operand. */
     581        uint32_t    u1ADDR16            : 1;   /**< Bit 7: 16-bit address size. */
     582        uint32_t    u1ADDR32            : 1;   /**< Bit 8: 32-bit address size. */
     583        uint32_t    u1ADDR64            : 1;   /**< Bit 9: 64-bit address size. */
    606584        uint32_t    u3SEG               : 3;   /**< BITS 12:10: Effective segment number. Added w/ decode assist in APM v3.17. */
    607585        uint32_t    u3Reserved          : 3;
    … …  
    615593typedef const SVMIOIOEXITINFO *PCSVMIOIOEXITINFO;
    616594
    617 /** @name SVMIOIOEXITINFO.u1Type
    618  *  @{ */
     595/** 8-bit IO transfer. */
     596#define SVM_IOIO_8_BIT_OP               RT_BIT_32(4)
     597/** 16-bit IO transfer. */
     598#define SVM_IOIO_16_BIT_OP              RT_BIT_32(5)
     599/** 32-bit IO transfer. */
     600#define SVM_IOIO_32_BIT_OP              RT_BIT_32(6)
     601/** Mask of all possible IO transfer sizes. */
     602#define SVM_IOIO_OP_SIZE_MASK           (SVM_IOIO_8_BIT_OP | SVM_IOIO_16_BIT_OP | SVM_IOIO_32_BIT_OP)
     603/** 16-bit address for the IO buffer. */
     604#define SVM_IOIO_16_BIT_ADDR            RT_BIT_32(7)
     605/** 32-bit address for the IO buffer. */
     606#define SVM_IOIO_32_BIT_ADDR            RT_BIT_32(8)
     607/** 64-bit address for the IO buffer. */
     608#define SVM_IOIO_64_BIT_ADDR            RT_BIT_32(9)
     609/** Mask of all the IO address sizes. */
     610#define SVM_IOIO_ADDR_SIZE_MASK         (SVM_IOIO_16_BIT_ADDR | SVM_IOIO_32_BIT_ADDR | SVM_IOIO_64_BIT_ADDR)
     611/** Number of bits to left shift to get the IO port number. */
     612#define SVM_IOIO_PORT_SHIFT             16
    619613/** IO write. */
    620614#define SVM_IOIO_WRITE                  0
    621615/** IO read. */
    622616#define SVM_IOIO_READ                   1
     617/**
     618 * SVM IOIO transfer type.
     619 */
     620typedef enum
     621{
     622    SVMIOIOTYPE_OUT = SVM_IOIO_WRITE,
     623    SVMIOIOTYPE_IN  = SVM_IOIO_READ
     624} SVMIOIOTYPE;
    623625/** @}*/
    624626

  • trunk/include/VBox/vmm/iem.h

    r66000 r66581  
    4747#define IEMMODE_64BIT 2
    4848/** @} */
     49
     50
     51/** @name IEM_XCPT_FLAGS_XXX - flags for iemRaiseXcptOrInt.
     52 * @{ */
     53/** CPU exception. */
     54#define IEM_XCPT_FLAGS_T_CPU_XCPT       RT_BIT_32(0)
     55/** External interrupt (from PIC, APIC, whatever). */
     56#define IEM_XCPT_FLAGS_T_EXT_INT        RT_BIT_32(1)
     57/** Software interrupt (int or into, not bound).
     58 * Returns to the following instruction */
     59#define IEM_XCPT_FLAGS_T_SOFT_INT       RT_BIT_32(2)
     60/** Takes an error code. */
     61#define IEM_XCPT_FLAGS_ERR              RT_BIT_32(3)
     62/** Takes a CR2. */
     63#define IEM_XCPT_FLAGS_CR2              RT_BIT_32(4)
     64/** Generated by the breakpoint instruction. */
     65#define IEM_XCPT_FLAGS_BP_INSTR         RT_BIT_32(5)
     66/** Generated by a DRx instruction breakpoint and RF should be cleared. */
     67#define IEM_XCPT_FLAGS_DRx_INSTR_BP     RT_BIT_32(6)
     68/** @}  */
    4969
    5070
    … …  
    117137VMM_INT_DECL(void)          IEMTlbInvalidatePage(PVMCPU pVCpu, RTGCPTR GCPtr);
    118138VMM_INT_DECL(void)          IEMTlbInvalidateAllPhysical(PVMCPU pVCpu);
    119 #ifdef VBOX_WITH_NESTED_HWVIRT
    120 VMM_INT_DECL(bool)          IEMIsRaisingIntOrXcpt(PVMCPU pVCpu);
    121 #endif
     139VMM_INT_DECL(bool)          IEMGetCurrentXcpt(PVMCPU pVCpu, uint8_t *puVector, uint32_t *pfFlags, uint32_t *puErr,
     140                                              uint64_t *puCr2);
    122141
    123142/** @name Given Instruction Interpreters

  • trunk/include/iprt/x86.h

    r66392 r66581  
    739739/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
    740740#define X86_CPUID_AMD_ADVPOWER_EDX_PA        RT_BIT_32(12)
     741/** @} */
     742
     743
     744/** @name CPUID AMD SVM Feature information.
     745 * CPUID query with EAX=0x8000000a.
     746 * @{
     747 */
     748/** Bit 0 - NP - Nested Paging supported. */
     749#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING             RT_BIT(0)
     750/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
     751#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT                  RT_BIT(1)
     752/** Bit 2 - SVML - SVM locking bit supported. */
     753#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK                  RT_BIT(2)
     754/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
     755#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE                 RT_BIT(3)
     756/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
     757#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR              RT_BIT(4)
     758/** Bit 5 - VmcbClean - Support VMCB clean bits. */
     759#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN                RT_BIT(5)
     760/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
     761 *  VMCB.TLB_Control is supported. */
     762#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID             RT_BIT(6)
     763/** Bit 7 - DecodeAssist - Indicate decode assist is supported. */
     764#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST             RT_BIT(7)
     765/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
     766#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER              RT_BIT(10)
     767/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
     768 *  intercept filter cycle count threshold. */
     769#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD    RT_BIT(12)
     770/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
     771#define X86_CPUID_SVM_FEATURE_EDX_AVIC                      RT_BIT(13)
    741772/** @} */
    742773
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