Index: /trunk/include/VBox/disopcode.h
===================================================================
--- /trunk/include/VBox/disopcode.h	(revision 66811)
+++ /trunk/include/VBox/disopcode.h	(revision 66812)
@@ -1064,18 +1064,30 @@
 
 /* For making IEM / bs3-cpu-generated-1 happy: */
+#define OP_PARM_M_RO            OP_PARM_M               /**< Annotates read only memory of variable operand size (xrstor). */
+#define OP_PARM_M_RW            OP_PARM_M               /**< Annotates read-write memory of variable operand size (xsave). */
+#define OP_PARM_Mb_RO           OP_PARM_Mb              /**< Annotates read only memory byte operand. */
+#define OP_PARM_Md_RO           OP_PARM_Md              /**< Annotates read only memory byte operand. */
+#define OP_PARM_Md_WO           OP_PARM_Md              /**< Annotates write only memory byte operand. */
+#define OP_PARM_Mq_WO           OP_PARM_Mq              /**< Annotates write only memory quad word operand. */
+#define OP_PARM_Pq_WO           OP_PARM_Pq              /**< Annotates write only operand. */
+#define OP_PARM_Nq              OP_PARM_Qq              /**< Missing 'N' class (MMX reg selected by modrm.mem) in disasm. */
 #define OP_PARM_Uq              (OP_PARM_U+OP_PARM_q)
 #define OP_PARM_UqHi            (OP_PARM_U+OP_PARM_dq)
-#define OP_PARM_WqZxReg         OP_PARM_Wq              /**< Annotates that register targets get their upper bits cleared. */
-#define OP_PARM_VssZxReg        OP_PARM_Vss             /**< Annotates that register targets get their upper bits cleared. */
-#define OP_PARM_VsdZxReg        OP_PARM_Vsd             /**< Annotates that register targets get their upper bits cleared. */
+#define OP_PARM_Vdq_WO          OP_PARM_Vdq             /**< Annotates that only YMM/XMM[127:64] are accessed. */
+#define OP_PARM_Vpd_WO          OP_PARM_Vpd             /**< Annotates write only operand. */
+#define OP_PARM_Vps_WO          OP_PARM_Vps             /**< Annotates write only operand. */
+#define OP_PARM_Vq_WO           OP_PARM_Vq              /**< Annotates write only operand. */
 #define OP_PARM_VqHi            OP_PARM_Vdq             /**< Annotates that only YMM/XMM[127:64] are accessed. */
-#define OP_PARM_VqZxReg         OP_PARM_Vq              /**< Annotates that register targets get their upper bits cleared */
-#define OP_PARM_MbRO            OP_PARM_Mb              /**< Annotates read only memory byte operand. */
-#define OP_PARM_MdRO            OP_PARM_Md              /**< Annotates read only memory byte operand. */
-#define OP_PARM_MdWO            OP_PARM_Md              /**< Annotates write only memory byte operand. */
-#define OP_PARM_MqWO            OP_PARM_Mq              /**< Annotates write only memory quad word operand. */
-#define OP_PARM_MRO             OP_PARM_M               /**< Annotates read only memory of variable operand size (xrstor). */
-#define OP_PARM_MRW             OP_PARM_M               /**< Annotates read-write memory of variable operand size (xsave). */
-#define OP_PARM_Nq              OP_PARM_Qq              /**< Missing 'N' class (MMX reg selected by modrm.mem) in disasm. */
+#define OP_PARM_VqHi_WO         OP_PARM_Vdq             /**< Annotates that only YMM/XMM[127:64] are written. */
+#define OP_PARM_VqZxReg_WO      OP_PARM_Vq              /**< Annotates that register targets get their upper bits cleared */
+#define OP_PARM_VsdZxReg_WO     OP_PARM_Vsd             /**< Annotates that register targets get their upper bits cleared. */
+#define OP_PARM_VsdZxReg_WO     OP_PARM_Vsd             /**< Annotates that register targets get their upper bits cleared. */
+#define OP_PARM_VssZxReg_WO     OP_PARM_Vss             /**< Annotates that register targets get their upper bits cleared. */
+#define OP_PARM_Wpd_WO          OP_PARM_Wpd             /**< Annotates write only operand. */
+#define OP_PARM_Wps_WO          OP_PARM_Wps             /**< Annotates write only operand. */
+#define OP_PARM_WqZxReg_WO      OP_PARM_Wq              /**< Annotates that register targets get their upper bits cleared. */
+#define OP_PARM_Wss_WO          OP_PARM_Wss             /**< Annotates write only operand. */
+#define OP_PARM_Wsd_WO          OP_PARM_Wsd             /**< Annotates write only operand. */
+
 
 /** @} */
Index: /trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsPython.py
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsPython.py	(revision 66811)
+++ /trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsPython.py	(revision 66812)
@@ -210,83 +210,92 @@
 g_kdOpTypes = {
     # Fixed addresses
-    'Ap':   ( 'IDX_ParseImmAddrF',  'imm',    '%Ap',  'Ap',      ),
+    'Ap':           ( 'IDX_ParseImmAddrF',  'imm',    '%Ap',  'Ap',      ),
 
     # ModR/M.rm
-    'Eb':   ( 'IDX_UseModRM',       'rm',     '%Eb',  'Eb',      ),
-    'Ew':   ( 'IDX_UseModRM',       'rm',     '%Ew',  'Ew',      ),
-    'Ev':   ( 'IDX_UseModRM',       'rm',     '%Ev',  'Ev',      ),
-    'Wss':  ( 'IDX_UseModRM',       'rm',     '%Wss', 'Wss',     ),
-    'Wsd':  ( 'IDX_UseModRM',       'rm',     '%Wsd', 'Wsd',     ),
-    'Wps':  ( 'IDX_UseModRM',       'rm',     '%Wps', 'Wps',     ),
-    'Wpd':  ( 'IDX_UseModRM',       'rm',     '%Wpd', 'Wpd',     ),
-    'Wdq':  ( 'IDX_UseModRM',       'rm',     '%Wdq', 'Wdq',     ),
-    'Wq':   ( 'IDX_UseModRM',       'rm',     '%Wq',  'Wq',      ),
-    'WqZxReg': ( 'IDX_UseModRM',    'rm',     '%Wq',  'Wq',      ),
+    'Eb':           ( 'IDX_UseModRM',       'rm',     '%Eb',  'Eb',      ),
+    'Ew':           ( 'IDX_UseModRM',       'rm',     '%Ew',  'Ew',      ),
+    'Ev':           ( 'IDX_UseModRM',       'rm',     '%Ev',  'Ev',      ),
+    'Wss':          ( 'IDX_UseModRM',       'rm',     '%Wss', 'Wss',     ),
+    'Wss_WO':       ( 'IDX_UseModRM',       'rm',     '%Wss', 'Wss',     ),
+    'Wsd':          ( 'IDX_UseModRM',       'rm',     '%Wsd', 'Wsd',     ),
+    'Wsd_WO':       ( 'IDX_UseModRM',       'rm',     '%Wsd', 'Wsd',     ),
+    'Wps':          ( 'IDX_UseModRM',       'rm',     '%Wps', 'Wps',     ),
+    'Wps_WO':       ( 'IDX_UseModRM',       'rm',     '%Wps', 'Wps',     ),
+    'Wpd':          ( 'IDX_UseModRM',       'rm',     '%Wpd', 'Wpd',     ),
+    'Wpd_WO':       ( 'IDX_UseModRM',       'rm',     '%Wpd', 'Wpd',     ),
+    'Wdq':          ( 'IDX_UseModRM',       'rm',     '%Wdq', 'Wdq',     ),
+    'Wdq_WO':       ( 'IDX_UseModRM',       'rm',     '%Wdq', 'Wdq',     ),
+    'Wq':           ( 'IDX_UseModRM',       'rm',     '%Wq',  'Wq',      ),
+    'WqZxReg_WO':   ( 'IDX_UseModRM',       'rm',     '%Wq',  'Wq',      ),
 
     # ModR/M.rm - register only.
-    'Uq':   ( 'IDX_UseModRM',       'rm',     '%Uq',  'Uq',      ),
-    'UqHi': ( 'IDX_UseModRM',       'rm',     '%Uq',  'UqHi',    ),
-    'Nq':   ( 'IDX_UseModRM',       'rm',     '%Qq',  'Nq',      ),
+    'Uq':           ( 'IDX_UseModRM',       'rm',     '%Uq',  'Uq',      ),
+    'UqHi':         ( 'IDX_UseModRM',       'rm',     '%Uq',  'UqHi',    ),
+    'Nq':           ( 'IDX_UseModRM',       'rm',     '%Qq',  'Nq',      ),
 
     # ModR/M.rm - memory only.
-    'Ma':   ( 'IDX_UseModRM',       'rm',     '%Ma',  'Ma',      ), ##< Only used by BOUND.
-    'MbRO': ( 'IDX_UseModRM',       'rm',     '%Mb',  'Mb',      ),
-    'MdRO': ( 'IDX_UseModRM',       'rm',     '%Md',  'Md',      ),
-    'MdWO': ( 'IDX_UseModRM',       'rm',     '%Md',  'Md',      ),
-    'Mq':   ( 'IDX_UseModRM',       'rm',     '%Mq',  'Mq',      ),
-    'MqWO': ( 'IDX_UseModRM',       'rm',     '%Mq',  'Mq',      ),
-    'MRO':  ( 'IDX_UseModRM',       'rm',     '%M',   'M',       ),
-    'MRW':  ( 'IDX_UseModRM',       'rm',     '%M',   'M',       ),
+    'Ma':           ( 'IDX_UseModRM',       'rm',     '%Ma',  'Ma',      ), ##< Only used by BOUND.
+    'Mb_RO':        ( 'IDX_UseModRM',       'rm',     '%Mb',  'Mb',      ),
+    'Md_RO':        ( 'IDX_UseModRM',       'rm',     '%Md',  'Md',      ),
+    'Md_WO':        ( 'IDX_UseModRM',       'rm',     '%Md',  'Md',      ),
+    'Mq':           ( 'IDX_UseModRM',       'rm',     '%Mq',  'Mq',      ),
+    'Mq_WO':        ( 'IDX_UseModRM',       'rm',     '%Mq',  'Mq',      ),
+    'M_RO':         ( 'IDX_UseModRM',       'rm',     '%M',   'M',       ),
+    'M_RW':         ( 'IDX_UseModRM',       'rm',     '%M',   'M',       ),
 
     # ModR/M.reg
-    'Gb':   ( 'IDX_UseModRM',       'reg',    '%Gb',  'Gb',      ),
-    'Gw':   ( 'IDX_UseModRM',       'reg',    '%Gw',  'Gw',      ),
-    'Gv':   ( 'IDX_UseModRM',       'reg',    '%Gv',  'Gv',      ),
-    'Pq':   ( 'IDX_UseModRM',       'reg',    '%Pq',  'Pq',      ),
-    'Vss':  ( 'IDX_UseModRM',       'reg',    '%Vss', 'Vss',     ),
-    'VssZxReg': ( 'IDX_UseModRM',   'reg',    '%Vss', 'Vss',     ),
-    'Vsd':  ( 'IDX_UseModRM',       'reg',    '%Vsd', 'Vsd',     ),
-    'VsdZxReg': ( 'IDX_UseModRM',   'reg',    '%Vsd', 'Vsd',     ),
-    'Vps':  ( 'IDX_UseModRM',       'reg',    '%Vps', 'Vps',     ),
-    'Vpd':  ( 'IDX_UseModRM',       'reg',    '%Vpd', 'Vpd',     ),
-    'Vq':   ( 'IDX_UseModRM',       'reg',    '%Vq',  'Vq',      ),
-    'Vdq':  ( 'IDX_UseModRM',       'reg',    '%Vdq', 'Vdq',     ),
-    'VqHi': ( 'IDX_UseModRM',       'reg',    '%Vdq', 'VdqHi',   ),
-    'VqZxReg': ( 'IDX_UseModRM',    'reg',    '%Vq',  'VqZx',   ),
+    'Gb':           ( 'IDX_UseModRM',       'reg',    '%Gb',  'Gb',      ),
+    'Gw':           ( 'IDX_UseModRM',       'reg',    '%Gw',  'Gw',      ),
+    'Gv':           ( 'IDX_UseModRM',       'reg',    '%Gv',  'Gv',      ),
+    'Pq_WO':        ( 'IDX_UseModRM',       'reg',    '%Pq',  'Pq',      ),
+    'Vss':          ( 'IDX_UseModRM',       'reg',    '%Vss', 'Vss',     ),
+    'VssZxReg_WO':  ( 'IDX_UseModRM',       'reg',    '%Vss', 'Vss',     ),
+    'Vsd':          ( 'IDX_UseModRM',       'reg',    '%Vsd', 'Vsd',     ),
+    'VsdZxReg_WO':  ( 'IDX_UseModRM',       'reg',    '%Vsd', 'Vsd',     ),
+    'Vps':          ( 'IDX_UseModRM',       'reg',    '%Vps', 'Vps',     ),
+    'Vps_WO':       ( 'IDX_UseModRM',       'reg',    '%Vps', 'Vps',     ),
+    'Vpd':          ( 'IDX_UseModRM',       'reg',    '%Vpd', 'Vpd',     ),
+    'Vpd_WO':       ( 'IDX_UseModRM',       'reg',    '%Vpd', 'Vpd',     ),
+    'Vq':           ( 'IDX_UseModRM',       'reg',    '%Vq',  'Vq',      ),
+    'Vq_WO':        ( 'IDX_UseModRM',       'reg',    '%Vq',  'Vq',      ),
+    'Vdq_WO':       ( 'IDX_UseModRM',       'reg',    '%Vdq', 'Vdq',     ),
+    'VqHi':         ( 'IDX_UseModRM',       'reg',    '%Vdq', 'VdqHi',   ),
+    'VqHi_WO':      ( 'IDX_UseModRM',       'reg',    '%Vdq', 'VdqHi',   ),
+    'VqZxReg_WO':   ( 'IDX_UseModRM',       'reg',    '%Vq',  'VqZx',    ),
 
     # Immediate values.
-    'Ib':   ( 'IDX_ParseImmByte',   'imm',    '%Ib',  'Ib',      ), ##< NB! Could be IDX_ParseImmByteSX for some instructions.
-    'Iw':   ( 'IDX_ParseImmUshort', 'imm',    '%Iw',  'Iw',      ),
-    'Id':   ( 'IDX_ParseImmUlong',  'imm',    '%Id',  'Id',      ),
-    'Iq':   ( 'IDX_ParseImmQword',  'imm',    '%Iq',  'Iq',      ),
-    'Iv':   ( 'IDX_ParseImmV',      'imm',    '%Iv',  'Iv',      ), ##< o16: word, o32: dword, o64: qword
-    'Iz':   ( 'IDX_ParseImmZ',      'imm',    '%Iz',  'Iz',      ), ##< o16: word, o32|o64:dword
+    'Ib':           ( 'IDX_ParseImmByte',   'imm',    '%Ib',  'Ib',      ), ##< NB! Could be IDX_ParseImmByteSX for some instrs.
+    'Iw':           ( 'IDX_ParseImmUshort', 'imm',    '%Iw',  'Iw',      ),
+    'Id':           ( 'IDX_ParseImmUlong',  'imm',    '%Id',  'Id',      ),
+    'Iq':           ( 'IDX_ParseImmQword',  'imm',    '%Iq',  'Iq',      ),
+    'Iv':           ( 'IDX_ParseImmV',      'imm',    '%Iv',  'Iv',      ), ##< o16: word, o32: dword, o64: qword
+    'Iz':           ( 'IDX_ParseImmZ',      'imm',    '%Iz',  'Iz',      ), ##< o16: word, o32|o64:dword
 
     # Address operands (no ModR/M).
-    'Ob':   ( 'IDX_ParseImmAddr',   'imm',    '%Ob',  'Ob',      ),
-    'Ov':   ( 'IDX_ParseImmAddr',   'imm',    '%Ov',  'Ov',      ),
+    'Ob':           ( 'IDX_ParseImmAddr',   'imm',    '%Ob',  'Ob',      ),
+    'Ov':           ( 'IDX_ParseImmAddr',   'imm',    '%Ov',  'Ov',      ),
 
     # Relative jump targets
-    'Jb':   ( 'IDX_ParseImmBRel',   'imm',    '%Jb',  'Jb',      ),
-    'Jv':   ( 'IDX_ParseImmVRel',   'imm',    '%Jv',  'Jv',      ),
+    'Jb':           ( 'IDX_ParseImmBRel',   'imm',    '%Jb',  'Jb',      ),
+    'Jv':           ( 'IDX_ParseImmVRel',   'imm',    '%Jv',  'Jv',      ),
 
     # DS:rSI
-    'Xb':   ( 'IDX_ParseXb',        'rSI',    '%eSI', 'Xb',      ),
-    'Xv':   ( 'IDX_ParseXv',        'rSI',    '%eSI', 'Xv',      ),
+    'Xb':           ( 'IDX_ParseXb',        'rSI',    '%eSI', 'Xb',      ),
+    'Xv':           ( 'IDX_ParseXv',        'rSI',    '%eSI', 'Xv',      ),
     # ES:rDI
-    'Yb':   ( 'IDX_ParseYb',        'rDI',    '%eDI', 'Yb',      ),
-    'Yv':   ( 'IDX_ParseYv',        'rDI',    '%eDI', 'Yv',      ),
-
-    'Fv':   ( 'IDX_ParseFixedReg',  'rFLAGS', '%Fv',  'Fv',      ),
+    'Yb':           ( 'IDX_ParseYb',        'rDI',    '%eDI', 'Yb',      ),
+    'Yv':           ( 'IDX_ParseYv',        'rDI',    '%eDI', 'Yv',      ),
+
+    'Fv':           ( 'IDX_ParseFixedReg',  'rFLAGS', '%Fv',  'Fv',      ),
 
     # Fixed registers.
-    'AL':   ( 'IDX_ParseFixedReg',  'AL',     'al',   'REG_AL',  ),
-    'rAX':  ( 'IDX_ParseFixedReg',  'rAX',    '%eAX', 'REG_EAX', ),
-    'CS':   ( 'IDX_ParseFixedReg',  'CS',     'cs',   'REG_CS',  ), # 8086: push CS
-    'DS':   ( 'IDX_ParseFixedReg',  'DS',     'ds',   'REG_DS',  ),
-    'ES':   ( 'IDX_ParseFixedReg',  'ES',     'es',   'REG_ES',  ),
-    'FS':   ( 'IDX_ParseFixedReg',  'FS',     'fs',   'REG_FS',  ),
-    'GS':   ( 'IDX_ParseFixedReg',  'GS',     'gs',   'REG_GS',  ),
-    'SS':   ( 'IDX_ParseFixedReg',  'SS',     'ss',   'REG_SS',  ),
+    'AL':           ( 'IDX_ParseFixedReg',  'AL',     'al',   'REG_AL',  ),
+    'rAX':          ( 'IDX_ParseFixedReg',  'rAX',    '%eAX', 'REG_EAX', ),
+    'CS':           ( 'IDX_ParseFixedReg',  'CS',     'cs',   'REG_CS',  ), # 8086: push CS
+    'DS':           ( 'IDX_ParseFixedReg',  'DS',     'ds',   'REG_DS',  ),
+    'ES':           ( 'IDX_ParseFixedReg',  'ES',     'es',   'REG_ES',  ),
+    'FS':           ( 'IDX_ParseFixedReg',  'FS',     'fs',   'REG_FS',  ),
+    'GS':           ( 'IDX_ParseFixedReg',  'GS',     'gs',   'REG_GS',  ),
+    'SS':           ( 'IDX_ParseFixedReg',  'SS',     'ss',   'REG_SS',  ),
 };
 
Index: /trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h	(revision 66811)
+++ /trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h	(revision 66812)
@@ -1001,5 +1001,5 @@
 FNIEMOP_DEF(iemOp_movups_Vps_Wps)
 {
-    IEMOP_MNEMONIC2(RM, MOVUPS, movups, Vps, Wps, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
+    IEMOP_MNEMONIC2(RM, MOVUPS, movups, Vps_WO, Wps, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
     uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
     if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
@@ -1053,5 +1053,5 @@
 FNIEMOP_DEF(iemOp_movupd_Vpd_Wpd)
 {
-    IEMOP_MNEMONIC2(RM, MOVUPD, movupd, Vpd, Wpd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
+    IEMOP_MNEMONIC2(RM, MOVUPD, movupd, Vpd_WO, Wpd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
     uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
     if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
@@ -1104,5 +1104,5 @@
 FNIEMOP_DEF(iemOp_movss_Vss_Wss)
 {
-    IEMOP_MNEMONIC2(RM, MOVSS, movss, VssZxReg, Wss, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
+    IEMOP_MNEMONIC2(RM, MOVSS, movss, VssZxReg_WO, Wss, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
     uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
     if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
@@ -1158,5 +1158,5 @@
 FNIEMOP_DEF(iemOp_movsd_Vsd_Wsd)
 {
-    IEMOP_MNEMONIC2(RM, MOVSD, movsd, VsdZxReg, Wsd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
+    IEMOP_MNEMONIC2(RM, MOVSD, movsd, VsdZxReg_WO, Wsd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
     uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
     if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
@@ -1212,5 +1212,5 @@
 FNIEMOP_DEF(iemOp_movups_Wps_Vps)
 {
-    IEMOP_MNEMONIC2(MR, MOVUPS, movups, Wps, Vps, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
+    IEMOP_MNEMONIC2(MR, MOVUPS, movups, Wps_WO, Vps, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
     uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
     if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
@@ -1263,5 +1263,5 @@
 FNIEMOP_DEF(iemOp_movupd_Wpd_Vpd)
 {
-    IEMOP_MNEMONIC2(MR, MOVUPD, movupd, Wpd, Vpd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
+    IEMOP_MNEMONIC2(MR, MOVUPD, movupd, Wpd_WO, Vpd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
     uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
     if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
@@ -1314,5 +1314,5 @@
 FNIEMOP_DEF(iemOp_movss_Wss_Vss)
 {
-    IEMOP_MNEMONIC2(MR, MOVSS, movss, Wss, Vss, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
+    IEMOP_MNEMONIC2(MR, MOVSS, movss, Wss_WO, Vss, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
     uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
     if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
@@ -1368,5 +1368,5 @@
 FNIEMOP_DEF(iemOp_movsd_Wsd_Vsd)
 {
-    IEMOP_MNEMONIC2(MR, MOVSD, movsd, Wsd, Vsd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
+    IEMOP_MNEMONIC2(MR, MOVSD, movsd, Wsd_WO, Vsd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
     uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
     if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
@@ -1426,5 +1426,5 @@
          * @optest      op1=0 op2=-42 -> op1=-42
          */
-        IEMOP_MNEMONIC2(RM_REG, MOVHLPS, movhlps, Vq, UqHi, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
+        IEMOP_MNEMONIC2(RM_REG, MOVHLPS, movhlps, Vq_WO, UqHi, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
 
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -1454,5 +1454,5 @@
          * @opfunction  iemOp_movlps_Vq_Mq__vmovhlps
          */
-        IEMOP_MNEMONIC2(RM_MEM, MOVLPS, movlps, Vq, Mq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
+        IEMOP_MNEMONIC2(RM_MEM, MOVLPS, movlps, Vq_WO, Mq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
 
         IEM_MC_BEGIN(0, 2);
@@ -1490,5 +1490,5 @@
     if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
     {
-        IEMOP_MNEMONIC2(RM_MEM, MOVLPD, movlpd, Vq, Mq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
+        IEMOP_MNEMONIC2(RM_MEM, MOVLPD, movlpd, Vq_WO, Mq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
 
         IEM_MC_BEGIN(0, 2);
@@ -1534,5 +1534,5 @@
 FNIEMOP_DEF(iemOp_movsldup_Vdq_Wdq)
 {
-    IEMOP_MNEMONIC2(RM, MOVSLDUP, movsldup, Vdq, Wdq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
+    IEMOP_MNEMONIC2(RM, MOVSLDUP, movsldup, Vdq_WO, Wdq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
     uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
     if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
@@ -1594,5 +1594,5 @@
 FNIEMOP_DEF(iemOp_movddup_Vdq_Wdq)
 {
-    IEMOP_MNEMONIC2(RM, MOVDDUP, movddup, Vdq, Wdq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
+    IEMOP_MNEMONIC2(RM, MOVDDUP, movddup, Vdq_WO, Wdq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
     uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
     if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
@@ -1657,5 +1657,5 @@
     if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
     {
-        IEMOP_MNEMONIC2(MR_MEM, MOVLPS, movlps, MqWO, Vq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
+        IEMOP_MNEMONIC2(MR_MEM, MOVLPS, movlps, Mq_WO, Vq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
 
         IEM_MC_BEGIN(0, 2);
@@ -1705,5 +1705,5 @@
     if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
     {
-        IEMOP_MNEMONIC2(MR_MEM, MOVLPD, movlpd, MqWO, Vq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
+        IEMOP_MNEMONIC2(MR_MEM, MOVLPD, movlpd, Mq_WO, Vq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
         IEM_MC_BEGIN(0, 2);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
@@ -1826,5 +1826,5 @@
          * @optest      op1=0 op2=-42 -> op1=-42
          */
-        IEMOP_MNEMONIC2(RM_REG, MOVLHPS, movlhps, VqHi, Uq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
+        IEMOP_MNEMONIC2(RM_REG, MOVLHPS, movlhps, VqHi_WO, Uq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
 
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
@@ -1854,5 +1854,5 @@
          * @opfunction  iemOp_movhps_Vdq_Mq__movlhps_Vdq_Uq
          */
-        IEMOP_MNEMONIC2(RM_MEM, MOVHPS, movhps, VqHi, Mq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
+        IEMOP_MNEMONIC2(RM_MEM, MOVHPS, movhps, VqHi_WO, Mq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
 
         IEM_MC_BEGIN(0, 2);
@@ -1890,5 +1890,5 @@
     if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
     {
-        IEMOP_MNEMONIC2(RM_MEM, MOVHPD, movhpd, VqHi, Mq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
+        IEMOP_MNEMONIC2(RM_MEM, MOVHPD, movhpd, VqHi_WO, Mq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
         IEM_MC_BEGIN(0, 2);
         IEM_MC_LOCAL(uint64_t,                  uSrc);
@@ -1933,5 +1933,5 @@
 FNIEMOP_DEF(iemOp_movshdup_Vdq_Wdq)
 {
-    IEMOP_MNEMONIC2(RM, MOVSHDUP, movshdup, Vdq, Wdq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
+    IEMOP_MNEMONIC2(RM, MOVSHDUP, movshdup, Vdq_WO, Wdq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
     uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
     if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
@@ -2008,5 +2008,5 @@
     if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
     {
-        IEMOP_MNEMONIC2(MR_MEM, MOVHPS, movhps, MqWO, VqHi, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
+        IEMOP_MNEMONIC2(MR_MEM, MOVHPS, movhps, Mq_WO, VqHi, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
 
         IEM_MC_BEGIN(0, 2);
@@ -2056,5 +2056,5 @@
     if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
     {
-        IEMOP_MNEMONIC2(MR_MEM, MOVHPD, movhpd, MqWO, VqHi, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
+        IEMOP_MNEMONIC2(MR_MEM, MOVHPD, movhpd, Mq_WO, VqHi, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
 
         IEM_MC_BEGIN(0, 2);
@@ -4325,5 +4325,5 @@
 FNIEMOP_DEF(iemOp_movq_Vq_Wq)
 {
-    IEMOP_MNEMONIC2(RM, MOVQ, movq, VqZxReg, Wq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
+    IEMOP_MNEMONIC2(RM, MOVQ, movq, VqZxReg_WO, Wq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
     uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
     if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
@@ -6453,5 +6453,5 @@
 FNIEMOP_DEF_1(iemOp_Grp15_ldmxcsr, uint8_t, bRm)
 {
-    IEMOP_MNEMONIC1(M_MEM, LDMXCSR, ldmxcsr, MdRO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
+    IEMOP_MNEMONIC1(M_MEM, LDMXCSR, ldmxcsr, Md_RO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
     if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse)
         return IEMOP_RAISE_INVALID_OPCODE();
@@ -6490,5 +6490,5 @@
 FNIEMOP_DEF_1(iemOp_Grp15_stmxcsr,  uint8_t, bRm)
 {
-    IEMOP_MNEMONIC1(M_MEM, STMXCSR, stmxcsr, MdWO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
+    IEMOP_MNEMONIC1(M_MEM, STMXCSR, stmxcsr, Md_WO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
     if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse)
         return IEMOP_RAISE_INVALID_OPCODE();
@@ -6517,5 +6517,5 @@
 FNIEMOP_DEF_1(iemOp_Grp15_xsave,    uint8_t, bRm)
 {
-    IEMOP_MNEMONIC1(M_MEM, XSAVE, xsave, MRW, DISOPTYPE_HARMLESS, 0);
+    IEMOP_MNEMONIC1(M_MEM, XSAVE, xsave, M_RW, DISOPTYPE_HARMLESS, 0);
     if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fXSaveRstor)
         return IEMOP_RAISE_INVALID_OPCODE();
@@ -6545,5 +6545,5 @@
 FNIEMOP_DEF_1(iemOp_Grp15_xrstor,   uint8_t, bRm)
 {
-    IEMOP_MNEMONIC1(M_MEM, XRSTOR, xrstor, MRO, DISOPTYPE_HARMLESS, 0);
+    IEMOP_MNEMONIC1(M_MEM, XRSTOR, xrstor, M_RO, DISOPTYPE_HARMLESS, 0);
     if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fXSaveRstor)
         return IEMOP_RAISE_INVALID_OPCODE();
@@ -6575,5 +6575,5 @@
 FNIEMOP_DEF_1(iemOp_Grp15_clflush,  uint8_t, bRm)
 {
-    IEMOP_MNEMONIC1(M_MEM, CLFLUSH, clflush, MbRO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
+    IEMOP_MNEMONIC1(M_MEM, CLFLUSH, clflush, Mb_RO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
     if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fClFlush)
         return FNIEMOP_CALL_1(iemOp_InvalidWithRMAllNeeded, bRm);
@@ -6600,5 +6600,5 @@
 FNIEMOP_DEF_1(iemOp_Grp15_clflushopt,  uint8_t, bRm)
 {
-    IEMOP_MNEMONIC1(M_MEM, CLFLUSHOPT, clflushopt, MbRO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
+    IEMOP_MNEMONIC1(M_MEM, CLFLUSHOPT, clflushopt, Mb_RO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
     if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fClFlushOpt)
         return FNIEMOP_CALL_1(iemOp_InvalidWithRMAllNeeded, bRm);
@@ -8341,5 +8341,5 @@
 FNIEMOP_DEF(iemOp_movq_Wq_Vq)
 {
-    IEMOP_MNEMONIC2(MR, MOVQ, movq, WqZxReg, Vq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
+    IEMOP_MNEMONIC2(MR, MOVQ, movq, WqZxReg_WO, Vq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
     uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
     if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
@@ -8402,5 +8402,5 @@
          * Register, register.
          */
-        IEMOP_MNEMONIC2(RM_REG, MOVQ2DQ, movq2dq, VqZxReg, Nq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
+        IEMOP_MNEMONIC2(RM_REG, MOVQ2DQ, movq2dq, VqZxReg_WO, Nq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_BEGIN(0, 1);
@@ -8454,5 +8454,5 @@
          * Register, register.
          */
-        IEMOP_MNEMONIC2(RM_REG, MOVDQ2Q, movdq2q, Pq, Uq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
+        IEMOP_MNEMONIC2(RM_REG, MOVDQ2Q, movdq2q, Pq_WO, Uq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
         IEM_MC_BEGIN(0, 1);
Index: /trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap1.cpp.h
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap1.cpp.h	(revision 66811)
+++ /trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap1.cpp.h	(revision 66812)
@@ -2227,5 +2227,5 @@
 FNIEMOP_DEF_1(iemOp_VGrp15_vstmxcsr,  uint8_t, bRm)
 {
-    IEMOP_MNEMONIC1(VEX_M_MEM, VSTMXCSR, vstmxcsr, MdWO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
+    IEMOP_MNEMONIC1(VEX_M_MEM, VSTMXCSR, vstmxcsr, Md_WO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
     if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx)
         return IEMOP_RAISE_INVALID_OPCODE();
Index: /trunk/src/VBox/ValidationKit/bootsectors/Config.kmk
===================================================================
--- /trunk/src/VBox/ValidationKit/bootsectors/Config.kmk	(revision 66811)
+++ /trunk/src/VBox/ValidationKit/bootsectors/Config.kmk	(revision 66812)
@@ -560,4 +560,5 @@
 #       -0                     Use 8086 instruction set (16-bit only).
 #       -3                     Use 386 instruction set (16-bit only).
+#       -e<num>                Stop after <num> errors.
 #       -wx                    Maxium warning level.
 #       -zl                    Don't emit default library information.
@@ -603,7 +604,7 @@
 TEMPLATE_VBoxBS3KitImg_CXXTOOL      = Bs3Ow16
 TEMPLATE_VBoxBS3KitImg_CFLAGS       = $(if $(BS3KIT_SEGNM_DATA16),-nd=$(BS3KIT_SEGNM_DATA16),) \
-	-nt=BS3TEXT16 -nc=$(BS3KIT_CLASS_CODE16) -ecc -q -0 -wx -zl -zdp -zu -ml $(BS3_OW_DBG_OPT) -s -oa -ob -of -oi -ol -or -os -oh -d+
+	-nt=BS3TEXT16 -nc=$(BS3KIT_CLASS_CODE16) -ecc -q -0 -e125 -wx -zl -zdp -zu -ml $(BS3_OW_DBG_OPT) -s -oa -ob -of -oi -ol -or -os -oh -d+
 TEMPLATE_VBoxBS3KitImg_CXXFLAGS     = $(if $(BS3KIT_SEGNM_DATA16),-nd=$(BS3KIT_SEGNM_DATA16),) \
-	-nt=BS3TEXT16 -nc=$(BS3KIT_CLASS_CODE16) -ecc -q -0 -wx -zl -zdp -zu -ml $(BS3_OW_DBG_OPT) -s -oa -ob -of -oi -ol -or -os -oh -d+
+	-nt=BS3TEXT16 -nc=$(BS3KIT_CLASS_CODE16) -ecc -q -0 -e125 -wx -zl -zdp -zu -ml $(BS3_OW_DBG_OPT) -s -oa -ob -of -oi -ol -or -os -oh -d+
 TEMPLATE_VBoxBS3KitImg_CDEFS        = ARCH_BITS=16 RT_ARCH_X86
 
@@ -772,7 +773,7 @@
 TEMPLATE_VBoxBS3KitImg32_CXXTOOL      = Bs3Ow32
 TEMPLATE_VBoxBS3KitImg32_CFLAGS       = \
-	-nt=BS3TEXT32 -nd=BS3DATA32 -nc=BS3CLASS32CODE -ecc -q -wx -zl -mf $(BS3_OW_DBG_OPT) -s -oa -ob -of -oi -ol -or -os -d+
+	-nt=BS3TEXT32 -nd=BS3DATA32 -nc=BS3CLASS32CODE -ecc -q -e125 -wx -zl -mf $(BS3_OW_DBG_OPT) -s -oa -ob -of -oi -ol -or -os -d+
 TEMPLATE_VBoxBS3KitImg32_CXXFLAGS     = \
-	-nt=BS3TEXT32 -nd=BS3DATA32 -nc=BS3CLASS32CODE -ecc -q -wx -zl -mf $(BS3_OW_DBG_OPT) -s -oa -ob -of -oi -ol -or -os -d+
+	-nt=BS3TEXT32 -nd=BS3DATA32 -nc=BS3CLASS32CODE -ecc -q -e125 -wx -zl -mf $(BS3_OW_DBG_OPT) -s -oa -ob -of -oi -ol -or -os -d+
 TEMPLATE_VBoxBS3KitImg32_INCS         = $(VBOX_PATH_BS3KIT_SRC) .
 TEMPLATE_VBoxBS3KitImg32_LDTOOL       = VBoxBsUnusedLd
Index: /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c
===================================================================
--- /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c	(revision 66811)
+++ /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c	(revision 66812)
@@ -1583,5 +1583,5 @@
 
 
-static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Pq_Uq(PBS3CG1STATE pThis, unsigned iEncoding)
+static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Pq_WO_Uq(PBS3CG1STATE pThis, unsigned iEncoding)
 {
     unsigned off;
@@ -1607,5 +1607,5 @@
 
 
-static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Vq_UqHi(PBS3CG1STATE pThis, unsigned iEncoding)
+static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Vq_WO_UqHi(PBS3CG1STATE pThis, unsigned iEncoding)
 {
     unsigned off;
@@ -1699,5 +1699,5 @@
 
 
-static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Vdq_Wdq(PBS3CG1STATE pThis, unsigned iEncoding)
+static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Vdq_WO_Wdq(PBS3CG1STATE pThis, unsigned iEncoding)
 {
     unsigned off;
@@ -1821,5 +1821,5 @@
 
 
-static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VqZxReg_Nq(PBS3CG1STATE pThis, unsigned iEncoding)
+static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VqZxReg_WO_Nq(PBS3CG1STATE pThis, unsigned iEncoding)
 {
     unsigned off;
@@ -1888,5 +1888,5 @@
 
 
-static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_MbRO(PBS3CG1STATE pThis, unsigned iEncoding)
+static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Mb_RO(PBS3CG1STATE pThis, unsigned iEncoding)
 {
     unsigned off;
@@ -1905,5 +1905,5 @@
 
 
-static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_MdRO(PBS3CG1STATE pThis, unsigned iEncoding)
+static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Md_RO(PBS3CG1STATE pThis, unsigned iEncoding)
 {
     unsigned off;
@@ -1922,5 +1922,5 @@
 
 
-static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_MdWO(PBS3CG1STATE pThis, unsigned iEncoding)
+static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Md_WO(PBS3CG1STATE pThis, unsigned iEncoding)
 {
     unsigned off;
@@ -2253,52 +2253,52 @@
             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Gv_Ev__OR__BS3CG1ENC_MODRM_Ev_Gv(pThis, iEncoding);
 
-        case BS3CG1ENC_MODRM_Wss_Vss:
+        case BS3CG1ENC_MODRM_Wss_WO_Vss:
             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Wss_Vss(pThis, iEncoding);
-        case BS3CG1ENC_MODRM_Wsd_Vsd:
+        case BS3CG1ENC_MODRM_Wsd_WO_Vsd:
             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Wsd_Vsd(pThis, iEncoding);
-        case BS3CG1ENC_MODRM_Wps_Vps:
-        case BS3CG1ENC_MODRM_Wpd_Vpd:
+        case BS3CG1ENC_MODRM_Wps_WO_Vps:
+        case BS3CG1ENC_MODRM_Wpd_WO_Vpd:
             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Wps_Vps__OR__BS3CG1ENC_MODRM_Wpd_Vpd(pThis, iEncoding);
-        case BS3CG1ENC_MODRM_WqZxReg_Vq:
+        case BS3CG1ENC_MODRM_WqZxReg_WO_Vq:
             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_WqZxReg_Vq(pThis, iEncoding);
 
-        case BS3CG1ENC_MODRM_Pq_Uq:
-            return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Pq_Uq(pThis, iEncoding);
-
-        case BS3CG1ENC_MODRM_Vq_UqHi:
-            return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Vq_UqHi(pThis, iEncoding);
-        case BS3CG1ENC_MODRM_Vq_Mq:
+        case BS3CG1ENC_MODRM_Pq_WO_Uq:
+            return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Pq_WO_Uq(pThis, iEncoding);
+
+        case BS3CG1ENC_MODRM_Vq_WO_UqHi:
+            return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Vq_WO_UqHi(pThis, iEncoding);
+        case BS3CG1ENC_MODRM_Vq_WO_Mq:
             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Vq_Mq(pThis, iEncoding);
-        case BS3CG1ENC_MODRM_VqHi_Uq:
+        case BS3CG1ENC_MODRM_VqHi_WO_Uq:
             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VqHi_Uq(pThis, iEncoding);
-        case BS3CG1ENC_MODRM_VqHi_Mq:
+        case BS3CG1ENC_MODRM_VqHi_WO_Mq:
             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VqHi_Mq(pThis, iEncoding);
-        case BS3CG1ENC_MODRM_Vdq_Wdq:
-            return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Vdq_Wdq(pThis, iEncoding);
-        case BS3CG1ENC_MODRM_Vpd_Wpd:
-        case BS3CG1ENC_MODRM_Vps_Wps:
+        case BS3CG1ENC_MODRM_Vdq_WO_Wdq:
+            return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Vdq_WO_Wdq(pThis, iEncoding);
+        case BS3CG1ENC_MODRM_Vpd_WO_Wpd:
+        case BS3CG1ENC_MODRM_Vps_WO_Wps:
             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Vps_Wps__OR__BS3CG1ENC_MODRM_Vpd_Wpd(pThis, iEncoding);
-        case BS3CG1ENC_MODRM_VssZxReg_Wss:
+        case BS3CG1ENC_MODRM_VssZxReg_WO_Wss:
             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VssZxReg_Wss(pThis, iEncoding);
-        case BS3CG1ENC_MODRM_VsdZxReg_Wsd:
-        case BS3CG1ENC_MODRM_VqZxReg_Wq:
+        case BS3CG1ENC_MODRM_VsdZxReg_WO_Wsd:
+        case BS3CG1ENC_MODRM_VqZxReg_WO_Wq:
             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VsdZxReg_Wsd__OR__MODRM_VqZxReg_Wq(pThis, iEncoding);
-        case BS3CG1ENC_MODRM_VqZxReg_Nq:
-            return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VqZxReg_Nq(pThis, iEncoding);
+        case BS3CG1ENC_MODRM_VqZxReg_WO_Nq:
+            return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VqZxReg_WO_Nq(pThis, iEncoding);
 
         case BS3CG1ENC_MODRM_Gv_Ma:
             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Gv_Ma(pThis, iEncoding);
 
-        case BS3CG1ENC_MODRM_MbRO:
-            return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_MbRO(pThis, iEncoding);
-        case BS3CG1ENC_MODRM_MdRO:
-            return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_MdRO(pThis, iEncoding);
-        case BS3CG1ENC_MODRM_MdWO:
-            return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_MdWO(pThis, iEncoding);
-        case BS3CG1ENC_VEX_MODRM_MdWO:
+        case BS3CG1ENC_MODRM_Mb_RO:
+            return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Mb_RO(pThis, iEncoding);
+        case BS3CG1ENC_MODRM_Md_RO:
+            return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Md_RO(pThis, iEncoding);
+        case BS3CG1ENC_MODRM_Md_WO:
+            return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Md_WO(pThis, iEncoding);
+        case BS3CG1ENC_VEX_MODRM_Md_WO:
             return Bs3Cg1EncodeNext_BS3CG1ENC_VEX_MODRM_MdWO(pThis, iEncoding);
-        case BS3CG1ENC_MODRM_MqWO_Vq:
+        case BS3CG1ENC_MODRM_Mq_WO_Vq:
             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_MqWO_Vq(pThis, iEncoding);
-        case BS3CG1ENC_MODRM_MqWO_VqHi:
+        case BS3CG1ENC_MODRM_Mq_WO_VqHi:
             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_MqWO_VqHi(pThis, iEncoding);
 
@@ -2398,5 +2398,5 @@
             break;
 
-        case BS3CG1ENC_MODRM_Wss_Vss:
+        case BS3CG1ENC_MODRM_Wss_WO_Vss:
             pThis->iRmOp             = 0;
             pThis->iRegOp            = 1;
@@ -2407,6 +2407,6 @@
             break;
 
-        case BS3CG1ENC_MODRM_Wsd_Vsd:
-        case BS3CG1ENC_MODRM_WqZxReg_Vq:
+        case BS3CG1ENC_MODRM_Wsd_WO_Vsd:
+        case BS3CG1ENC_MODRM_WqZxReg_WO_Vq:
             pThis->iRmOp             = 0;
             pThis->iRegOp            = 1;
@@ -2417,6 +2417,6 @@
             break;
 
-        case BS3CG1ENC_MODRM_Wps_Vps:
-        case BS3CG1ENC_MODRM_Wpd_Vpd:
+        case BS3CG1ENC_MODRM_Wps_WO_Vps:
+        case BS3CG1ENC_MODRM_Wpd_WO_Vpd:
             pThis->iRmOp             = 0;
             pThis->iRegOp            = 1;
@@ -2427,5 +2427,5 @@
             break;
 
-        case BS3CG1ENC_MODRM_Vdq_Wdq:
+        case BS3CG1ENC_MODRM_Vdq_WO_Wdq:
             pThis->iRmOp             = 1;
             pThis->iRegOp            = 0;
@@ -2436,6 +2436,6 @@
             break;
 
-        case BS3CG1ENC_MODRM_Vpd_Wpd:
-        case BS3CG1ENC_MODRM_Vps_Wps:
+        case BS3CG1ENC_MODRM_Vpd_WO_Wpd:
+        case BS3CG1ENC_MODRM_Vps_WO_Wps:
             pThis->iRmOp             = 1;
             pThis->iRegOp            = 0;
@@ -2446,7 +2446,7 @@
             break;
 
-        case BS3CG1ENC_MODRM_Pq_Uq:
-        case BS3CG1ENC_MODRM_Vq_UqHi:
-        case BS3CG1ENC_MODRM_VqHi_Uq:
+        case BS3CG1ENC_MODRM_Pq_WO_Uq:
+        case BS3CG1ENC_MODRM_Vq_WO_UqHi:
+        case BS3CG1ENC_MODRM_VqHi_WO_Uq:
             pThis->iRmOp             = 1;
             pThis->iRegOp            = 0;
@@ -2457,6 +2457,6 @@
             break;
 
-        case BS3CG1ENC_MODRM_Vq_Mq:
-        case BS3CG1ENC_MODRM_VqHi_Mq:
+        case BS3CG1ENC_MODRM_Vq_WO_Mq:
+        case BS3CG1ENC_MODRM_VqHi_WO_Mq:
             pThis->iRmOp             = 1;
             pThis->iRegOp            = 0;
@@ -2467,5 +2467,5 @@
             break;
 
-        case BS3CG1ENC_MODRM_VssZxReg_Wss:
+        case BS3CG1ENC_MODRM_VssZxReg_WO_Wss:
             pThis->iRmOp             = 1;
             pThis->iRegOp            = 0;
@@ -2476,7 +2476,7 @@
             break;
 
-        case BS3CG1ENC_MODRM_VsdZxReg_Wsd:
-        case BS3CG1ENC_MODRM_VqZxReg_Wq:
-        case BS3CG1ENC_MODRM_VqZxReg_Nq:
+        case BS3CG1ENC_MODRM_VsdZxReg_WO_Wsd:
+        case BS3CG1ENC_MODRM_VqZxReg_WO_Wq:
+        case BS3CG1ENC_MODRM_VqZxReg_WO_Nq:
             pThis->iRmOp             = 1;
             pThis->iRegOp            = 0;
@@ -2487,5 +2487,5 @@
             break;
 
-        case BS3CG1ENC_MODRM_MbRO:
+        case BS3CG1ENC_MODRM_Mb_RO:
             pThis->iRmOp             = 0;
             pThis->aOperands[0].cbOp = 1;
@@ -2493,5 +2493,5 @@
             break;
 
-        case BS3CG1ENC_MODRM_MdRO:
+        case BS3CG1ENC_MODRM_Md_RO:
             pThis->iRmOp             = 0;
             pThis->aOperands[0].cbOp = 4;
@@ -2499,6 +2499,6 @@
             break;
 
-        case BS3CG1ENC_MODRM_MdWO:
-        case BS3CG1ENC_VEX_MODRM_MdWO:
+        case BS3CG1ENC_MODRM_Md_WO:
+        case BS3CG1ENC_VEX_MODRM_Md_WO:
             pThis->iRmOp             = 0;
             pThis->aOperands[0].cbOp = 4;
@@ -2506,6 +2506,6 @@
             break;
 
-        case BS3CG1ENC_MODRM_MqWO_Vq:
-        case BS3CG1ENC_MODRM_MqWO_VqHi:
+        case BS3CG1ENC_MODRM_Mq_WO_Vq:
+        case BS3CG1ENC_MODRM_Mq_WO_VqHi:
             pThis->iRmOp             = 0;
             pThis->iRegOp            = 1;
Index: /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h
===================================================================
--- /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h	(revision 66811)
+++ /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h	(revision 66812)
@@ -45,27 +45,40 @@
     BS3CG1OP_Ev,
     BS3CG1OP_Wss,
+    BS3CG1OP_Wss_WO,
     BS3CG1OP_Wsd,
+    BS3CG1OP_Wsd_WO,
     BS3CG1OP_Wps,
+    BS3CG1OP_Wps_WO,
     BS3CG1OP_Wpd,
+    BS3CG1OP_Wpd_WO,
     BS3CG1OP_Wdq,
+    BS3CG1OP_Wdq_WO,
     BS3CG1OP_Wq,
-    BS3CG1OP_WqZxReg,
+    BS3CG1OP_Wq_WO,
+    BS3CG1OP_WqZxReg_WO,
 
     BS3CG1OP_Gb,
     BS3CG1OP_Gv,
     BS3CG1OP_Nq,
-    BS3CG1OP_Pq,
+    BS3CG1OP_Pq_WO,
     BS3CG1OP_Uq,
     BS3CG1OP_UqHi,
     BS3CG1OP_Vss,
-    BS3CG1OP_VssZxReg,
+    BS3CG1OP_Vss_WO,
+    BS3CG1OP_VssZxReg_WO,
     BS3CG1OP_Vsd,
-    BS3CG1OP_VsdZxReg,
+    BS3CG1OP_Vsd_WO,
+    BS3CG1OP_VsdZxReg_WO,
     BS3CG1OP_Vps,
+    BS3CG1OP_Vps_WO,
     BS3CG1OP_Vpd,
+    BS3CG1OP_Vpd_WO,
     BS3CG1OP_Vq,
+    BS3CG1OP_Vq_WO,
     BS3CG1OP_Vdq,
+    BS3CG1OP_Vdq_WO,
     BS3CG1OP_VqHi,
-    BS3CG1OP_VqZxReg,
+    BS3CG1OP_VqHi_WO,
+    BS3CG1OP_VqZxReg_WO,
 
     BS3CG1OP_Ib,
@@ -76,9 +89,9 @@
 
     BS3CG1OP_Ma,
-    BS3CG1OP_MbRO,
-    BS3CG1OP_MdRO,
-    BS3CG1OP_MdWO,
+    BS3CG1OP_Mb_RO,
+    BS3CG1OP_Md_RO,
+    BS3CG1OP_Md_WO,
     BS3CG1OP_Mq,
-    BS3CG1OP_MqWO,
+    BS3CG1OP_Mq_WO,
 
     BS3CG1OP_END
@@ -100,32 +113,32 @@
     BS3CG1ENC_MODRM_Eb_Gb,
     BS3CG1ENC_MODRM_Ev_Gv,
-    BS3CG1ENC_MODRM_Wss_Vss,
-    BS3CG1ENC_MODRM_Wsd_Vsd,
-    BS3CG1ENC_MODRM_Wps_Vps,
-    BS3CG1ENC_MODRM_Wpd_Vpd,
-    BS3CG1ENC_MODRM_WqZxReg_Vq,
+    BS3CG1ENC_MODRM_Wss_WO_Vss,
+    BS3CG1ENC_MODRM_Wsd_WO_Vsd,
+    BS3CG1ENC_MODRM_Wps_WO_Vps,
+    BS3CG1ENC_MODRM_Wpd_WO_Vpd,
+    BS3CG1ENC_MODRM_WqZxReg_WO_Vq,
 
     BS3CG1ENC_MODRM_Gb_Eb,
     BS3CG1ENC_MODRM_Gv_Ev,
     BS3CG1ENC_MODRM_Gv_Ma, /**< bound instruction */
-    BS3CG1ENC_MODRM_Pq_Uq,
-    BS3CG1ENC_MODRM_Vq_UqHi,
-    BS3CG1ENC_MODRM_Vq_Mq,
-    BS3CG1ENC_MODRM_VqHi_Uq,
-    BS3CG1ENC_MODRM_VqHi_Mq,
-    BS3CG1ENC_MODRM_Vdq_Wdq,
-    BS3CG1ENC_MODRM_Vpd_Wpd,
-    BS3CG1ENC_MODRM_Vps_Wps,
-    BS3CG1ENC_MODRM_VssZxReg_Wss,
-    BS3CG1ENC_MODRM_VsdZxReg_Wsd,
-    BS3CG1ENC_MODRM_VqZxReg_Wq,
-    BS3CG1ENC_MODRM_VqZxReg_Nq,
-    BS3CG1ENC_MODRM_MbRO,
-    BS3CG1ENC_MODRM_MdRO,
-    BS3CG1ENC_MODRM_MdWO,
-    BS3CG1ENC_MODRM_MqWO_Vq,
-    BS3CG1ENC_MODRM_MqWO_VqHi,
-
-    BS3CG1ENC_VEX_MODRM_MdWO,
+    BS3CG1ENC_MODRM_Pq_WO_Uq,
+    BS3CG1ENC_MODRM_Vq_WO_UqHi,
+    BS3CG1ENC_MODRM_Vq_WO_Mq,
+    BS3CG1ENC_MODRM_VqHi_WO_Uq,
+    BS3CG1ENC_MODRM_VqHi_WO_Mq,
+    BS3CG1ENC_MODRM_Vdq_WO_Wdq,
+    BS3CG1ENC_MODRM_Vpd_WO_Wpd,
+    BS3CG1ENC_MODRM_Vps_WO_Wps,
+    BS3CG1ENC_MODRM_VssZxReg_WO_Wss,
+    BS3CG1ENC_MODRM_VsdZxReg_WO_Wsd,
+    BS3CG1ENC_MODRM_VqZxReg_WO_Wq,
+    BS3CG1ENC_MODRM_VqZxReg_WO_Nq,
+    BS3CG1ENC_MODRM_Mb_RO,
+    BS3CG1ENC_MODRM_Md_RO,
+    BS3CG1ENC_MODRM_Md_WO,
+    BS3CG1ENC_MODRM_Mq_WO_Vq,
+    BS3CG1ENC_MODRM_Mq_WO_VqHi,
+
+    BS3CG1ENC_VEX_MODRM_Md_WO,
 
     BS3CG1ENC_FIXED,
