Index: trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsPython.py
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsPython.py	(revision 66936)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsPython.py	(revision 66937)
@@ -273,7 +273,6 @@
 
     # VEX.vvvv
-    'HdqCss':       ( 'IDX_UseModRM',       'vvvv',   '%Hx',  'HdqCss',  ),
-    'HdqCsd':       ( 'IDX_UseModRM',       'vvvv',   '%Hx',  'HdqCsd',  ),
-    'HdqCq':        ( 'IDX_UseModRM',       'vvvv',   '%Hq',  'HdqCq',   ),
+    'HssHi':        ( 'IDX_UseModRM',       'vvvv',   '%Hx',  'HssHi',   ),
+    'HsdHi':        ( 'IDX_UseModRM',       'vvvv',   '%Hx',  'HsdHi',   ),
     'HqHi':         ( 'IDX_UseModRM',       'vvvv',   '%Hq',  'HqHi',    ),
 
Index: trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap1.cpp.h
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap1.cpp.h	(revision 66936)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap1.cpp.h	(revision 66937)
@@ -218,6 +218,8 @@
          * @optest      op1=0 op2=0  op3=-22  -> op1=0xffffffea
          * @optest      op1=3 op2=-1 op3=0x77 -> op1=-4294967177
+         * @optest      op1=3 op2=-2 op3=0x77 -> op1=-8589934473
+         * @note        HssHi refers to bits 127:32.
          */
-        IEMOP_MNEMONIC3(VEX_RVM, VMOVSS, vmovss, Vss_WO, HdqCss, Uss, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
+        IEMOP_MNEMONIC3(VEX_RVM, VMOVSS, vmovss, Vss_WO, HssHi, Uss, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
         IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX();
         IEM_MC_BEGIN(0, 0);
@@ -283,6 +285,7 @@
          * @optest      op1=3 op2=-1 op3=0x77 ->
          *              op1=0xffffffffffffffff0000000000000077
+         * @optest      op1=3 op2=0x42 op3=0x77 -> op1=0x420000000000000077
          */
-        IEMOP_MNEMONIC3(VEX_RVM, VMOVSD, vmovsd, Vsd_WO, HdqCsd, Usd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
+        IEMOP_MNEMONIC3(VEX_RVM, VMOVSD, vmovsd, Vsd_WO, HsdHi, Usd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
         IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX();
         IEM_MC_BEGIN(0, 0);
@@ -499,6 +502,7 @@
          * @optest      op1=0 op2=0  op3=-22  -> op1=0xffffffea
          * @optest      op1=3 op2=-1 op3=0x77 -> op1=-4294967177
+         * @optest      op1=3 op2=0x42 op3=0x77 -> op1=0x4200000077
          */
-        IEMOP_MNEMONIC3(VEX_MVR, VMOVSS, vmovss, Uss_WO, HdqCss, Vss, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
+        IEMOP_MNEMONIC3(VEX_MVR, VMOVSS, vmovss, Uss_WO, HssHi, Vss, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
         IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX();
         IEM_MC_BEGIN(0, 0);
@@ -564,6 +568,7 @@
          * @optest      op1=3 op2=-1 op3=0x77 ->
          *              op1=0xffffffffffffffff0000000000000077
+         * @optest      op2=0x42 op3=0x77 -> op1=0x420000000000000077
          */
-        IEMOP_MNEMONIC3(VEX_MVR, VMOVSD, vmovsd, Usd_WO, HdqCsd, Vsd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
+        IEMOP_MNEMONIC3(VEX_MVR, VMOVSD, vmovsd, Usd_WO, HsdHi, Vsd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
         IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX();
         IEM_MC_BEGIN(0, 0);
@@ -624,11 +629,11 @@
          * @opgroup     og_avx_simdfp_datamerge
          * @opxcpttype  7LZ
-         * @optest         op2=0x22002201220222032204220522062207
+         * @optest         op2=0x2200220122022203
          *                 op3=0x3304330533063307
          *              -> op1=0x22002201220222033304330533063307
-         * @optest      op2=-2  op3=-42 -> op1=-42
-         * @note        op3 is only a 8-byte high XMM register half.
+         * @optest      op2=-1  op3=-42 -> op1=-42
+         * @note        op3 and op2 are only the 8-byte high XMM register halfs.
          */
-        IEMOP_MNEMONIC3(VEX_RVM, VMOVHLPS, vmovhlps, Vq_WO, HdqCq, UqHi, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
+        IEMOP_MNEMONIC3(VEX_RVM, VMOVHLPS, vmovhlps, Vq_WO, HqHi, UqHi, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
 
         IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX_AND_L0();
@@ -657,8 +662,8 @@
          * @optest      op1=1 op2=0 op3=0 -> op1=0
          * @optest      op1=0 op2=-1 op3=-1 -> op1=-1
-         * @optest      op1=1 op2=0x20000000000000000 op3=3 -> op1=0x20000000000000003
+         * @optest      op1=1 op2=2 op3=3 -> op1=0x20000000000000003
          * @optest      op2=-1 op3=0x42 -> op1=0xffffffffffffffff0000000000000042
          */
-        IEMOP_MNEMONIC3(VEX_RVM_MEM, VMOVLPS, vmovlps, Vq_WO, HdqCq, Mq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
+        IEMOP_MNEMONIC3(VEX_RVM_MEM, VMOVLPS, vmovlps, Vq_WO, HqHi, Mq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
 
         IEM_MC_BEGIN(0, 2);
Index: trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-data.py
===================================================================
--- trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-data.py	(revision 66936)
+++ trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-data.py	(revision 66937)
@@ -306,5 +306,4 @@
             self.sEncoding     += '_' + oOp.sType;
         if oInstr.fUnused:
-            print('DEBUG: Unused Bs3Cg1Instruction: %s\n' % (oInstr.sEncoding,));
             if oInstr.sInvalidStyle == 'immediate' and oInstr.sSubOpcode:
                 self.sEncoding += '_MOD_EQ_3' if oInstr.sSubOpcode == '11 mr/reg' else '_MOD_NE_3';
Index: trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c
===================================================================
--- trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c	(revision 66936)
+++ trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c	(revision 66937)
@@ -552,4 +552,20 @@
     /* [BS3CG1DST_XMM14_DW0_ZX] =*/ 4,
     /* [BS3CG1DST_XMM15_DW0_ZX] =*/ 4,
+    /* [BS3CG1DST_XMM0_HI96] = */   12,
+    /* [BS3CG1DST_XMM1_HI96] = */   12,
+    /* [BS3CG1DST_XMM2_HI96] = */   12,
+    /* [BS3CG1DST_XMM3_HI96] = */   12,
+    /* [BS3CG1DST_XMM4_HI96] = */   12,
+    /* [BS3CG1DST_XMM5_HI96] = */   12,
+    /* [BS3CG1DST_XMM6_HI96] = */   12,
+    /* [BS3CG1DST_XMM7_HI96] = */   12,
+    /* [BS3CG1DST_XMM8_HI96] = */   12,
+    /* [BS3CG1DST_XMM9_HI96] = */   12,
+    /* [BS3CG1DST_XMM10_HI96] =*/   12,
+    /* [BS3CG1DST_XMM11_HI96] =*/   12,
+    /* [BS3CG1DST_XMM12_HI96] =*/   12,
+    /* [BS3CG1DST_XMM13_HI96] =*/   12,
+    /* [BS3CG1DST_XMM14_HI96] =*/   12,
+    /* [BS3CG1DST_XMM15_HI96] =*/   12,
     /* [BS3CG1DST_YMM0] = */        32,
     /* [BS3CG1DST_YMM1] = */        32,
@@ -800,4 +816,20 @@
     /* [BS3CG1DST_XMM14_DW0_ZX] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]),
     /* [BS3CG1DST_XMM15_DW0_ZX] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]),
+    /* [BS3CG1DST_XMM0_HI96] = */   sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0].au32[1]),
+    /* [BS3CG1DST_XMM1_HI96] = */   sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1].au32[1]),
+    /* [BS3CG1DST_XMM2_HI96] = */   sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2].au32[1]),
+    /* [BS3CG1DST_XMM3_HI96] = */   sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3].au32[1]),
+    /* [BS3CG1DST_XMM4_HI96] = */   sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4].au32[1]),
+    /* [BS3CG1DST_XMM5_HI96] = */   sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5].au32[1]),
+    /* [BS3CG1DST_XMM6_HI96] = */   sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6].au32[1]),
+    /* [BS3CG1DST_XMM7_HI96] = */   sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7].au32[1]),
+    /* [BS3CG1DST_XMM8_HI96] = */   sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8].au32[1]),
+    /* [BS3CG1DST_XMM9_HI96] = */   sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9].au32[1]),
+    /* [BS3CG1DST_XMM10_HI96] =*/   sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10].au32[1]),
+    /* [BS3CG1DST_XMM11_HI96] =*/   sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11].au32[1]),
+    /* [BS3CG1DST_XMM12_HI96] =*/   sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12].au32[1]),
+    /* [BS3CG1DST_XMM13_HI96] =*/   sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13].au32[1]),
+    /* [BS3CG1DST_XMM14_HI96] =*/   sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14].au32[1]),
+    /* [BS3CG1DST_XMM15_HI96] =*/   sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15].au32[1]),
 
     /* [BS3CG1DST_YMM0] = */        ~0U,
@@ -1048,4 +1080,20 @@
     { "XMM14_DW0_ZX" },
     { "XMM15_DW0_ZX" },
+    { "XMM0_HI96" },
+    { "XMM1_HI96" },
+    { "XMM2_HI96" },
+    { "XMM3_HI96" },
+    { "XMM4_HI96" },
+    { "XMM5_HI96" },
+    { "XMM6_HI96" },
+    { "XMM7_HI96" },
+    { "XMM8_HI96" },
+    { "XMM9_HI96" },
+    { "XMM10_HI96" },
+    { "XMM11_HI96" },
+    { "XMM12_HI96" },
+    { "XMM13_HI96" },
+    { "XMM14_HI96" },
+    { "XMM15_HI96" },
     { "YMM0" },
     { "YMM1" },
@@ -2431,5 +2479,5 @@
  */
 static unsigned BS3_NEAR_CODE
-Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_HdqCsomething_Usomething_Lip_Wip_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding)
+Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Hsomething_Usomething_Lip_Wip_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding)
 {
     unsigned off;
@@ -3576,10 +3624,10 @@
             break;
 
-        case BS3CG1ENC_VEX_MODRM_Vss_WO_HdqCss_Uss:
-            pThis->pfnEncoder        = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_HdqCsomething_Usomething_Lip_Wip_OR_ViceVersa;
+        case BS3CG1ENC_VEX_MODRM_Vss_WO_HssHi_Uss:
+            pThis->pfnEncoder        = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Hsomething_Usomething_Lip_Wip_OR_ViceVersa;
             pThis->iRegOp            = 0;
             pThis->iRmOp             = 2;
             pThis->aOperands[0].cbOp = 16;
-            pThis->aOperands[1].cbOp = 16;
+            pThis->aOperands[1].cbOp = 12;
             pThis->aOperands[2].cbOp = 4;
             pThis->aOperands[0].enmLocation  = BS3CG1OPLOC_CTX_ZX_VLMAX;
@@ -3587,5 +3635,5 @@
             pThis->aOperands[2].enmLocation  = BS3CG1OPLOC_CTX;
             pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0;
-            pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0;
+            pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_HI96;
             pThis->aOperands[2].idxFieldBase = BS3CG1DST_XMM0_DW0;
             break;
@@ -3603,10 +3651,10 @@
             break;
 
-        case BS3CG1ENC_VEX_MODRM_Vsd_WO_HdqCsd_Usd:
-            pThis->pfnEncoder        = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_HdqCsomething_Usomething_Lip_Wip_OR_ViceVersa;
+        case BS3CG1ENC_VEX_MODRM_Vsd_WO_HsdHi_Usd:
+            pThis->pfnEncoder        = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Hsomething_Usomething_Lip_Wip_OR_ViceVersa;
             pThis->iRegOp            = 0;
             pThis->iRmOp             = 2;
             pThis->aOperands[0].cbOp = 16;
-            pThis->aOperands[1].cbOp = 16;
+            pThis->aOperands[1].cbOp = 8;
             pThis->aOperands[2].cbOp = 8;
             pThis->aOperands[0].enmLocation  = BS3CG1OPLOC_CTX_ZX_VLMAX;
@@ -3614,14 +3662,14 @@
             pThis->aOperands[2].enmLocation  = BS3CG1OPLOC_CTX;
             pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0;
-            pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0;
+            pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_HI;
             pThis->aOperands[2].idxFieldBase = BS3CG1DST_XMM0_LO;
             break;
 
-        case BS3CG1ENC_VEX_MODRM_Vq_WO_HdqCq_UqHi:
+        case BS3CG1ENC_VEX_MODRM_Vq_WO_HqHi_UqHi:
             pThis->pfnEncoder        = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_HdqCsomething_Usomething_Wip_OR_ViceVersa;
             pThis->iRegOp            = 0;
             pThis->iRmOp             = 2;
             pThis->aOperands[0].cbOp = 16;
-            pThis->aOperands[1].cbOp = 16;
+            pThis->aOperands[1].cbOp = 8;
             pThis->aOperands[2].cbOp = 8;
             pThis->aOperands[0].enmLocation  = BS3CG1OPLOC_CTX_ZX_VLMAX;
@@ -3629,21 +3677,6 @@
             pThis->aOperands[2].enmLocation  = BS3CG1OPLOC_CTX;
             pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0;
-            pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0;
+            pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_HI;
             pThis->aOperands[2].idxFieldBase = BS3CG1DST_XMM0_HI;
-            break;
-
-        case BS3CG1ENC_VEX_MODRM_Vq_WO_HdqCq_Mq:
-            pThis->pfnEncoder        = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Hsomething_Msomething_Wip_OR_ViceVersa;
-            pThis->iRegOp            = 0;
-            pThis->iRmOp             = 2;
-            pThis->aOperands[0].cbOp = 16;
-            pThis->aOperands[1].cbOp = 16;
-            pThis->aOperands[2].cbOp = 8;
-            pThis->aOperands[0].enmLocation  = BS3CG1OPLOC_CTX_ZX_VLMAX;
-            pThis->aOperands[1].enmLocation  = BS3CG1OPLOC_CTX;
-            pThis->aOperands[2].enmLocation  = BS3CG1OPLOC_MEM;
-            pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0;
-            pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0;
-            pThis->aOperands[2].idxFieldBase = BS3CG1DST_INVALID;
             break;
 
@@ -3687,10 +3720,10 @@
             break;
 
-        case BS3CG1ENC_VEX_MODRM_Uss_WO_HdqCss_Vss:
-            pThis->pfnEncoder        = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_HdqCsomething_Usomething_Lip_Wip_OR_ViceVersa;
+        case BS3CG1ENC_VEX_MODRM_Uss_WO_HssHi_Vss:
+            pThis->pfnEncoder        = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Hsomething_Usomething_Lip_Wip_OR_ViceVersa;
             pThis->iRegOp            = 2;
             pThis->iRmOp             = 0;
             pThis->aOperands[0].cbOp = 16;
-            pThis->aOperands[1].cbOp = 16;
+            pThis->aOperands[1].cbOp = 96;
             pThis->aOperands[2].cbOp = 4;
             pThis->aOperands[0].enmLocation  = BS3CG1OPLOC_CTX_ZX_VLMAX;
@@ -3698,14 +3731,14 @@
             pThis->aOperands[2].enmLocation  = BS3CG1OPLOC_CTX;
             pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0;
-            pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0;
+            pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_HI96;
             pThis->aOperands[2].idxFieldBase = BS3CG1DST_XMM0_DW0;
             break;
 
-        case BS3CG1ENC_VEX_MODRM_Usd_WO_HdqCsd_Vsd:
-            pThis->pfnEncoder        = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_HdqCsomething_Usomething_Lip_Wip_OR_ViceVersa;
+        case BS3CG1ENC_VEX_MODRM_Usd_WO_HsdHi_Vsd:
+            pThis->pfnEncoder        = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Hsomething_Usomething_Lip_Wip_OR_ViceVersa;
             pThis->iRegOp            = 2;
             pThis->iRmOp             = 0;
             pThis->aOperands[0].cbOp = 16;
-            pThis->aOperands[1].cbOp = 16;
+            pThis->aOperands[1].cbOp = 8;
             pThis->aOperands[2].cbOp = 8;
             pThis->aOperands[0].enmLocation  = BS3CG1OPLOC_CTX_ZX_VLMAX;
@@ -3713,5 +3746,5 @@
             pThis->aOperands[2].enmLocation  = BS3CG1OPLOC_CTX;
             pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0;
-            pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0;
+            pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_HI;
             pThis->aOperands[2].idxFieldBase = BS3CG1DST_XMM0_LO;
             break;
@@ -4426,5 +4459,5 @@
             /* Optimized access to XMM and STx registers. */
             if (   pThis->pExtCtx->enmMethod != BS3EXTCTXMETHOD_ANCIENT
-                && offField - sizeof(BS3REGCTX) <= RT_UOFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]) )
+                && offField - sizeof(BS3REGCTX) < RT_UOFFSET_AFTER(BS3EXTCTX, Ctx.x87.aXMM[15]) )
                 PtrField.pb = (uint8_t *)pThis->pExtCtx + offField - sizeof(BS3REGCTX);
             /* Non-register operands: */
Index: trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h
===================================================================
--- trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h	(revision 66936)
+++ trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h	(revision 66937)
@@ -61,7 +61,6 @@
     BS3CG1OP_Gv,
     BS3CG1OP_Gv_RO,
-    BS3CG1OP_HdqCss,
-    BS3CG1OP_HdqCsd,
-    BS3CG1OP_HdqCq,
+    BS3CG1OP_HssHi,
+    BS3CG1OP_HsdHi,
     BS3CG1OP_HqHi,
     BS3CG1OP_Nq,
@@ -152,8 +151,7 @@
     BS3CG1ENC_VEX_MODRM_Vps_WO_Wps,
     BS3CG1ENC_VEX_MODRM_Vpd_WO_Wpd,
-    BS3CG1ENC_VEX_MODRM_Vss_WO_HdqCss_Uss,
-    BS3CG1ENC_VEX_MODRM_Vsd_WO_HdqCsd_Usd,
-    BS3CG1ENC_VEX_MODRM_Vq_WO_HdqCq_UqHi,
-    BS3CG1ENC_VEX_MODRM_Vq_WO_HdqCq_Mq,
+    BS3CG1ENC_VEX_MODRM_Vss_WO_HssHi_Uss,
+    BS3CG1ENC_VEX_MODRM_Vsd_WO_HsdHi_Usd,
+    BS3CG1ENC_VEX_MODRM_Vq_WO_HqHi_UqHi,
     BS3CG1ENC_VEX_MODRM_Vq_WO_HqHi_Mq,
     BS3CG1ENC_VEX_MODRM_VssZx_WO_Md,
@@ -162,6 +160,6 @@
     BS3CG1ENC_VEX_MODRM_Md_WO_Vss,
     BS3CG1ENC_VEX_MODRM_Mq_WO_Vsd,
-    BS3CG1ENC_VEX_MODRM_Uss_WO_HdqCss_Vss,
-    BS3CG1ENC_VEX_MODRM_Usd_WO_HdqCsd_Vsd,
+    BS3CG1ENC_VEX_MODRM_Uss_WO_HssHi_Vss,
+    BS3CG1ENC_VEX_MODRM_Usd_WO_HsdHi_Vsd,
     BS3CG1ENC_VEX_MODRM_Wps_WO_Vps,
     BS3CG1ENC_VEX_MODRM_Wpd_WO_Vpd,
@@ -610,4 +608,20 @@
     BS3CG1DST_XMM14_DW0_ZX,
     BS3CG1DST_XMM15_DW0_ZX,
+    BS3CG1DST_XMM0_HI96,
+    BS3CG1DST_XMM1_HI96,
+    BS3CG1DST_XMM2_HI96,
+    BS3CG1DST_XMM3_HI96,
+    BS3CG1DST_XMM4_HI96,
+    BS3CG1DST_XMM5_HI96,
+    BS3CG1DST_XMM6_HI96,
+    BS3CG1DST_XMM7_HI96,
+    BS3CG1DST_XMM8_HI96,
+    BS3CG1DST_XMM9_HI96,
+    BS3CG1DST_XMM10_HI96,
+    BS3CG1DST_XMM11_HI96,
+    BS3CG1DST_XMM12_HI96,
+    BS3CG1DST_XMM13_HI96,
+    BS3CG1DST_XMM14_HI96,
+    BS3CG1DST_XMM15_HI96,
     /* AVX registers. */
     BS3CG1DST_YMM0,
