Changeset 67042 in vbox for trunk/src/VBox/VMM/VMMAll

Timestamp:

May 23, 2017 1:44:16 PM (8 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

115627

Message:

IEM: Implemented (but not tested) vmovntdqa Vx,Mx (VEX.66.0F38 2a mod!=3).

Location:

trunk/src/VBox/VMM/VMMAll

Files:

• IEMAll.cpp (modified) (1 diff)
• IEMAllInstructionsPython.py (modified) (1 diff)
• IEMAllInstructionsVexMap2.cpp.h (modified) (2 diffs)

trunk/src/VBox/VMM/VMMAll/IEMAll.cpp

@@ -11220 +11220 @@
             return iemRaiseMathFault(pVCpu); \
     } while (0)
+#define IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT() \
+    do { \
+        if (   (IEM_GET_CTX(pVCpu)->aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
+            || !(IEM_GET_CTX(pVCpu)->cr4 & X86_CR4_OSXSAVE) \
+            || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx2) \
+            return iemRaiseUndefinedOpcode(pVCpu); \
+        if (IEM_GET_CTX(pVCpu)->cr0 & X86_CR0_TS) \
+            return iemRaiseDeviceNotAvailable(pVCpu); \
+    } while (0)
 #define IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() \
     do { \

trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsPython.py

@@ -259 +259 @@
     'Mps_WO':       ( 'IDX_UseModRM',       'rm',     '%Mps', 'Mps',     ),
     'Mpd_WO':       ( 'IDX_UseModRM',       'rm',     '%Mpd', 'Mpd',     ),
+    'Mx':           ( 'IDX_UseModRM',       'rm',     '%Mx',  'Mx',      ),
     'Mx_WO':        ( 'IDX_UseModRM',       'rm',     '%Mx',  'Mx',      ),
     'M_RO':         ( 'IDX_UseModRM',       'rm',     '%M',   'M',       ),

trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap2.cpp.h

@@ -134 +134 @@
 /** Opcode VEX.66.0F38 0x29. */
 FNIEMOP_STUB(iemOp_vpcmpeqq_Vx_Hx_Wx);
+
 /** Opcode VEX.66.0F38 0x2a. */
-FNIEMOP_STUB(iemOp_vmovntdqa_Vx_Hx_Mx);
+/*
+ * @ opcode      0x2a
+ * @ opcodesub   !11 mr/reg vex.l=0
+ * @ oppfx       0x66
+ * @ opcpuid     avx
+ * @ opgroup     og_avx_cachect
+ * @ opxcpttype  1
+ * @ optest      op1=-1 op2=2  -> op1=2
+ * @ optest      op1=0 op2=-42 -> op1=-42
+ */
+FNIEMOP_DEF(iemOp_vmovntdqa_Vx_Mx)
+{
+    Assert(pVCpu->iem.s.uVexLength <= 1);
+    IEMOP_MNEMONIC2(VEX_RM, VMOVNTDQA, vmovntdqa, Vx_WO, Mx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
+    uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
+    if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
+    {
+        if (pVCpu->iem.s.uVexLength == 0)
+        {
+            /*
+             * 128-bit: Memory, register.
+             */
+            IEM_MC_BEGIN(0, 2);
+            IEM_MC_LOCAL(RTUINT128U,                uSrc);
+            IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
+
+            IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
+            IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
+            IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
+            IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
+
+            IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
+            IEM_MC_STORE_YREG_U128_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
+
+            IEM_MC_ADVANCE_RIP();
+            IEM_MC_END();
+        }
+        else
+        {
+/*
+ * @ opdone
+ * @ opcode      0x2a
+ * @ opcodesub   !11 mr/reg vex.l=1
+ * @ oppfx       0x66
+ * @ opcpuid     avx2
+ * @ opgroup     og_avx2_cachect
+ * @ opxcpttype  1
+ * @ optest      op1=-1 op2=2  -> op1=2
+ * @ optest      op1=0 op2=-42 -> op1=-42
+ */
+            /*
+             * 256-bit: Memory, register.
+             */
+            IEM_MC_BEGIN(0, 2);
+            IEM_MC_LOCAL(RTUINT256U,                uSrc);
+            IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
+
+            IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
+            IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
+            IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
+            IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
+
+            IEM_MC_FETCH_YREG_U256(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
+            IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
+
+            IEM_MC_ADVANCE_RIP();
+            IEM_MC_END();
+        }
+        return VINF_SUCCESS;
+    }
+    /**
+     * @opdone
+     * @opmnemonic  udvex660f382areg
+     * @opcode      0x2a
+     * @opcodesub   11 mr/reg
+     * @oppfx       0x66
+     * @opunused    immediate
+     * @opcpuid     avx
+     * @optest      ->
+     * @oponly
+     */
+    return IEMOP_RAISE_INVALID_OPCODE();
+
+}
+
 /** Opcode VEX.66.0F38 0x2b. */
 FNIEMOP_STUB(iemOp_vpackusdw_Vx_Hx_Wx);
@@ -622 +707 @@
     /* 0x28 */  iemOp_InvalidNeedRM,        iemOp_vpmuldq_Vx_Hx_Wx,     iemOp_InvalidNeedRM,        iemOp_InvalidNeedRM,
     /* 0x29 */  iemOp_InvalidNeedRM,        iemOp_vpcmpeqq_Vx_Hx_Wx,    iemOp_InvalidNeedRM,        iemOp_InvalidNeedRM,
-    /* 0x2a */  iemOp_InvalidNeedRM,        iemOp_vmovntdqa_Vx_Hx_Mx,   iemOp_InvalidNeedRM,        iemOp_InvalidNeedRM,
+    /* 0x2a */  iemOp_InvalidNeedRM,        iemOp_vmovntdqa_Vx_Mx,      iemOp_InvalidNeedRM,        iemOp_InvalidNeedRM,
     /* 0x2b */  iemOp_InvalidNeedRM,        iemOp_vpackusdw_Vx_Hx_Wx,   iemOp_InvalidNeedRM,        iemOp_InvalidNeedRM,
     /* 0x2c */  iemOp_InvalidNeedRM,        iemOp_vmaskmovps_Vx_Hx_Mx,  iemOp_InvalidNeedRM,        iemOp_InvalidNeedRM,