Changeset 67072 in vbox
- Timestamp:
- May 25, 2017 8:26:51 AM (8 years ago)
- svn:sync-xref-src-repo-rev:
- 115735
- Location:
- trunk/src/VBox
- Files:
-
- 9 edited
-
VMM/Makefile.kmk (modified) (1 diff)
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VMM/VMMAll/IEMAllInstructionsPython.py (modified) (11 diffs)
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VMM/VMMAll/IEMAllInstructionsVexMap1.cpp.h (modified) (21 diffs)
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VMM/VMMAll/IEMAllInstructionsVexMap2.cpp.h (modified) (6 diffs)
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VMM/include/IEMInternal.h (modified) (3 diffs)
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VMM/testcase/tstIEMCheckMc.cpp (modified) (1 diff)
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ValidationKit/bootsectors/bs3-cpu-generated-1-data.py (modified) (4 diffs)
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ValidationKit/bootsectors/bs3-cpu-generated-1-template.c (modified) (22 diffs)
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ValidationKit/bootsectors/bs3-cpu-generated-1.h (modified) (5 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/Makefile.kmk
r67040 r67072 367 367 $(QUIET)$(SED) \ 368 368 -e '/IEMOP_MNEMONIC\(\|[01234]\|[01234]EX\)(/!d' \ 369 -e ':look-for-end-of-invocation' \ 370 -e '/)/bend-of-invocation' \ 371 -e 'N' \ 372 -e 'blook-for-end-of-invocation' \ 373 -e ':end-of-invocation' \ 374 -e 's/\n/ /g' \ 375 -e 's/ */ /g' \ 369 376 -e 's/^.*IEMOP_MNEMONIC\(\|[01234]\|[01234]EX\)(/IEM_DO_INSTR_STAT\1(/' \ 370 377 -e 's/;.*$(DOLLAR)//' \ -
trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsPython.py
r67042 r67072 206 206 ## - 2: disassembler format string version of the type. 207 207 ## - 3: disassembler OP_PARAM_XXX (XXX only). 208 ## - 4: IEM form matching instruction. 208 209 ## 209 210 ## Note! See the A.2.1 in SDM vol 2 for the type names. 210 211 g_kdOpTypes = { 211 212 # Fixed addresses 212 'Ap': ( 'IDX_ParseImmAddrF', 'imm', '%Ap', 'Ap', ),213 'Ap': ( 'IDX_ParseImmAddrF', 'imm', '%Ap', 'Ap', 'FIXED', ), 213 214 214 215 # ModR/M.rm 215 'Eb': ( 'IDX_UseModRM', 'rm', '%Eb', 'Eb', ),216 'Ed': ( 'IDX_UseModRM', 'rm', '%Ed', 'Ed', ),217 'Ed_WO': ( 'IDX_UseModRM', 'rm', '%Ed', 'Ed', ),218 'Eq': ( 'IDX_UseModRM', 'rm', '%Eq', 'Eq', ),219 'Eq_WO': ( 'IDX_UseModRM', 'rm', '%Eq', 'Eq', ),220 'Ew': ( 'IDX_UseModRM', 'rm', '%Ew', 'Ew', ),221 'Ev': ( 'IDX_UseModRM', 'rm', '%Ev', 'Ev', ),222 'Qq': ( 'IDX_UseModRM', 'rm', '%Qq', 'Qq', ),223 'Qq_WO': ( 'IDX_UseModRM', 'rm', '%Qq', 'Qq', ),224 'Wss': ( 'IDX_UseModRM', 'rm', '%Wss', 'Wss', ),225 'Wss_WO': ( 'IDX_UseModRM', 'rm', '%Wss', 'Wss', ),226 'Wsd': ( 'IDX_UseModRM', 'rm', '%Wsd', 'Wsd', ),227 'Wsd_WO': ( 'IDX_UseModRM', 'rm', '%Wsd', 'Wsd', ),228 'Wps': ( 'IDX_UseModRM', 'rm', '%Wps', 'Wps', ),229 'Wps_WO': ( 'IDX_UseModRM', 'rm', '%Wps', 'Wps', ),230 'Wpd': ( 'IDX_UseModRM', 'rm', '%Wpd', 'Wpd', ),231 'Wpd_WO': ( 'IDX_UseModRM', 'rm', '%Wpd', 'Wpd', ),232 'Wdq': ( 'IDX_UseModRM', 'rm', '%Wdq', 'Wdq', ),233 'Wdq_WO': ( 'IDX_UseModRM', 'rm', '%Wdq', 'Wdq', ),234 'Wq': ( 'IDX_UseModRM', 'rm', '%Wq', 'Wq', ),235 'Wq_WO': ( 'IDX_UseModRM', 'rm', '%Wq', 'Wq', ),236 'WqZxReg_WO': ( 'IDX_UseModRM', 'rm', '%Wq', 'Wq', ),237 'Wx': ( 'IDX_UseModRM', 'rm', '%Wx', 'Wx', ),238 'Wx_WO': ( 'IDX_UseModRM', 'rm', '%Wx', 'Wx', ),216 'Eb': ( 'IDX_UseModRM', 'rm', '%Eb', 'Eb', 'RM', ), 217 'Ed': ( 'IDX_UseModRM', 'rm', '%Ed', 'Ed', 'RM', ), 218 'Ed_WO': ( 'IDX_UseModRM', 'rm', '%Ed', 'Ed', 'RM', ), 219 'Eq': ( 'IDX_UseModRM', 'rm', '%Eq', 'Eq', 'RM', ), 220 'Eq_WO': ( 'IDX_UseModRM', 'rm', '%Eq', 'Eq', 'RM', ), 221 'Ew': ( 'IDX_UseModRM', 'rm', '%Ew', 'Ew', 'RM', ), 222 'Ev': ( 'IDX_UseModRM', 'rm', '%Ev', 'Ev', 'RM', ), 223 'Qq': ( 'IDX_UseModRM', 'rm', '%Qq', 'Qq', 'RM', ), 224 'Qq_WO': ( 'IDX_UseModRM', 'rm', '%Qq', 'Qq', 'RM', ), 225 'Wss': ( 'IDX_UseModRM', 'rm', '%Wss', 'Wss', 'RM', ), 226 'Wss_WO': ( 'IDX_UseModRM', 'rm', '%Wss', 'Wss', 'RM', ), 227 'Wsd': ( 'IDX_UseModRM', 'rm', '%Wsd', 'Wsd', 'RM', ), 228 'Wsd_WO': ( 'IDX_UseModRM', 'rm', '%Wsd', 'Wsd', 'RM', ), 229 'Wps': ( 'IDX_UseModRM', 'rm', '%Wps', 'Wps', 'RM', ), 230 'Wps_WO': ( 'IDX_UseModRM', 'rm', '%Wps', 'Wps', 'RM', ), 231 'Wpd': ( 'IDX_UseModRM', 'rm', '%Wpd', 'Wpd', 'RM', ), 232 'Wpd_WO': ( 'IDX_UseModRM', 'rm', '%Wpd', 'Wpd', 'RM', ), 233 'Wdq': ( 'IDX_UseModRM', 'rm', '%Wdq', 'Wdq', 'RM', ), 234 'Wdq_WO': ( 'IDX_UseModRM', 'rm', '%Wdq', 'Wdq', 'RM', ), 235 'Wq': ( 'IDX_UseModRM', 'rm', '%Wq', 'Wq', 'RM', ), 236 'Wq_WO': ( 'IDX_UseModRM', 'rm', '%Wq', 'Wq', 'RM', ), 237 'WqZxReg_WO': ( 'IDX_UseModRM', 'rm', '%Wq', 'Wq', 'RM', ), 238 'Wx': ( 'IDX_UseModRM', 'rm', '%Wx', 'Wx', 'RM', ), 239 'Wx_WO': ( 'IDX_UseModRM', 'rm', '%Wx', 'Wx', 'RM', ), 239 240 240 241 # ModR/M.rm - register only. 241 'Uq': ( 'IDX_UseModRM', 'rm', '%Uq', 'Uq', ),242 'UqHi': ( 'IDX_UseModRM', 'rm', '%Uq', 'UqHi', ),243 'Uss': ( 'IDX_UseModRM', 'rm', '%Uss', 'Uss', ),244 'Uss_WO': ( 'IDX_UseModRM', 'rm', '%Uss', 'Uss', ),245 'Usd': ( 'IDX_UseModRM', 'rm', '%Usd', 'Usd', ),246 'Usd_WO': ( 'IDX_UseModRM', 'rm', '%Usd', 'Usd', ),247 'Nq': ( 'IDX_UseModRM', 'rm', '%Qq', 'Nq', ),242 'Uq': ( 'IDX_UseModRM', 'rm', '%Uq', 'Uq', 'REG' ), 243 'UqHi': ( 'IDX_UseModRM', 'rm', '%Uq', 'UqHi', 'REG' ), 244 'Uss': ( 'IDX_UseModRM', 'rm', '%Uss', 'Uss', 'REG' ), 245 'Uss_WO': ( 'IDX_UseModRM', 'rm', '%Uss', 'Uss', 'REG' ), 246 'Usd': ( 'IDX_UseModRM', 'rm', '%Usd', 'Usd', 'REG' ), 247 'Usd_WO': ( 'IDX_UseModRM', 'rm', '%Usd', 'Usd', 'REG' ), 248 'Nq': ( 'IDX_UseModRM', 'rm', '%Qq', 'Nq', 'REG' ), 248 249 249 250 # ModR/M.rm - memory only. 250 'Ma': ( 'IDX_UseModRM', 'rm', '%Ma', 'Ma', ), ##< Only used by BOUND.251 'Mb_RO': ( 'IDX_UseModRM', 'rm', '%Mb', 'Mb', ),252 'Md': ( 'IDX_UseModRM', 'rm', '%Md', 'Md', ),253 'Md_RO': ( 'IDX_UseModRM', 'rm', '%Md', 'Md', ),254 'Md_WO': ( 'IDX_UseModRM', 'rm', '%Md', 'Md', ),255 'Mdq': ( 'IDX_UseModRM', 'rm', '%Mdq', 'Mdq', ),256 'Mdq_WO': ( 'IDX_UseModRM', 'rm', '%Mdq', 'Mdq', ),257 'Mq': ( 'IDX_UseModRM', 'rm', '%Mq', 'Mq', ),258 'Mq_WO': ( 'IDX_UseModRM', 'rm', '%Mq', 'Mq', ),259 'Mps_WO': ( 'IDX_UseModRM', 'rm', '%Mps', 'Mps', ),260 'Mpd_WO': ( 'IDX_UseModRM', 'rm', '%Mpd', 'Mpd', ),261 'Mx': ( 'IDX_UseModRM', 'rm', '%Mx', 'Mx', ),262 'Mx_WO': ( 'IDX_UseModRM', 'rm', '%Mx', 'Mx', ),263 'M_RO': ( 'IDX_UseModRM', 'rm', '%M', 'M', ),264 'M_RW': ( 'IDX_UseModRM', 'rm', '%M', 'M', ),251 'Ma': ( 'IDX_UseModRM', 'rm', '%Ma', 'Ma', 'MEM', ), ##< Only used by BOUND. 252 'Mb_RO': ( 'IDX_UseModRM', 'rm', '%Mb', 'Mb', 'MEM', ), 253 'Md': ( 'IDX_UseModRM', 'rm', '%Md', 'Md', 'MEM', ), 254 'Md_RO': ( 'IDX_UseModRM', 'rm', '%Md', 'Md', 'MEM', ), 255 'Md_WO': ( 'IDX_UseModRM', 'rm', '%Md', 'Md', 'MEM', ), 256 'Mdq': ( 'IDX_UseModRM', 'rm', '%Mdq', 'Mdq', 'MEM', ), 257 'Mdq_WO': ( 'IDX_UseModRM', 'rm', '%Mdq', 'Mdq', 'MEM', ), 258 'Mq': ( 'IDX_UseModRM', 'rm', '%Mq', 'Mq', 'MEM', ), 259 'Mq_WO': ( 'IDX_UseModRM', 'rm', '%Mq', 'Mq', 'MEM', ), 260 'Mps_WO': ( 'IDX_UseModRM', 'rm', '%Mps', 'Mps', 'MEM', ), 261 'Mpd_WO': ( 'IDX_UseModRM', 'rm', '%Mpd', 'Mpd', 'MEM', ), 262 'Mx': ( 'IDX_UseModRM', 'rm', '%Mx', 'Mx', 'MEM', ), 263 'Mx_WO': ( 'IDX_UseModRM', 'rm', '%Mx', 'Mx', 'MEM', ), 264 'M_RO': ( 'IDX_UseModRM', 'rm', '%M', 'M', 'MEM', ), 265 'M_RW': ( 'IDX_UseModRM', 'rm', '%M', 'M', 'MEM', ), 265 266 266 267 # ModR/M.reg 267 'Gb': ( 'IDX_UseModRM', 'reg', '%Gb', 'Gb', ),268 'Gw': ( 'IDX_UseModRM', 'reg', '%Gw', 'Gw', ),269 'Gv': ( 'IDX_UseModRM', 'reg', '%Gv', 'Gv', ),270 'Gv_RO': ( 'IDX_UseModRM', 'reg', '%Gv', 'Gv', ),271 'Pd': ( 'IDX_UseModRM', 'reg', '%Pd', 'Pd', ),272 'PdZx_WO': ( 'IDX_UseModRM', 'reg', '%Pd', 'PdZx', ),273 'Pq': ( 'IDX_UseModRM', 'reg', '%Pq', 'Pq', ),274 'Pq_WO': ( 'IDX_UseModRM', 'reg', '%Pq', 'Pq', ),275 'Vd': ( 'IDX_UseModRM', 'reg', '%Vd', 'Vd', ),276 'Vd_WO': ( 'IDX_UseModRM', 'reg', '%Vd', 'Vd', ),277 'VdZx_WO': ( 'IDX_UseModRM', 'reg', '%Vd', 'Vd', ),278 'Vdq': ( 'IDX_UseModRM', 'reg', '%Vdq', 'Vdq', ),279 'Vss': ( 'IDX_UseModRM', 'reg', '%Vss', 'Vss', ),280 'Vss_WO': ( 'IDX_UseModRM', 'reg', '%Vss', 'Vss', ),281 'VssZx_WO': ( 'IDX_UseModRM', 'reg', '%Vss', 'Vss', ),282 'Vsd': ( 'IDX_UseModRM', 'reg', '%Vsd', 'Vsd', ),283 'Vsd_WO': ( 'IDX_UseModRM', 'reg', '%Vsd', 'Vsd', ),284 'VsdZx_WO': ( 'IDX_UseModRM', 'reg', '%Vsd', 'Vsd', ),285 'Vps': ( 'IDX_UseModRM', 'reg', '%Vps', 'Vps', ),286 'Vps_WO': ( 'IDX_UseModRM', 'reg', '%Vps', 'Vps', ),287 'Vpd': ( 'IDX_UseModRM', 'reg', '%Vpd', 'Vpd', ),288 'Vpd_WO': ( 'IDX_UseModRM', 'reg', '%Vpd', 'Vpd', ),289 'Vq': ( 'IDX_UseModRM', 'reg', '%Vq', 'Vq', ),290 'Vq_WO': ( 'IDX_UseModRM', 'reg', '%Vq', 'Vq', ),291 'Vdq_WO': ( 'IDX_UseModRM', 'reg', '%Vdq', 'Vdq', ),292 'VqHi': ( 'IDX_UseModRM', 'reg', '%Vdq', 'VdqHi', ),293 'VqHi_WO': ( 'IDX_UseModRM', 'reg', '%Vdq', 'VdqHi', ),294 'VqZx_WO': ( 'IDX_UseModRM', 'reg', '%Vq', 'VqZx', ),295 'Vx': ( 'IDX_UseModRM', 'reg', '%Vx', 'Vx', ),296 'Vx_WO': ( 'IDX_UseModRM', 'reg', '%Vx', 'Vx', ),268 'Gb': ( 'IDX_UseModRM', 'reg', '%Gb', 'Gb', '', ), 269 'Gw': ( 'IDX_UseModRM', 'reg', '%Gw', 'Gw', '', ), 270 'Gv': ( 'IDX_UseModRM', 'reg', '%Gv', 'Gv', '', ), 271 'Gv_RO': ( 'IDX_UseModRM', 'reg', '%Gv', 'Gv', '', ), 272 'Pd': ( 'IDX_UseModRM', 'reg', '%Pd', 'Pd', '', ), 273 'PdZx_WO': ( 'IDX_UseModRM', 'reg', '%Pd', 'PdZx', '', ), 274 'Pq': ( 'IDX_UseModRM', 'reg', '%Pq', 'Pq', '', ), 275 'Pq_WO': ( 'IDX_UseModRM', 'reg', '%Pq', 'Pq', '', ), 276 'Vd': ( 'IDX_UseModRM', 'reg', '%Vd', 'Vd', '', ), 277 'Vd_WO': ( 'IDX_UseModRM', 'reg', '%Vd', 'Vd', '', ), 278 'VdZx_WO': ( 'IDX_UseModRM', 'reg', '%Vd', 'Vd', '', ), 279 'Vdq': ( 'IDX_UseModRM', 'reg', '%Vdq', 'Vdq', '', ), 280 'Vss': ( 'IDX_UseModRM', 'reg', '%Vss', 'Vss', '', ), 281 'Vss_WO': ( 'IDX_UseModRM', 'reg', '%Vss', 'Vss', '', ), 282 'VssZx_WO': ( 'IDX_UseModRM', 'reg', '%Vss', 'Vss', '', ), 283 'Vsd': ( 'IDX_UseModRM', 'reg', '%Vsd', 'Vsd', '', ), 284 'Vsd_WO': ( 'IDX_UseModRM', 'reg', '%Vsd', 'Vsd', '', ), 285 'VsdZx_WO': ( 'IDX_UseModRM', 'reg', '%Vsd', 'Vsd', '', ), 286 'Vps': ( 'IDX_UseModRM', 'reg', '%Vps', 'Vps', '', ), 287 'Vps_WO': ( 'IDX_UseModRM', 'reg', '%Vps', 'Vps', '', ), 288 'Vpd': ( 'IDX_UseModRM', 'reg', '%Vpd', 'Vpd', '', ), 289 'Vpd_WO': ( 'IDX_UseModRM', 'reg', '%Vpd', 'Vpd', '', ), 290 'Vq': ( 'IDX_UseModRM', 'reg', '%Vq', 'Vq', '', ), 291 'Vq_WO': ( 'IDX_UseModRM', 'reg', '%Vq', 'Vq', '', ), 292 'Vdq_WO': ( 'IDX_UseModRM', 'reg', '%Vdq', 'Vdq', '', ), 293 'VqHi': ( 'IDX_UseModRM', 'reg', '%Vdq', 'VdqHi', '', ), 294 'VqHi_WO': ( 'IDX_UseModRM', 'reg', '%Vdq', 'VdqHi', '', ), 295 'VqZx_WO': ( 'IDX_UseModRM', 'reg', '%Vq', 'VqZx', '', ), 296 'Vx': ( 'IDX_UseModRM', 'reg', '%Vx', 'Vx', '', ), 297 'Vx_WO': ( 'IDX_UseModRM', 'reg', '%Vx', 'Vx', '', ), 297 298 298 299 # VEX.vvvv 299 'HssHi': ( 'IDX_UseModRM', 'vvvv', '%Hx', 'HssHi', ),300 'HsdHi': ( 'IDX_UseModRM', 'vvvv', '%Hx', 'HsdHi', ),301 'HqHi': ( 'IDX_UseModRM', 'vvvv', '%Hq', 'HqHi', ),300 'HssHi': ( 'IDX_UseModRM', 'vvvv', '%Hx', 'HssHi', 'V', ), 301 'HsdHi': ( 'IDX_UseModRM', 'vvvv', '%Hx', 'HsdHi', 'V', ), 302 'HqHi': ( 'IDX_UseModRM', 'vvvv', '%Hq', 'HqHi', 'V', ), 302 303 303 304 # Immediate values. 304 'Ib': ( 'IDX_ParseImmByte', 'imm', '%Ib', 'Ib', 305 'Iw': ( 'IDX_ParseImmUshort', 'imm', '%Iw', 'Iw', ),306 'Id': ( 'IDX_ParseImmUlong', 'imm', '%Id', 'Id', ),307 'Iq': ( 'IDX_ParseImmQword', 'imm', '%Iq', 'Iq', ),308 'Iv': ( 'IDX_ParseImmV', 'imm', '%Iv', 'Iv', ), ##< o16: word, o32: dword, o64: qword309 'Iz': ( 'IDX_ParseImmZ', 'imm', '%Iz', 'Iz', ), ##< o16: word, o32|o64:dword305 'Ib': ( 'IDX_ParseImmByte', 'imm', '%Ib', 'Ib', '', ), ##< NB! Could be IDX_ParseImmByteSX for some instrs. 306 'Iw': ( 'IDX_ParseImmUshort', 'imm', '%Iw', 'Iw', '', ), 307 'Id': ( 'IDX_ParseImmUlong', 'imm', '%Id', 'Id', '', ), 308 'Iq': ( 'IDX_ParseImmQword', 'imm', '%Iq', 'Iq', '', ), 309 'Iv': ( 'IDX_ParseImmV', 'imm', '%Iv', 'Iv', '', ), ##< o16: word, o32: dword, o64: qword 310 'Iz': ( 'IDX_ParseImmZ', 'imm', '%Iz', 'Iz', '', ), ##< o16: word, o32|o64:dword 310 311 311 312 # Address operands (no ModR/M). 312 'Ob': ( 'IDX_ParseImmAddr', 'imm', '%Ob', 'Ob', ),313 'Ov': ( 'IDX_ParseImmAddr', 'imm', '%Ov', 'Ov', ),313 'Ob': ( 'IDX_ParseImmAddr', 'imm', '%Ob', 'Ob', '', ), 314 'Ov': ( 'IDX_ParseImmAddr', 'imm', '%Ov', 'Ov', '', ), 314 315 315 316 # Relative jump targets 316 'Jb': ( 'IDX_ParseImmBRel', 'imm', '%Jb', 'Jb', ),317 'Jv': ( 'IDX_ParseImmVRel', 'imm', '%Jv', 'Jv', ),317 'Jb': ( 'IDX_ParseImmBRel', 'imm', '%Jb', 'Jb', '', ), 318 'Jv': ( 'IDX_ParseImmVRel', 'imm', '%Jv', 'Jv', '', ), 318 319 319 320 # DS:rSI 320 'Xb': ( 'IDX_ParseXb', 'rSI', '%eSI', 'Xb', ),321 'Xv': ( 'IDX_ParseXv', 'rSI', '%eSI', 'Xv', ),321 'Xb': ( 'IDX_ParseXb', 'rSI', '%eSI', 'Xb', '', ), 322 'Xv': ( 'IDX_ParseXv', 'rSI', '%eSI', 'Xv', '', ), 322 323 # ES:rDI 323 'Yb': ( 'IDX_ParseYb', 'rDI', '%eDI', 'Yb', ),324 'Yv': ( 'IDX_ParseYv', 'rDI', '%eDI', 'Yv', ),325 326 'Fv': ( 'IDX_ParseFixedReg', 'rFLAGS', '%Fv', 'Fv', ),324 'Yb': ( 'IDX_ParseYb', 'rDI', '%eDI', 'Yb', '', ), 325 'Yv': ( 'IDX_ParseYv', 'rDI', '%eDI', 'Yv', '', ), 326 327 'Fv': ( 'IDX_ParseFixedReg', 'rFLAGS', '%Fv', 'Fv', '', ), 327 328 328 329 # Fixed registers. 329 'AL': ( 'IDX_ParseFixedReg', 'AL', 'al', 'REG_AL', ),330 'rAX': ( 'IDX_ParseFixedReg', 'rAX', '%eAX', 'REG_EAX', ),331 'CS': ( 'IDX_ParseFixedReg', 'CS', 'cs', 'REG_CS', ), # 8086: push CS332 'DS': ( 'IDX_ParseFixedReg', 'DS', 'ds', 'REG_DS', ),333 'ES': ( 'IDX_ParseFixedReg', 'ES', 'es', 'REG_ES', ),334 'FS': ( 'IDX_ParseFixedReg', 'FS', 'fs', 'REG_FS', ),335 'GS': ( 'IDX_ParseFixedReg', 'GS', 'gs', 'REG_GS', ),336 'SS': ( 'IDX_ParseFixedReg', 'SS', 'ss', 'REG_SS', ),330 'AL': ( 'IDX_ParseFixedReg', 'AL', 'al', 'REG_AL', '', ), 331 'rAX': ( 'IDX_ParseFixedReg', 'rAX', '%eAX', 'REG_EAX', '', ), 332 'CS': ( 'IDX_ParseFixedReg', 'CS', 'cs', 'REG_CS', '', ), # 8086: push CS 333 'DS': ( 'IDX_ParseFixedReg', 'DS', 'ds', 'REG_DS', '', ), 334 'ES': ( 'IDX_ParseFixedReg', 'ES', 'es', 'REG_ES', '', ), 335 'FS': ( 'IDX_ParseFixedReg', 'FS', 'fs', 'REG_FS', '', ), 336 'GS': ( 'IDX_ParseFixedReg', 'GS', 'gs', 'REG_GS', '', ), 337 'SS': ( 'IDX_ParseFixedReg', 'SS', 'ss', 'REG_SS', '', ), 337 338 }; 338 339 … … 342 343 343 344 ## IEMFORM_XXX mappings. 344 g_kdIemForms = { # sEncoding, [ sWhere1, ... ] 345 'RM': ( 'ModR/M', [ 'reg', 'rm' ], ), 346 'RM_REG': ( 'ModR/M', [ 'reg', 'rm' ], ), 347 'RM_MEM': ( 'ModR/M', [ 'reg', 'rm' ], ), 348 'MR': ( 'ModR/M', [ 'rm', 'reg' ], ), 349 'MR_REG': ( 'ModR/M', [ 'rm', 'reg' ], ), 350 'MR_MEM': ( 'ModR/M', [ 'rm', 'reg' ], ), 351 'M': ( 'ModR/M', [ 'rm', ], ), 352 'M_REG': ( 'ModR/M', [ 'rm', ], ), 353 'M_MEM': ( 'ModR/M', [ 'rm', ], ), 354 'R': ( 'ModR/M', [ 'reg', ], ), 355 356 'VEX_RM': ( 'VEX.ModR/M', [ 'reg', 'rm' ], ), 357 'VEX_RM_REG': ( 'VEX.ModR/M', [ 'reg', 'rm' ], ), 358 'VEX_RM_MEM': ( 'VEX.ModR/M', [ 'reg', 'rm' ], ), 359 'VEX_XM': ( 'VEX.ModR/M', [ 'reg', 'rm' ], ), # same as VEX_RM_MEM, typo? 360 'VEX_MR': ( 'VEX.ModR/M', [ 'rm', 'reg' ], ), 361 'VEX_MR_REG': ( 'VEX.ModR/M', [ 'rm', 'reg' ], ), 362 'VEX_MR_MEM': ( 'VEX.ModR/M', [ 'rm', 'reg' ], ), 363 'VEX_M': ( 'VEX.ModR/M', [ 'rm', ], ), 364 'VEX_M_REG': ( 'VEX.ModR/M', [ 'rm', ], ), 365 'VEX_M_MEM': ( 'VEX.ModR/M', [ 'rm', ], ), 366 'VEX_R': ( 'VEX.ModR/M', [ 'reg', ], ), 367 'VEX_RVM': ( 'VEX.ModR/M', [ 'reg', 'vvvv', 'rm'], ), 368 'VEX_RVM_REG': ( 'VEX.ModR/M', [ 'reg', 'vvvv', 'rm'], ), 369 'VEX_RVM_MEM': ( 'VEX.ModR/M', [ 'reg', 'vvvv', 'rm'], ), 370 'VEX_MVR': ( 'VEX.ModR/M', [ 'rm', 'vvvv', 'reg'], ), 371 'VEX_MVR_REG': ( 'VEX.ModR/M', [ 'rm', 'vvvv', 'reg'], ), 372 'VEX_MVR_MEM': ( 'VEX.ModR/M', [ 'rm', 'vvvv', 'reg'], ), 373 374 'FIXED': ( 'fixed', None, ) 345 g_kdIemForms = { # sEncoding, [ sWhere1, ... ] opcodesub ), 346 'RM': ( 'ModR/M', [ 'reg', 'rm' ], '', ), 347 'RM_REG': ( 'ModR/M', [ 'reg', 'rm' ], '11 mr/reg', ), 348 'RM_MEM': ( 'ModR/M', [ 'reg', 'rm' ], '!11 mr/reg', ), 349 'MR': ( 'ModR/M', [ 'rm', 'reg' ], '', ), 350 'MR_REG': ( 'ModR/M', [ 'rm', 'reg' ], '11 mr/reg', ), 351 'MR_MEM': ( 'ModR/M', [ 'rm', 'reg' ], '!11 mr/reg', ), 352 'M': ( 'ModR/M', [ 'rm', ], '', ), 353 'M_REG': ( 'ModR/M', [ 'rm', ], '', ), 354 'M_MEM': ( 'ModR/M', [ 'rm', ], '', ), 355 'R': ( 'ModR/M', [ 'reg', ], '', ), 356 357 'VEX_RM': ( 'VEX.ModR/M', [ 'reg', 'rm' ], '', ), 358 'VEX_RM_REG': ( 'VEX.ModR/M', [ 'reg', 'rm' ], '11 mr/reg', ), 359 'VEX_RM_MEM': ( 'VEX.ModR/M', [ 'reg', 'rm' ], '!11 mr/reg', ), 360 'VEX_MR': ( 'VEX.ModR/M', [ 'rm', 'reg' ], '', ), 361 'VEX_MR_REG': ( 'VEX.ModR/M', [ 'rm', 'reg' ], '11 mr/reg', ), 362 'VEX_MR_MEM': ( 'VEX.ModR/M', [ 'rm', 'reg' ], '!11 mr/reg', ), 363 'VEX_M': ( 'VEX.ModR/M', [ 'rm', ], '' ), 364 'VEX_M_REG': ( 'VEX.ModR/M', [ 'rm', ], '' ), 365 'VEX_M_MEM': ( 'VEX.ModR/M', [ 'rm', ], '' ), 366 'VEX_R': ( 'VEX.ModR/M', [ 'reg', ], '' ), 367 'VEX_RVM': ( 'VEX.ModR/M', [ 'reg', 'vvvv', 'rm' ], '', ), 368 'VEX_RVM_REG': ( 'VEX.ModR/M', [ 'reg', 'vvvv', 'rm' ], '11 mr/reg', ), 369 'VEX_RVM_MEM': ( 'VEX.ModR/M', [ 'reg', 'vvvv', 'rm' ], '!11 mr/reg', ), 370 'VEX_MVR': ( 'VEX.ModR/M', [ 'rm', 'vvvv', 'reg' ], '', ), 371 'VEX_MVR_REG': ( 'VEX.ModR/M', [ 'rm', 'vvvv', 'reg' ], '11 mr/reg', ), 372 'VEX_MVR_MEM': ( 'VEX.ModR/M', [ 'rm', 'vvvv', 'reg' ], '!11 mr/reg', ), 373 374 'FIXED': ( 'fixed', None, '', ), 375 375 }; 376 376 … … 394 394 395 395 ## Special \@opcodesub tag values. 396 ## The first value is the real value for aliases. 397 ## The second value is for bs3cg1. 396 398 g_kdSubOpcodes = { 397 'none': [ None, ], 398 '11 mr/reg': [ '11 mr/reg', ], 399 '11': [ '11 mr/reg', ], ##< alias 400 '!11 mr/reg': [ '!11 mr/reg', ], 401 '!11': [ '!11 mr/reg', ], ##< alias 402 'rex.w=0': [ 'rex.w=0', ], 403 'w=0': [ 'rex.w=0', ], ##< alias 404 'rex.w=1': [ 'rex.w=1', ], 405 'w=1': [ 'rex.w=1', ], ##< alias 399 'none': [ None, '', ], 400 '11 mr/reg': [ '11 mr/reg', '', ], 401 '11': [ '11 mr/reg', '', ], ##< alias 402 '!11 mr/reg': [ '!11 mr/reg', '', ], 403 '!11': [ '!11 mr/reg', '', ], ##< alias 404 'rex.w=0': [ 'rex.w=0', 'WZ', ], 405 'w=0': [ 'rex.w=0', '', ], ##< alias 406 'rex.w=1': [ 'rex.w=1', 'WNZ', ], 407 'w=1': [ 'rex.w=1', '', ], ##< alias 408 'vex.l=0': [ 'vex.l=0', 'L0', ], 409 'vex.l=1': [ 'vex.l=0', 'L1', ], 410 '11 mr/reg vex.l=0': [ '11 mr/reg vex.l=0', 'L0', ], 411 '11 mr/reg vex.l=1': [ '11 mr/reg vex.l=1', 'L1', ], 412 '!11 mr/reg vex.l=0': [ '!11 mr/reg vex.l=0', 'L0', ], 413 '!11 mr/reg vex.l=1': [ '!11 mr/reg vex.l=1', 'L1', ], 406 414 }; 407 415 … … 463 471 'xsave': 'X86_CPUID_FEATURE_ECX_XSAVE', 464 472 'avx': 'X86_CPUID_FEATURE_ECX_AVX', 473 'avx2': 'X86_CPUID_STEXT_FEATURE_EBX_AVX2', 465 474 'f16c': 'X86_CPUID_FEATURE_ECX_F16C', 466 475 'rdrand': 'X86_CPUID_FEATURE_ECX_RDRAND', … … 512 521 'ignores_rexw': '', ##< Ignores REX.W. 513 522 'ignores_op_sizes': '', ##< Shorthand for "ignores_oz_pfx | ignores_op_sizes". 514 'ignores_vex_l': '', ##< Ignores VEX.L.515 523 'vex_l_zero': '', ##< VEX.L must be 0. 524 'vex_l_ignored': '', ##< VEX.L is ignored. 516 525 'lock_allowed': '', ##< Lock prefix allowed. 517 526 }; … … 1685 1694 return False; 1686 1695 1696 def errorOnLine(self, iLine, sMessage): 1697 """ 1698 Adds an error. 1699 returns False; 1700 """ 1701 self.asErrors.append(u'%s:%d: error: %s\n' % (self.sSrcFile, iLine, sMessage,)); 1702 return False; 1703 1687 1704 def errorComment(self, iLineInComment, sMessage): 1688 1705 """ … … 2165 2182 """ 2166 2183 Tag: \@opcodesub 2167 Value: none | 11 mr/reg | !11 mr/reg 2184 Value: none | 11 mr/reg | !11 mr/reg | rex.w=0 | rex.w=1 | vex.l=0 | vex.l=1 2185 | 11 mr/reg vex.l=0 | 11 mr/reg vex.l=1 | !11 mr/reg vex.l=0 | !11 mr/reg vex.l=1 2168 2186 2169 2187 This is a simple way of dealing with encodings where the mod=3 and mod!=3 … … 2894 2912 off = offOpen + 1; 2895 2913 offStart = off; 2914 chQuote = None; 2896 2915 while cDepth > 0: 2897 2916 if off >= len(sInvocation): 2898 2917 if iLine >= len(self.asLines): 2899 return self.error('macro invocation beyond end of file'); 2918 self.error('macro invocation beyond end of file'); 2919 return (off, asRet); 2900 2920 sInvocation += self.asLines[iLine]; 2901 2921 iLine += 1; 2902 2922 ch = sInvocation[off]; 2903 2923 2904 if ch == ',' or ch == ')': 2924 if chQuote: 2925 if ch == '\\' and off + 1 < len(sInvocation): 2926 off += 1; 2927 elif ch == chQuote: 2928 chQuote = None; 2929 elif ch == '"' or ch == '\'': 2930 chQuote = ch; 2931 elif ch == ',' or ch == ')': 2905 2932 if cDepth == 1: 2906 2933 asRet.append(sInvocation[offStart:off].strip()); … … 3021 3048 self.error('%s: current instruction @op%u and a_Form location does not match: %s vs %s (%s)' 3022 3049 % (sMacro, iOperand + 1, oInstr.aoOperands[iOperand].sWhere, sWhere, sForm,)); 3050 sOpFormMatch = g_kdOpTypes[oInstr.aoOperands[iOperand].sType][4]; 3051 if (sOpFormMatch in [ 'REG', 'MEM', ] and sForm.find('_' + sOpFormMatch) < 0) \ 3052 or (sOpFormMatch in [ 'FIXED', ] and sForm.find(sOpFormMatch) < 0) \ 3053 or (sOpFormMatch == 'RM' and (sForm.find('_MEM') > 0 or sForm.find('_REG') > 0) ) \ 3054 or (sOpFormMatch == 'V' and ( not (sForm.find('VEX') > 0 or sForm.find('XOP')) \ 3055 or sForm.replace('VEX','').find('V') < 0) ): 3056 self.error('%s: current instruction @op%u and a_Form type does not match: %s/%s vs %s' 3057 % (sMacro, iOperand + 1, oInstr.aoOperands[iOperand].sType, sOpFormMatch, sForm, )); 3058 3059 # Check @opcodesub 3060 if oInstr.sSubOpcode \ 3061 and g_kdIemForms[sForm][2] \ 3062 and oInstr.sSubOpcode.find(g_kdIemForms[sForm][2]) < 0: 3063 self.error('%s: current instruction @opcodesub and a_Form does not match: %s vs %s (%s)' 3064 % (sMacro, oInstr.sSubOpcode, g_kdIemForms[sForm][2], sForm,)); 3023 3065 3024 3066 # Stats. … … 3053 3095 elif sHint != '0': 3054 3096 self.error('%s: expected a_fIemHints value: %s' % (sMacro, sHint,)); 3055 3056 3097 3057 3098 _ = sAsm; … … 3099 3140 self.doneInstructions(); 3100 3141 return True; 3142 3143 # IEMOP_HLP_DONE_VEX_DECODING_* 3144 asArgs = self.findAndParseFirstMacroInvocation(sCode, 3145 [ 'IEMOP_HLP_DONE_VEX_DECODING', 3146 'IEMOP_HLP_DONE_VEX_DECODING_L0', 3147 'IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV', 3148 'IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV', 3149 ]); 3150 if asArgs is not None: 3151 sMacro = asArgs[0]; 3152 if sMacro in ('IEMOP_HLP_DONE_VEX_DECODING_L0', 'IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV', ): 3153 for oInstr in self.aoCurInstrs: 3154 if 'vex_l_zero' not in oInstr.dHints: 3155 if oInstr.iLineMnemonicMacro >= 0: 3156 self.errorOnLine(oInstr.iLineMnemonicMacro, 3157 'Missing IEMOPHINT_VEX_L_ZERO! (%s on line %d)' % (sMacro, self.iLine,)); 3158 oInstr.dHints['vex_l_zero'] = True; 3159 return True; 3160 3161 # 3162 # IEMOP_MNEMONIC* 3163 # 3101 3164 3102 3165 # IEMOP_MNEMONIC(a_Stats, a_szMnemonic) IEMOP_INC_STATS(a_Stats) -
trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap1.cpp.h
r67037 r67072 221 221 * @note HssHi refers to bits 127:32. 222 222 */ 223 IEMOP_MNEMONIC3(VEX_RVM , VMOVSS, vmovss, Vss_WO, HssHi, Uss, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_IGNORES_VEX_L);223 IEMOP_MNEMONIC3(VEX_RVM_REG, VMOVSS, vmovss, Vss_WO, HssHi, Uss, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED); 224 224 IEMOP_HLP_DONE_VEX_DECODING(); 225 225 IEM_MC_BEGIN(0, 0); … … 239 239 * @opcode 0x10 240 240 * @oppfx 0xf3 241 * @opcodesub 11 mr/reg241 * @opcodesub !11 mr/reg 242 242 * @opcpuid avx 243 243 * @opgroup og_avx_simdfp_datamove … … 247 247 * @optest op1=0 op2=-22 -> op1=-22 248 248 */ 249 IEMOP_MNEMONIC2(VEX_ XM, VMOVSS, vmovss, VssZx_WO, Md, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_IGNORES_VEX_L);249 IEMOP_MNEMONIC2(VEX_RM_MEM, VMOVSS, vmovss, VssZx_WO, Md, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED); 250 250 IEM_MC_BEGIN(0, 2); 251 251 IEM_MC_LOCAL(uint32_t, uSrc); … … 287 287 * @optest op1=3 op2=0x42 op3=0x77 -> op1=0x420000000000000077 288 288 */ 289 IEMOP_MNEMONIC3(VEX_RVM , VMOVSD, vmovsd, Vsd_WO, HsdHi, Usd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_IGNORES_VEX_L);289 IEMOP_MNEMONIC3(VEX_RVM_REG, VMOVSD, vmovsd, Vsd_WO, HsdHi, Usd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED); 290 290 IEMOP_HLP_DONE_VEX_DECODING(); 291 291 IEM_MC_BEGIN(0, 0); … … 305 305 * @opcode 0x10 306 306 * @oppfx 0xf2 307 * @opcodesub 11 mr/reg307 * @opcodesub !11 mr/reg 308 308 * @opcpuid avx 309 309 * @opgroup og_avx_simdfp_datamove … … 313 313 * @optest op1=0 op2=-22 -> op1=-22 314 314 */ 315 IEMOP_MNEMONIC2(VEX_ XM, VMOVSD, vmovsd, VsdZx_WO, Mq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_IGNORES_VEX_L);315 IEMOP_MNEMONIC2(VEX_RM_MEM, VMOVSD, vmovsd, VsdZx_WO, Mq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED); 316 316 IEM_MC_BEGIN(0, 2); 317 317 IEM_MC_LOCAL(uint64_t, uSrc); … … 504 504 * @optest op1=3 op2=0x42 op3=0x77 -> op1=0x4200000077 505 505 */ 506 IEMOP_MNEMONIC3(VEX_MVR , VMOVSS, vmovss, Uss_WO, HssHi, Vss, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_IGNORES_VEX_L);506 IEMOP_MNEMONIC3(VEX_MVR_REG, VMOVSS, vmovss, Uss_WO, HssHi, Vss, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED); 507 507 IEMOP_HLP_DONE_VEX_DECODING(); 508 508 IEM_MC_BEGIN(0, 0); … … 522 522 * @opcode 0x11 523 523 * @oppfx 0xf3 524 * @opcodesub 11 mr/reg524 * @opcodesub !11 mr/reg 525 525 * @opcpuid avx 526 526 * @opgroup og_avx_simdfp_datamove … … 530 530 * @optest op1=0 op2=-22 -> op1=-22 531 531 */ 532 IEMOP_MNEMONIC2(VEX_MR , VMOVSS, vmovss, Md_WO, Vss, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_IGNORES_VEX_L);532 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVSS, vmovss, Md_WO, Vss, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED); 533 533 IEM_MC_BEGIN(0, 2); 534 534 IEM_MC_LOCAL(uint32_t, uSrc); … … 570 570 * @optest op2=0x42 op3=0x77 -> op1=0x420000000000000077 571 571 */ 572 IEMOP_MNEMONIC3(VEX_MVR , VMOVSD, vmovsd, Usd_WO, HsdHi, Vsd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_IGNORES_VEX_L);572 IEMOP_MNEMONIC3(VEX_MVR_REG, VMOVSD, vmovsd, Usd_WO, HsdHi, Vsd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED); 573 573 IEMOP_HLP_DONE_VEX_DECODING(); 574 574 IEM_MC_BEGIN(0, 0); … … 588 588 * @opcode 0x11 589 589 * @oppfx 0xf2 590 * @opcodesub 11 mr/reg590 * @opcodesub !11 mr/reg 591 591 * @opcpuid avx 592 592 * @opgroup og_avx_simdfp_datamove … … 596 596 * @optest op1=0 op2=-22 -> op1=-22 597 597 */ 598 IEMOP_MNEMONIC2(VEX_MR , VMOVSD, vmovsd, Mq_WO, Vsd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_IGNORES_VEX_L);598 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVSD, vmovsd, Mq_WO, Vsd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED); 599 599 IEM_MC_BEGIN(0, 2); 600 600 IEM_MC_LOCAL(uint64_t, uSrc); … … 635 635 * @note op3 and op2 are only the 8-byte high XMM register halfs. 636 636 */ 637 IEMOP_MNEMONIC3(VEX_RVM , VMOVHLPS, vmovhlps, Vq_WO, HqHi, UqHi, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);637 IEMOP_MNEMONIC3(VEX_RVM_REG, VMOVHLPS, vmovhlps, Vq_WO, HqHi, UqHi, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO); 638 638 639 639 IEMOP_HLP_DONE_VEX_DECODING_L0(); … … 2057 2057 * @optest 64-bit / op1=0 op2=-42 -> op1=-42 2058 2058 */ 2059 IEMOP_MNEMONIC2(VEX_RM, VMOVQ, vmovq, Vq_WO, Eq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OZ_PFX );2059 IEMOP_MNEMONIC2(VEX_RM, VMOVQ, vmovq, Vq_WO, Eq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OZ_PFX | IEMOPHINT_VEX_L_ZERO); 2060 2060 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT)) 2061 2061 { … … 2107 2107 * @optest op1=0 op2=-42 -> op1=-42 2108 2108 */ 2109 IEMOP_MNEMONIC2(VEX_RM, VMOVD, vmovd, Vd_WO, Ed, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OZ_PFX );2109 IEMOP_MNEMONIC2(VEX_RM, VMOVD, vmovd, Vd_WO, Ed, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OZ_PFX | IEMOPHINT_VEX_L_ZERO); 2110 2110 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT)) 2111 2111 { … … 2750 2750 * @optest 64-bit / op1=0 op2=-42 -> op1=-42 2751 2751 */ 2752 IEMOP_MNEMONIC2(VEX_MR, VMOVQ, vmovq, Eq_WO, Vq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OZ_PFX );2752 IEMOP_MNEMONIC2(VEX_MR, VMOVQ, vmovq, Eq_WO, Vq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OZ_PFX | IEMOPHINT_VEX_L_ZERO); 2753 2753 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT)) 2754 2754 { … … 2800 2800 * @optest op1=0 op2=-42 -> op1=-42 2801 2801 */ 2802 IEMOP_MNEMONIC2(VEX_MR, VMOVD, vmovd, Ed_WO, Vd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OZ_PFX );2802 IEMOP_MNEMONIC2(VEX_MR, VMOVD, vmovd, Ed_WO, Vd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OZ_PFX | IEMOPHINT_VEX_L_ZERO); 2803 2803 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT)) 2804 2804 { … … 2850 2850 FNIEMOP_DEF(iemOp_vmovq_Vq_Wq) 2851 2851 { 2852 IEMOP_MNEMONIC2(VEX_RM, VMOVQ, vmovq, Vq_WO, Wq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES );2852 IEMOP_MNEMONIC2(VEX_RM, VMOVQ, vmovq, Vq_WO, Wq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO); 2853 2853 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 2854 2854 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT)) … … 3181 3181 FNIEMOP_DEF_1(iemOp_VGrp15_vstmxcsr, uint8_t, bRm) 3182 3182 { 3183 IEMOP_MNEMONIC1(VEX_M_MEM, VSTMXCSR, vstmxcsr, Md_WO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES );3183 IEMOP_MNEMONIC1(VEX_M_MEM, VSTMXCSR, vstmxcsr, Md_WO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO); 3184 3184 IEM_MC_BEGIN(2, 0); 3185 3185 IEM_MC_ARG(uint8_t, iEffSeg, 0); … … 3367 3367 FNIEMOP_DEF(iemOp_vmovq_Wq_Vq) 3368 3368 { 3369 IEMOP_MNEMONIC2(VEX_MR, VMOVQ, vmovq, Wq_WO, Vq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES );3369 IEMOP_MNEMONIC2(VEX_MR, VMOVQ, vmovq, Wq_WO, Vq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO); 3370 3370 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 3371 3371 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT)) … … 3555 3555 FNIEMOP_DEF(iemOp_vmovntdq_Mx_Vx) 3556 3556 { 3557 IEMOP_MNEMONIC2(VEX_MR , VMOVNTDQ, vmovntdq, Mx_WO, Vx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);3557 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVNTDQ, vmovntdq, Mx_WO, Vx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES); 3558 3558 Assert(pVCpu->iem.s.uVexLength <= 1); 3559 3559 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); -
trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap2.cpp.h
r67042 r67072 135 135 FNIEMOP_STUB(iemOp_vpcmpeqq_Vx_Hx_Wx); 136 136 137 /** Opcode VEX.66.0F38 0x2a. */ 138 /* 139 * @ opcode 0x2a 140 * @ opcodesub !11 mr/reg vex.l=0 141 * @ oppfx 0x66 142 * @ opcpuid avx 143 * @ opgroup og_avx_cachect 144 * @ opxcpttype 1 145 * @ optest op1=-1 op2=2 -> op1=2 146 * @ optest op1=0 op2=-42 -> op1=-42 147 */ 137 148 138 FNIEMOP_DEF(iemOp_vmovntdqa_Vx_Mx) 149 139 { 150 140 Assert(pVCpu->iem.s.uVexLength <= 1); 151 IEMOP_MNEMONIC2(VEX_RM, VMOVNTDQA, vmovntdqa, Vx_WO, Mx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);152 141 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 153 142 if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT)) … … 155 144 if (pVCpu->iem.s.uVexLength == 0) 156 145 { 157 /* 158 * 128-bit: Memory, register. 146 /** 147 * @opcode 0x2a 148 * @opcodesub !11 mr/reg vex.l=0 149 * @oppfx 0x66 150 * @opcpuid avx 151 * @opgroup og_avx_cachect 152 * @opxcpttype 1 153 * @optest op1=-1 op2=2 -> op1=2 154 * @optest op1=0 op2=-42 -> op1=-42 159 155 */ 156 /* 128-bit: Memory, register. */ 157 IEMOP_MNEMONIC2EX(vmovntdqa_Vdq_WO_Mdq_L0, "vmovntdqa, Vdq_WO, Mdq", VEX_RM_MEM, VMOVNTDQA, vmovntdqa, Vx_WO, Mx, 158 DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES); 160 159 IEM_MC_BEGIN(0, 2); 161 160 IEM_MC_LOCAL(RTUINT128U, uSrc); … … 175 174 else 176 175 { 177 /* 178 * @ opdone 179 * @ opcode 0x2a 180 * @ opcodesub !11 mr/reg vex.l=1 181 * @ oppfx 0x66 182 * @ opcpuid avx2 183 * @ opgroup og_avx2_cachect 184 * @ opxcpttype 1 185 * @ optest op1=-1 op2=2 -> op1=2 186 * @ optest op1=0 op2=-42 -> op1=-42 187 */ 188 /* 189 * 256-bit: Memory, register. 176 /** 177 * @opdone 178 * @opcode 0x2a 179 * @opcodesub !11 mr/reg vex.l=1 180 * @oppfx 0x66 181 * @opcpuid avx2 182 * @opgroup og_avx2_cachect 183 * @opxcpttype 1 184 * @optest op1=-1 op2=2 -> op1=2 185 * @optest op1=0 op2=-42 -> op1=-42 190 186 */ 187 /* 256-bit: Memory, register. */ 188 IEMOP_MNEMONIC2EX(vmovntdqa_Vqq_WO_Mqq_L1, "vmovntdqa, Vqq_WO,Mqq", VEX_RM_MEM, VMOVNTDQA, vmovntdqa, Vx_WO, Mx, 189 DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES); 191 190 IEM_MC_BEGIN(0, 2); 192 191 IEM_MC_LOCAL(RTUINT256U, uSrc); … … 196 195 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV(); 197 196 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT(); 198 IEM_MC_ACTUALIZE_AVX_STATE_FOR_ READ();199 200 IEM_MC_FETCH_ YREG_U256(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);201 IEM_MC_STORE_ MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);197 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE(); 198 199 IEM_MC_FETCH_MEM_U256_ALIGN_AVX(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 200 IEM_MC_STORE_YREG_U256_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc); 202 201 203 202 IEM_MC_ADVANCE_RIP(); … … 206 205 return VINF_SUCCESS; 207 206 } 207 208 208 /** 209 209 * @opdone 210 * @opmnemonic udvex660f382ar eg210 * @opmnemonic udvex660f382arg 211 211 * @opcode 0x2a 212 212 * @opcodesub 11 mr/reg … … 215 215 * @opcpuid avx 216 216 * @optest -> 217 * @oponly218 217 */ 219 218 return IEMOP_RAISE_INVALID_OPCODE(); 220 219 221 220 } 221 222 222 223 223 /** Opcode VEX.66.0F38 0x2b. */ -
trunk/src/VBox/VMM/include/IEMInternal.h
r67003 r67072 914 914 /** VEX+ModR/M: reg, r/m (memory) */ 915 915 #define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM | IEMOPFORM_NOT_MOD3) 916 #define IEMOPFORM_VEX_XM IEMOPFORM_VEX_RM_MEM917 916 /** VEX+ModR/M: r/m, reg */ 918 917 #define IEMOPFORM_VEX_MR 5 … … 956 955 /** Ignores the operand size prefix (66h). */ 957 956 #define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10) 958 /** Ignores REX.W . */957 /** Ignores REX.W (aka WIG). */ 959 958 #define IEMOPHINT_IGNORES_REXW RT_BIT_32(11) 960 959 /** Both the operand size prefixes (66h + REX.W) are ignored. */ … … 963 962 #define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11) 964 963 /** The VEX.L value is ignored (aka LIG). */ 965 #define IEMOPHINT_ IGNORES_VEX_LRT_BIT_32(12)966 /** The VEX.L value must be zero (i.e. 128-bit width ). */964 #define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12) 965 /** The VEX.L value must be zero (i.e. 128-bit width only). */ 967 966 #define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13) 968 967 -
trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp
r67042 r67072 119 119 #define IEMOP_HLP_DEFAULT_64BIT_OP_SIZE() do { } while (0) 120 120 #define IEMOP_HLP_CLEAR_REX_NOT_BEFORE_OPCODE(a_szPrf) do { } while (0) 121 #define IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV() do { } while (0)122 121 #define IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX() do { } while (0) 123 #define IEMOP_HLP_DONE_VEX_DECODING() do { } while (0) 124 #define IEMOP_HLP_DONE_VEX_DECODING_L0() do { } while (0) 125 #define IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV() do { } while (0) 122 #define IEMOP_HLP_DONE_VEX_DECODING() do { } while (0) 123 #define IEMOP_HLP_DONE_VEX_DECODING_L0() do { } while (0) 124 #define IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV() do { } while (0) 125 #define IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV() do { } while (0) 126 126 #define IEMOP_HLP_DONE_DECODING_NO_LOCK_REPZ_OR_REPNZ_PREFIXES() do { } while (0) 127 127 -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-data.py
r67040 r67072 305 305 for oOp in oInstr.aoOperands: 306 306 self.sEncoding += '_' + oOp.sType; 307 if oInstr.sSubOpcode == 'rex.w=1': self.sEncoding += '_WNZ';308 elif oInstr.sSubOpcode == 'rex.w=0': self.sEncoding += '_WZ';307 if oInstr.sSubOpcode and iai.g_kdSubOpcodes[oInstr.sSubOpcode][1]: 308 self.sEncoding += '_' + iai.g_kdSubOpcodes[oInstr.sSubOpcode][1]; 309 309 310 310 if oInstr.fUnused: … … 334 334 if 'vex_l_zero' in oInstr.dHints: 335 335 self.asFlags.append('BS3CG1INSTR_F_VEX_L_ZERO'); 336 if 'vex_l_ignored' in oInstr.dHints: 337 self.asFlags.append('BS3CG1INSTR_F_VEX_L_IGNORED'); 336 338 337 339 self.fAdvanceMnemonic = True; ##< Set by the caller. … … 367 369 return ', '.join(['(uint8_t)BS3CG1OP_%s' % (oOp.sType,) for oOp in self.oInstr.aoOperands]); 368 370 371 def getOpcodeMap(self): 372 """ Returns the opcode map number for the BS3CG1INSTR structure. """ 373 sEncoding = self.oInstr.aoMaps[0].sEncoding; 374 if sEncoding == 'legacy': return 0; 375 if sEncoding == 'vex1': return 1; 376 if sEncoding == 'vex2': return 2; 377 if sEncoding == 'vex3': return 3; 378 if sEncoding == 'xop8': return 8; 379 if sEncoding == 'xop9': return 9; 380 if sEncoding == 'xop10': return 10; 381 assert False, sEncoding; 382 return 3; 383 369 384 def getInstructionEntry(self): 370 385 """ Returns an array of BS3CG1INSTR member initializers. """ 386 assert len(self.oInstr.sMnemonic) < 16; 371 387 sOperands = ', '.join([oOp.sType for oOp in self.oInstr.aoOperands]); 372 388 if sOperands: … … 379 395 ' /* offTests = */ %s,' % (self.oTests.offTests,), 380 396 ' /* enmEncoding = */ (unsigned)%s,' % (self.sEncoding,), 397 ' /* uOpcodeMap = */ (unsigned)%s,' % (self.getOpcodeMap(),), 381 398 ' /* enmPrefixKind = */ (unsigned)%s,' % (self.sPfxKind,), 382 399 ' /* enmCpuTest = */ (unsigned)%s,' % (self.sCpu,), -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c
r67040 r67072 147 147 /** The encoding. */ 148 148 BS3CG1ENC enmEncoding; 149 /** The non-invalid encoding. This differsfrom enmEncoding when149 /** The non-invalid encoding. This may differ from enmEncoding when 150 150 * Bs3Cg1CalcNoneIntelInvalidEncoding has been called. */ 151 151 BS3CG1ENC enmEncodingNonInvalid; … … 167 167 /** Whether to advance the mnemonic pointer or not. */ 168 168 uint8_t fAdvanceMnemonic; 169 /** The opcode map number. */ 170 uint8_t uOpcodeMap; 169 171 /** The number of opcode bytes. */ 170 172 uint8_t cbOpcodes; … … 275 277 /** Set by the encoding method to indicating invalid encoding. */ 276 278 bool fInvalidEncoding; 279 /** The result of Bs3Cg1CpuSetupFirst(). */ 280 bool fCpuSetupFirstResult; 277 281 278 282 /** The context we're working on. */ … … 885 889 AssertCompile(RT_ELEMENTS(g_aoffBs3Cg1DstFields) == BS3CG1DST_END); 886 890 887 #ifdef BS3CG1_DEBUG_CTX_MOD888 891 /** Destination field names. */ 889 892 static const struct { char sz[12]; } g_aszBs3Cg1DstFields[] = … … 1157 1160 AssertCompile(RT_ELEMENTS(g_aszBs3Cg1DstFields) == BS3CG1DST_END); 1158 1161 1159 #endif1160 1162 1161 1163 #if 0 … … 2596 2598 2597 2599 /** 2600 * Inserts a 3-byte VEX prefix. 2601 * 2602 * @returns New offDst value. 2603 * @param pThis The state. 2604 * @param offDst The current instruction offset. 2605 * @param uVexL The VEX.L value. 2606 * @param uVexV The VEX.V value (caller inverted it already). 2607 * @param uVexR The VEX.R value (caller inverted it already). 2608 * @param uVexX The VEX.X value (caller inverted it already). 2609 * @param uVexB The VEX.B value (caller inverted it already). 2610 * @param uVexW The VEX.W value (straight). 2611 */ 2612 DECLINLINE(unsigned) BS3_NEAR_CODE Bs3Cg1InsertVex3bPrefix(PBS3CG1STATE pThis, unsigned offDst, uint8_t uVexV, uint8_t uVexL, 2613 uint8_t uVexR, uint8_t uVexX, uint8_t uVexB, uint8_t uVexW) 2614 { 2615 uint8_t b1; 2616 uint8_t b2; 2617 b1 = uVexR << 7; 2618 b1 |= uVexX << 6; 2619 b1 |= uVexB << 5; 2620 b1 |= pThis->uOpcodeMap; 2621 b2 = uVexV << 3; 2622 b2 |= uVexW << 7; 2623 b2 |= uVexL << 2; 2624 switch (pThis->enmPrefixKind) 2625 { 2626 case BS3CG1PFXKIND_NO_F2_F3_66: b2 |= 0; break; 2627 case BS3CG1PFXKIND_REQ_66: b2 |= 1; break; 2628 case BS3CG1PFXKIND_REQ_F3: b2 |= 2; break; 2629 case BS3CG1PFXKIND_REQ_F2: b2 |= 3; break; 2630 default: 2631 Bs3TestFailedF("enmPrefixKind=%d not supported for VEX!\n", pThis->enmPrefixKind); 2632 break; 2633 } 2634 2635 pThis->abCurInstr[offDst] = 0xc4; /* vex3 */ 2636 pThis->abCurInstr[offDst + 1] = b1; 2637 pThis->abCurInstr[offDst + 2] = b2; 2638 pThis->uVexL = uVexL; 2639 return offDst + 3; 2640 } 2641 2642 2643 /** 2598 2644 * Inserts a 2-byte VEX prefix. 2645 * 2646 * @note Will switch to 3-byte VEX prefix if uOpcodeMap isn't one. 2599 2647 * 2600 2648 * @returns New offDst value. … … 2608 2656 uint8_t uVexV, uint8_t uVexL, uint8_t uVexR) 2609 2657 { 2610 uint8_t b = uVexR << 7; 2611 b |= uVexV << 3; 2612 b |= uVexL << 2; 2613 switch (pThis->enmPrefixKind) 2614 { 2615 case BS3CG1PFXKIND_NO_F2_F3_66: b |= 0; break; 2616 case BS3CG1PFXKIND_REQ_66: b |= 1; break; 2617 case BS3CG1PFXKIND_REQ_F3: b |= 2; break; 2618 case BS3CG1PFXKIND_REQ_F2: b |= 3; break; 2619 default: 2620 Bs3TestFailedF("enmPrefixKind=%d not supported for VEX!\n"); 2621 break; 2622 } 2623 2624 pThis->abCurInstr[offDst] = 0xc5; /* vex2 */ 2625 pThis->abCurInstr[offDst + 1] = b; 2626 pThis->uVexL = uVexL; 2627 return offDst + 2; 2628 } 2629 2630 2631 /** 2632 * Inserts a 3-byte VEX prefix. 2633 * 2634 * @returns New offDst value. 2635 * @param pThis The state. 2636 * @param offDst The current instruction offset. 2637 * @param uVexL The VEX.L value. 2638 * @param uVexV The VEX.V value (caller inverted it already). 2639 * @param uVexR The VEX.R value (caller inverted it already). 2640 * @param uVexR The VEX.X value (caller inverted it already). 2641 * @param uVexR The VEX.B value (caller inverted it already). 2642 * @param uVexR The VEX.W value (straight). 2643 */ 2644 DECLINLINE(unsigned) BS3_NEAR_CODE Bs3Cg1InsertVex3bPrefix(PBS3CG1STATE pThis, unsigned offDst, uint8_t uVexV, uint8_t uVexL, 2645 uint8_t uVexR, uint8_t uVexX, uint8_t uVexB, uint8_t uVexW) 2646 { 2647 uint8_t b1; 2648 uint8_t b2; 2649 b1 = uVexR << 7; 2650 b1 |= uVexX << 6; 2651 b1 |= uVexB << 5; 2652 b1 |= 1; /* VEX.mmmmm = 1*/ /** @todo three byte opcode tables */ 2653 b2 = uVexV << 3; 2654 b2 |= uVexW << 7; 2655 b2 |= uVexL << 2; 2656 switch (pThis->enmPrefixKind) 2657 { 2658 case BS3CG1PFXKIND_NO_F2_F3_66: b2 |= 0; break; 2659 case BS3CG1PFXKIND_REQ_66: b2 |= 1; break; 2660 case BS3CG1PFXKIND_REQ_F3: b2 |= 2; break; 2661 case BS3CG1PFXKIND_REQ_F2: b2 |= 3; break; 2662 default: 2663 Bs3TestFailedF("enmPrefixKind=%d not supported for VEX!\n", pThis->enmPrefixKind); 2664 break; 2665 } 2666 2667 pThis->abCurInstr[offDst] = 0xc4; /* vex3 */ 2668 pThis->abCurInstr[offDst + 1] = b1; 2669 pThis->abCurInstr[offDst + 2] = b2; 2670 pThis->uVexL = uVexL; 2671 return offDst + 3; 2658 if (pThis->uOpcodeMap == 1) 2659 { 2660 uint8_t b = uVexR << 7; 2661 b |= uVexV << 3; 2662 b |= uVexL << 2; 2663 switch (pThis->enmPrefixKind) 2664 { 2665 case BS3CG1PFXKIND_NO_F2_F3_66: b |= 0; break; 2666 case BS3CG1PFXKIND_REQ_66: b |= 1; break; 2667 case BS3CG1PFXKIND_REQ_F3: b |= 2; break; 2668 case BS3CG1PFXKIND_REQ_F2: b |= 3; break; 2669 default: 2670 Bs3TestFailedF("enmPrefixKind=%d not supported for VEX!\n"); 2671 break; 2672 } 2673 2674 pThis->abCurInstr[offDst] = 0xc5; /* vex2 */ 2675 pThis->abCurInstr[offDst + 1] = b; 2676 pThis->uVexL = uVexL; 2677 return offDst + 2; 2678 } 2679 return Bs3Cg1InsertVex3bPrefix(pThis, offDst, uVexV, uVexL, uVexR, 1 /*uVexX*/, 1 /*uVexB*/, 0/*uVexW*/); 2672 2680 } 2673 2681 … … 3432 3440 */ 3433 3441 static unsigned BS3_NEAR_CODE 3434 Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_L 0_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding)3442 Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lmbz_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding) 3435 3443 { 3436 3444 unsigned off; … … 3520 3528 return iEncoding + 1; 3521 3529 } 3530 3531 3532 /** 3533 * Wip - VEX.W ignored. 3534 */ 3535 static unsigned BS3_NEAR_CODE 3536 Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lxx_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding, uint8_t uVexL) 3537 { 3538 unsigned off; 3539 switch (iEncoding) 3540 { 3541 case 0: 3542 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, uVexL, 1 /*~R*/); 3543 off = Bs3Cg1InsertOpcodes(pThis, off); 3544 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 0, 0); 3545 iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0; 3546 break; 3547 #if ARCH_BITS == 64 3548 case 1: 3549 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, uVexL, 0 /*~R*/); 3550 off = Bs3Cg1InsertOpcodes(pThis, off); 3551 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 7 + 8, 0); 3552 break; 3553 #endif 3554 case 2: 3555 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xe /*~V*/, uVexL, 1 /*~R*/); 3556 off = Bs3Cg1InsertOpcodes(pThis, off); 3557 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 0, 0); 3558 pThis->fInvalidEncoding = true; 3559 break; 3560 case 3: 3561 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, uVexL, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/); 3562 off = Bs3Cg1InsertOpcodes(pThis, off); 3563 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 1, 0); 3564 break; 3565 case 4: 3566 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, uVexL, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W-ignored*/); 3567 off = Bs3Cg1InsertOpcodes(pThis, off); 3568 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 5, 0); 3569 iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 3 : 0; 3570 break; 3571 #if ARCH_BITS == 64 3572 case 5: 3573 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, uVexL, 0 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/); 3574 off = Bs3Cg1InsertOpcodes(pThis, off); 3575 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 5+8, 0); 3576 break; 3577 case 6: 3578 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, uVexL, 1 /*~R*/, 1 /*~X*/, 0 /*~B-ignored*/, 0 /*W*/); 3579 off = Bs3Cg1InsertOpcodes(pThis, off); 3580 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 1, 0); 3581 break; 3582 case 7: 3583 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, uVexL, 1 /*~R*/, 0 /*~X-ignored*/, 1 /*~B*/, 0 /*W*/); 3584 off = Bs3Cg1InsertOpcodes(pThis, off); 3585 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 2, 0); 3586 break; 3587 #endif 3588 case 8: 3589 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0 /*~V*/, uVexL, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/); 3590 off = Bs3Cg1InsertOpcodes(pThis, off); 3591 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 5, 0); 3592 pThis->fInvalidEncoding = true; 3593 break; 3594 case 9: 3595 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 7 /*~V*/, uVexL, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/); 3596 off = Bs3Cg1InsertOpcodes(pThis, off); 3597 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 2, 0); 3598 pThis->fInvalidEncoding = true; 3599 break; 3600 default: 3601 return 0; 3602 } 3603 pThis->cbCurInstr = off; 3604 return iEncoding + 1; 3605 } 3606 3607 3608 /** 3609 * Wip - VEX.W ignored. 3610 * L0 - VEX.L is zero (encoding may exist where it isn't). 3611 */ 3612 static unsigned BS3_NEAR_CODE 3613 Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_L0_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding) 3614 { 3615 return Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lxx_OR_ViceVersa(pThis, iEncoding, 0 /*uVexL*/); 3616 } 3617 3618 3619 /** 3620 * Wip - VEX.W ignored. 3621 * L1 - VEX.L is one (encoding may exist where it isn't). 3622 */ 3623 static unsigned BS3_NEAR_CODE 3624 Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_L1_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding) 3625 { 3626 return Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lxx_OR_ViceVersa(pThis, iEncoding, 1 /*uVexL*/); 3627 } 3628 3522 3629 3523 3630 … … 3716 3823 /** 3717 3824 * Wip = VEX.W ignored. 3718 * L 0= VEX.L must be zero.3825 * Lmbz = VEX.L must be zero. 3719 3826 */ 3720 3827 static unsigned BS3_NEAR_CODE 3721 Bs3Cg1EncodeNext_VEX_MODRM_WsomethingWO_Vsomething_Wip_L 0_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding)3828 Bs3Cg1EncodeNext_VEX_MODRM_WsomethingWO_Vsomething_Wip_Lmbz_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding) 3722 3829 { 3723 3830 unsigned off; … … 4729 4836 break; 4730 4837 4838 case BS3CG1ENC_VEX_MODRM_Vx_WO_Mx_L0: 4839 BS3_ASSERT(!(pThis->fFlags & BS3CG1INSTR_F_VEX_L_ZERO)); 4840 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_L0_OR_ViceVersa; 4841 pThis->iRegOp = 0; 4842 pThis->iRmOp = 1; 4843 pThis->aOperands[0].cbOp = 16; 4844 pThis->aOperands[1].cbOp = 16; 4845 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX_ZX_VLMAX; 4846 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_MEM; 4847 pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0; 4848 break; 4849 4850 case BS3CG1ENC_VEX_MODRM_Vx_WO_Mx_L1: 4851 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_L1_OR_ViceVersa; 4852 pThis->iRegOp = 0; 4853 pThis->iRmOp = 1; 4854 pThis->aOperands[0].cbOp = 32; 4855 pThis->aOperands[1].cbOp = 32; 4856 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX_ZX_VLMAX; 4857 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_MEM; 4858 pThis->aOperands[0].idxFieldBase = BS3CG1DST_YMM0; 4859 break; 4860 4731 4861 case BS3CG1ENC_VEX_MODRM_Vsd_WO_HsdHi_Usd: 4732 4862 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Hsomething_Usomething_Lip_Wip_OR_ViceVersa; … … 4775 4905 4776 4906 case BS3CG1ENC_VEX_MODRM_Vq_WO_Wq: 4777 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_WsomethingWO_Vsomething_Wip_L0_OR_ViceVersa; 4907 BS3_ASSERT(pThis->fFlags & BS3CG1INSTR_F_VEX_L_ZERO); 4908 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_WsomethingWO_Vsomething_Wip_Lmbz_OR_ViceVersa; 4778 4909 pThis->iRegOp = 0; 4779 4910 pThis->iRmOp = 1; … … 4850 4981 4851 4982 case BS3CG1ENC_VEX_MODRM_Mq_WO_Vq: 4983 BS3_ASSERT(pThis->fFlags & (BS3CG1INSTR_F_VEX_L_ZERO | BS3CG1INSTR_F_VEX_L_IGNORED)); 4852 4984 pThis->pfnEncoder = pThis->fFlags & BS3CG1INSTR_F_VEX_L_ZERO 4853 ? Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_L 0_OR_ViceVersa4985 ? Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lmbz_OR_ViceVersa 4854 4986 : Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lig_OR_ViceVersa; 4855 4987 pThis->iRmOp = 0; … … 4933 5065 4934 5066 case BS3CG1ENC_VEX_MODRM_Wq_WO_Vq: 4935 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_WsomethingWO_Vsomething_Wip_L0_OR_ViceVersa; 5067 BS3_ASSERT(pThis->fFlags & BS3CG1INSTR_F_VEX_L_ZERO); 5068 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_WsomethingWO_Vsomething_Wip_Lmbz_OR_ViceVersa; 4936 5069 pThis->iRegOp = 1; 4937 5070 pThis->iRmOp = 0; … … 5542 5675 && offField - sizeof(BS3REGCTX) < RT_UOFFSET_AFTER(BS3EXTCTX, Ctx.x87.aXMM[15])) 5543 5676 { 5544 if (!pThis->fWorkExtCtx) 5545 return Bs3TestFailedF("Extended context disabled: Field %d @ %#x LB %u\n", idxField, offField, cbDst); 5546 PtrField.pb = (uint8_t *)pThis->pExtCtx + offField - sizeof(BS3REGCTX); 5677 if (pThis->fWorkExtCtx) 5678 PtrField.pb = (uint8_t *)pThis->pExtCtx + offField - sizeof(BS3REGCTX); 5679 else if (!pThis->fCpuSetupFirstResult) 5680 { 5681 BS3CG1_DPRINTF(("dbg: Extended context disabled: skipping modification (<=8)\n")); 5682 goto l_advance_to_next; 5683 } 5684 else 5685 return Bs3TestFailedF("Extended context disabled: Field %d (%s) @ %#x LB %u\n", 5686 idxField, g_aszBs3Cg1DstFields[idxField].sz, offField, cbDst); 5547 5687 } 5548 5688 /** @todo other FPU fields and FPU state formats. */ 5549 5689 else 5550 return Bs3TestFailedF("Todo implement me: cbDst=%u idxField=%d offField=%#x (<= 8)", cbDst, idxField, offField); 5690 return Bs3TestFailedF("Todo implement me: cbDst=%u idxField=%d %s offField=%#x (<= 8)", 5691 cbDst, idxField, g_aszBs3Cg1DstFields[idxField].sz, offField); 5551 5692 5552 5693 #ifdef BS3CG1_DEBUG_CTX_MOD … … 5661 5802 * Deal with larger field (FPU, SSE, AVX, ...). 5662 5803 */ 5663 else 5804 else if (pThis->fWorkExtCtx) 5664 5805 { 5665 5806 union … … 5675 5816 unsigned const offField = g_aoffBs3Cg1DstFields[idxField]; 5676 5817 unsigned iReg; 5677 5678 if (!pThis->fWorkExtCtx)5679 return Bs3TestFailedF("Extended context disabled: Field %d @ %#x LB %u\n", idxField, offField, cbDst);5680 5818 5681 5819 /* Copy the value into the union, doing the zero padding / extending. */ … … 5829 5967 Bs3MemCpy(pbMemCopy, PtrField.pv, cbDst); 5830 5968 } 5969 /* !pThis->fWorkExtCtx: */ 5970 else if (pThis->fCpuSetupFirstResult) 5971 return Bs3TestFailedF("Extended context disabled: Field %d (%s) @ %#x LB %u\n", 5972 idxField, g_aszBs3Cg1DstFields[idxField].sz, g_aoffBs3Cg1DstFields[idxField], cbDst); 5973 else 5974 BS3CG1_DPRINTF(("dbg: Extended context disabled: skipping modification [> 8]\n")); 5831 5975 5832 5976 /* … … 6439 6583 Bs3TestSubF("%s / %.*s", pThis->pszModeShort, pThis->cchMnemonic, pThis->pchMnemonic); 6440 6584 pThis->fAdvanceMnemonic = pInstr->fAdvanceMnemonic; 6585 pThis->uOpcodeMap = pInstr->uOpcodeMap; 6441 6586 pThis->cOperands = pInstr->cOperands; 6442 6587 pThis->cbOpcodes = pInstr->cbOpcodes; … … 6459 6604 * Check if the CPU supports the instruction. 6460 6605 */ 6461 if ( !Bs3Cg1CpuSetupFirst(pThis) 6606 pThis->fCpuSetupFirstResult = Bs3Cg1CpuSetupFirst(pThis); 6607 if ( !pThis->fCpuSetupFirstResult 6462 6608 || (pThis->fFlags & (BS3CG1INSTR_F_UNUSED | BS3CG1INSTR_F_INVALID))) 6463 6609 fOuterInvalidInstr = true; … … 6566 6712 else 6567 6713 { 6568 Bs3TestPrintf("Bs3Cg1RunContextModifier(out): iEncoding=%u iTest=%u\n", iEncoding, pThis->iTest); 6714 Bs3TestPrintf("Bs3Cg1RunContextModifier(out): iEncoding=%u iTest=%RU32 iInstr=%u %.*s\n", 6715 iEncoding, pThis->iTest, pThis->iInstr, pThis->cchMnemonic, pThis->pchMnemonic); 6569 6716 ASMHalt(); 6570 6717 } … … 6604 6751 else 6605 6752 { 6606 Bs3TestPrintf("Bs3Cg1RunContextModifier(in): iEncoding=%u iTest=%u\n", iEncoding, pThis->iTest); 6753 Bs3TestPrintf("Bs3Cg1RunContextModifier(in): iEncoding=%u iTest=%u iInstr=%RU32 %.*s\n", 6754 iEncoding, pThis->iTest, pThis->iInstr, pThis->cchMnemonic, pThis->pchMnemonic); 6607 6755 ASMHalt(); 6608 6756 } -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h
r67040 r67072 123 123 BS3CG1OP_Mps_WO, 124 124 BS3CG1OP_Mpd_WO, 125 BS3CG1OP_Mx, 125 126 BS3CG1OP_Mx_WO, 126 127 … … 195 196 BS3CG1ENC_VEX_MODRM_VssZx_WO_Md, 196 197 BS3CG1ENC_VEX_MODRM_VsdZx_WO_Mq, 198 BS3CG1ENC_VEX_MODRM_Vx_WO_Mx_L0, 199 BS3CG1ENC_VEX_MODRM_Vx_WO_Mx_L1, 197 200 BS3CG1ENC_VEX_MODRM_Vx_WO_Wx, 198 201 BS3CG1ENC_VEX_MODRM_Ed_WO_Vd_WZ, … … 335 338 /** BS3CG1ENC values. */ 336 339 uint32_t enmEncoding : 10; 340 /** The VEX, EVEX or XOP opcode map number (VEX.mmmm). */ 341 uint32_t uOpcodeMap : 4; 337 342 /** BS3CG1PFXKIND values. */ 338 343 uint32_t enmPrefixKind : 4; … … 342 347 uint32_t enmXcptType : 5; 343 348 /** Currently unused bits. */ 344 uint32_t uUnused : 6;349 uint32_t uUnused : 3; 345 350 /** BS3CG1INSTR_F_XXX. */ 346 351 uint32_t fFlags; … … 366 371 /** VEX.L must be zero (IEMOPHINT_VEX_L_ZERO). */ 367 372 #define BS3CG1INSTR_F_VEX_L_ZERO UINT32_C(0x00000020) 373 /** VEX.L is ignored (IEMOPHINT_VEX_L_IGNORED). */ 374 #define BS3CG1INSTR_F_VEX_L_IGNORED UINT32_C(0x00000040) 368 375 /** @} */ 369 376
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