Changeset 67076 in vbox for trunk/src/VBox/ValidationKit
- Timestamp:
- May 25, 2017 8:58:57 AM (8 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c
r67074 r67076 1420 1420 1421 1421 1422 /** The modrm.reg value is taken from the instruction byte at @a off. */ 1423 static unsigned BS3_NEAR_CODE 1424 Bs3Cfg1EncodeMemMod0DispWithDefaultsAndNoReg(PBS3CG1STATE pThis, unsigned off) 1425 { 1426 return Bs3Cfg1EncodeMemMod0Disp(pThis, false /*fAddrOverride*/, off, 1427 (pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT, 1428 pThis->aOperands[pThis->iRmOp].cbOp, 1429 0 /*cbMisalign*/, 1430 pThis->aOperands[pThis->iRmOp].enmLocation); 1431 } 1432 1433 1422 1434 1423 1435 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Eb_Gb(PBS3CG1STATE pThis, unsigned iEncoding) … … 3482 3494 { 3483 3495 unsigned off; 3484 if (iEncoding == 0) 3485 { 3486 /** @todo three by opcode needs some tweaking. */ 3487 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/); 3488 off = Bs3Cg1InsertOpcodes(pThis, off) - 1; 3489 off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3490 (pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT, 3491 4, 0, BS3CG1OPLOC_MEM_WO); 3492 } 3493 else if (iEncoding == 1) 3494 { 3495 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/); 3496 off = Bs3Cg1InsertOpcodes(pThis, off) - 1; 3497 off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3498 (pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT, 3499 4, 0, BS3CG1OPLOC_MEM_WO); 3500 } 3501 else if (iEncoding == 2) 3502 { 3503 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0x7 /*~V-invalid*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/); 3504 off = Bs3Cg1InsertOpcodes(pThis, off) - 1; 3505 off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3506 (pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT, 3507 4, 0, BS3CG1OPLOC_MEM_WO); 3508 pThis->fInvalidEncoding = true; 3509 } 3510 else if (iEncoding == 3) 3511 { 3512 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/); 3513 off = Bs3Cg1InsertOpcodes(pThis, off) - 1; 3514 off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3515 (pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT, 3516 4, 0, BS3CG1OPLOC_MEM_WO); 3517 pThis->fInvalidEncoding = true; 3518 } 3519 else if (iEncoding == 4) 3520 { 3521 pThis->abCurInstr[0] = P_OZ; 3522 off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/); 3523 off = Bs3Cg1InsertOpcodes(pThis, off) - 1; 3524 off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3525 (pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT, 3526 4, 0, BS3CG1OPLOC_MEM_WO); 3527 pThis->fInvalidEncoding = true; 3528 } 3529 else if (iEncoding == 5) 3530 { 3531 pThis->abCurInstr[0] = P_RZ; 3532 off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/); 3533 off = Bs3Cg1InsertOpcodes(pThis, off) - 1; 3534 off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3535 (pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT, 3536 4, 0, BS3CG1OPLOC_MEM_WO); 3537 pThis->fInvalidEncoding = true; 3538 } 3539 else if (iEncoding == 6) 3540 { 3541 pThis->abCurInstr[0] = P_RN; 3542 off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/); 3543 off = Bs3Cg1InsertOpcodes(pThis, off) - 1; 3544 off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3545 (pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT, 3546 4, 0, BS3CG1OPLOC_MEM_WO); 3547 pThis->fInvalidEncoding = true; 3548 } 3549 else if (iEncoding == 7) 3550 { 3551 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W*/); 3552 off = Bs3Cg1InsertOpcodes(pThis, off) - 1; 3553 off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3554 (pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT, 3555 4, 0, BS3CG1OPLOC_MEM_WO); 3556 } 3496 switch (iEncoding) 3497 { 3498 case 0: 3499 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/); 3500 off = Bs3Cg1InsertOpcodes(pThis, off) - 1; 3501 off = Bs3Cfg1EncodeMemMod0DispWithDefaultsAndNoReg(pThis, off); 3502 break; 3503 case 1: 3504 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/); 3505 off = Bs3Cg1InsertOpcodes(pThis, off) - 1; 3506 off = Bs3Cfg1EncodeMemMod0DispWithDefaultsAndNoReg(pThis, off); 3507 break; 3508 case 2: 3509 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0x7 /*~V-invalid*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/); 3510 off = Bs3Cg1InsertOpcodes(pThis, off) - 1; 3511 off = Bs3Cfg1EncodeMemMod0DispWithDefaultsAndNoReg(pThis, off); 3512 pThis->fInvalidEncoding = true; 3513 break; 3514 case 3: 3515 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/); 3516 off = Bs3Cg1InsertOpcodes(pThis, off) - 1; 3517 off = Bs3Cfg1EncodeMemMod0DispWithDefaultsAndNoReg(pThis, off); 3518 pThis->fInvalidEncoding = true; 3519 break; 3520 case 4: 3521 pThis->abCurInstr[0] = P_OZ; 3522 off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/); 3523 off = Bs3Cg1InsertOpcodes(pThis, off) - 1; 3524 off = Bs3Cfg1EncodeMemMod0DispWithDefaultsAndNoReg(pThis, off); 3525 pThis->fInvalidEncoding = true; 3526 break; 3527 case 5: 3528 pThis->abCurInstr[0] = P_RZ; 3529 off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/); 3530 off = Bs3Cg1InsertOpcodes(pThis, off) - 1; 3531 off = Bs3Cfg1EncodeMemMod0DispWithDefaultsAndNoReg(pThis, off); 3532 pThis->fInvalidEncoding = true; 3533 break; 3534 case 6: 3535 pThis->abCurInstr[0] = P_RN; 3536 off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/); 3537 off = Bs3Cg1InsertOpcodes(pThis, off) - 1; 3538 off = Bs3Cfg1EncodeMemMod0DispWithDefaultsAndNoReg(pThis, off); 3539 pThis->fInvalidEncoding = true; 3540 break; 3541 case 7: 3542 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W*/); 3543 off = Bs3Cg1InsertOpcodes(pThis, off) - 1; 3544 off = Bs3Cfg1EncodeMemMod0DispWithDefaultsAndNoReg(pThis, off); 3545 iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0; 3546 break; 3557 3547 #if ARCH_BITS == 64 3558 else if (BS3CG1_IS_64BIT_TARGET(pThis)) 3559 { 3560 if (iEncoding == 8) 3561 { 3548 case 8: 3562 3549 pThis->abCurInstr[0] = REX_____; 3563 3550 off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/); 3564 3551 off = Bs3Cg1InsertOpcodes(pThis, off) - 1; 3565 off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3566 (pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT, 3567 4, 0, BS3CG1OPLOC_MEM_WO); 3552 off = Bs3Cfg1EncodeMemMod0DispWithDefaultsAndNoReg(pThis, off); 3568 3553 pThis->fInvalidEncoding = true; 3569 } 3570 else 3554 break; 3555 #endif 3556 default: 3571 3557 return 0; 3572 3558 } 3573 #endif 3574 else 3575 return 0; 3559 3576 3560 pThis->cbCurInstr = off; 3577 3561 return iEncoding + 1; … … 4668 4652 pThis->iRmOp = 0; 4669 4653 pThis->aOperands[0].cbOp = 4; 4670 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_MEM_WO; 4654 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_MEM_WO; 4655 pThis->aOperands[0].enmLocationMem = BS3CG1OPLOC_MEM_WO; 4671 4656 break; 4672 4657
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