VirtualBox

Changeset 67077 in vbox


Ignore:
Timestamp:
May 25, 2017 9:23:27 AM (8 years ago)
Author:
vboxsync
Message:

bs3-cpu-generated-1: cleanups

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c

    r67076 r67077  
    14091409#endif
    14101410
    1411 /** Also encodes idxField of the register operand using idxFieldBase.   */
     1411/** Also encodes idxField of the register operand using idxFieldBase. */
    14121412static unsigned BS3_NEAR_CODE
    1413 Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(PBS3CG1STATE pThis, bool fAddrOverride, unsigned off,
    1414                                                 uint8_t iReg, uint8_t cbMisalign)
     1413Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(PBS3CG1STATE pThis, unsigned off, uint8_t iReg)
    14151414{
    14161415    pThis->aOperands[pThis->iRegOp].idxField = pThis->aOperands[pThis->iRegOp].idxFieldBase + iReg;
    1417     return Bs3Cfg1EncodeMemMod0Disp(pThis, fAddrOverride, off, iReg & 7, pThis->aOperands[pThis->iRmOp].cbOp, cbMisalign,
     1416    return Bs3Cfg1EncodeMemMod0Disp(pThis, false /*fAddrOverride*/, off, iReg & 7,
     1417                                    pThis->aOperands[pThis->iRmOp].cbOp,
     1418                                    0 /*cbMisalign*/,
     1419                                    pThis->aOperands[pThis->iRmOp].enmLocation);
     1420}
     1421
     1422
     1423/** Also encodes idxField of the register operand using idxFieldBase. */
     1424static unsigned BS3_NEAR_CODE
     1425Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(PBS3CG1STATE pThis, unsigned off, uint8_t iReg, uint8_t cbMisalign)
     1426{
     1427    pThis->aOperands[pThis->iRegOp].idxField = pThis->aOperands[pThis->iRegOp].idxFieldBase + iReg;
     1428    return Bs3Cfg1EncodeMemMod0Disp(pThis, false /*fAddrOverride*/, off, iReg & 7,
     1429                                    pThis->aOperands[pThis->iRmOp].cbOp,
     1430                                    cbMisalign,
    14181431                                    pThis->aOperands[pThis->iRmOp].enmLocation);
    14191432}
    … …  
    17261739            pThis->aOperands[pThis->iRmOp ].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationMem;
    17271740            off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
    1728             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 4 /*iReg*/, 0 /*cbMisalign*/);
     1741            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 4 /*iReg*/);
    17291742            break;
    17301743        case 4:
    17311744            off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
    1732             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 7 /*iReg*/, 1 /*cbMisalign*/);
     1745            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 7 /*iReg*/, 1 /*cbMisalign*/);
    17331746            iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
    17341747            break;
    … …  
    17381751            pThis->abCurInstr[off++] = REX__RBX;
    17391752            off = Bs3Cg1InsertOpcodes(pThis, off);
    1740             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 7 /*iReg - no +8*/, 0 /*cbMisalign*/);
     1753            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7 /*iReg - no +8*/);
    17411754            break;
    17421755#endif
    … …  
    18071820            pThis->aOperands[pThis->iRmOp ].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationMem;
    18081821            off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
    1809             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 4 /*iReg*/, 0 /*cbMisalign*/);
     1822            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 4 /*iReg*/);
    18101823            break;
    18111824        case 4:
    18121825            off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
    1813             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 7 /*iReg*/, 1 /*cbMisalign*/);
     1826            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 7 /*iReg*/, 1 /*cbMisalign*/);
    18141827            iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
    18151828            break;
    … …  
    18191832            pThis->abCurInstr[off++] = REX__RBX;
    18201833            off = Bs3Cg1InsertOpcodes(pThis, off);
    1821             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 7 /*iReg*/, 0 /*cbMisalign*/);
     1834            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7 /*iReg*/);
    18221835            break;
    18231836#endif
    … …  
    18691882                pThis->abCurInstr[off++] = REX_W___;
    18701883                off = Bs3Cg1InsertOpcodes(pThis, off);
    1871                 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 4 /*iReg*/, 0 /*cbMisalign*/);
     1884                off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 4 /*iReg*/);
    18721885                break;
    18731886            case 4:
    … …  
    18751888                pThis->abCurInstr[off++] = REX_W___;
    18761889                off = Bs3Cg1InsertOpcodes(pThis, off);
    1877                 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 7 /*iReg*/, 1 /*cbMisalign*/);
     1890                off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 7 /*iReg*/, 1 /*cbMisalign*/);
    18781891                break;
    18791892            case 5:
    … …  
    18811894                pThis->abCurInstr[off++] = REX_WRBX;
    18821895                off = Bs3Cg1InsertOpcodes(pThis, off);
    1883                 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 7 /*iReg*/, 0 /*cbMisalign*/);
     1896                off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7 /*iReg*/);
    18841897                break;
    18851898
    … …  
    19281941            pThis->aOperands[pThis->iRmOp ].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationMem;
    19291942            off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
    1930             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 4 /*iReg*/, 0 /*cbMisalign*/);
     1943            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 4 /*iReg*/);
    19311944            break;
    19321945        case 4:
    19331946            off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
    1934             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 7 /*iReg*/, 1 /*cbMisalign*/);
     1947            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 7 /*iReg*/, 1 /*cbMisalign*/);
    19351948            iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
    19361949            break;
    … …  
    19401953            pThis->abCurInstr[off++] = REX__RBX;
    19411954            off = Bs3Cg1InsertOpcodes(pThis, off);
    1942             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 7+8 /*iReg*/, 0 /*cbMisalign*/);
     1955            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7+8 /*iReg*/);
    19431956            break;
    19441957#endif
    … …  
    19912004                pThis->abCurInstr[off++] = REX_W___;
    19922005                off = Bs3Cg1InsertOpcodes(pThis, off);
    1993                 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 4 /*iReg*/, 0 /*cbMisalign*/);
     2006                off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 4 /*iReg*/);
    19942007                break;
    19952008            case 5:
    … …  
    19972010                pThis->abCurInstr[off++] = REX_W___;
    19982011                off = Bs3Cg1InsertOpcodes(pThis, off);
    1999                 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 7 /*iReg*/, 1 /*cbMisalign*/);
     2012                off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 7 /*iReg*/, 1 /*cbMisalign*/);
    20002013                break;
    20012014            case 6:
    … …  
    20032016                pThis->abCurInstr[off++] = REX_WRBX;
    20042017                off = Bs3Cg1InsertOpcodes(pThis, off);
    2005                 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 7+8 /*iReg*/, 0 /*cbMisalign*/);
     2018                off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7+8 /*iReg*/);
    20062019                break;
    20072020
    … …  
    23562369        case 0:
    23572370            off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
    2358             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 4 /*iReg*/, 0 /*cbMisalign*/);
     2371            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 4 /*iReg*/);
    23592372            break;
    23602373        case 1:
    23612374            off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
    2362             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 7 /*iReg*/, 1 /*cbMisalign*/);
     2375            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 7 /*iReg*/, 1 /*cbMisalign*/);
    23632376            iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
    23642377            break;
    … …  
    23682381            pThis->abCurInstr[off++] = REX__RBX;
    23692382            off = Bs3Cg1InsertOpcodes(pThis, off);
    2370             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 7 /*iReg - no +8*/, 0 /*cbMisalign*/);
     2383            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7 /*iReg - no +8*/);
    23712384            break;
    23722385#endif
    … …  
    23812394
    23822395
    2383 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Mq_WO_Vq(PBS3CG1STATE pThis, unsigned iEncoding)
     2396static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Msomething_WO_Vsomething(PBS3CG1STATE pThis, unsigned iEncoding)
    23842397{
    23852398    unsigned off;
    2386     if (iEncoding == 0)
    2387     {
    2388         pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2_LO;
    2389         off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
    2390         off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /*iReg*/, 8, 0, BS3CG1OPLOC_MEM_WO);
    2391     }
    2392     else if (iEncoding == 1)
    2393     {
    2394         pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3_LO;
    2395         off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
    2396         off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /*iReg*/, 8, 1 /*cbMisalign*/, BS3CG1OPLOC_MEM_WO);
    2397     }
    2398     else
    2399         return 0;
     2399    switch (iEncoding)
     2400    {
     2401        case 0:
     2402            off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
     2403            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2 /*iReg*/);
     2404            break;
     2405        case 1:
     2406            off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
     2407            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 3 /*iReg*/, 1 /*cbMisalign*/);
     2408            break;
     2409        default:
     2410            return 0;
     2411    }
    24002412    pThis->cbCurInstr = off;
    24012413    return iEncoding + 1;
    … …  
    24032415
    24042416
    2405 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Mq_WO_VqHi(PBS3CG1STATE pThis, unsigned iEncoding)
    2406 {
    2407     unsigned off;
    2408     if (iEncoding == 0)
    2409     {
    2410         pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2_HI;
    2411         off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
    2412         off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /*iReg*/, 8, 0, BS3CG1OPLOC_MEM_WO);
    2413     }
    2414     else if (iEncoding == 1)
    2415     {
    2416         pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3_HI;
    2417         off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
    2418         off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /*iReg*/, 8, 1 /*cbMisalign*/, BS3CG1OPLOC_MEM_WO);
    2419     }
    2420     else
    2421         return 0;
    2422     pThis->cbCurInstr = off;
    2423     return iEncoding + 1;
    2424 }
    2425 
    2426 
    24272417static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_MsomethingWO_Vsomething_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding)
    24282418{
    … …  
    24322422        case 0:
    24332423            off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
    2434             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 2 /*iReg*/, 0);
     2424            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2 /*iReg*/);
    24352425            break;
    24362426        case 1:
    24372427            off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
    2438             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 2 /*iReg*/, 1 /*cbMisalign*/ );
     2428            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 2 /*iReg*/, 1 /*cbMisalign*/ );
    24392429            if (!Bs3Cg1XcptTypeIsUnaligned(pThis->enmXcptType))
    24402430                pThis->bAlignmentXcpt = X86_XCPT_GP;
    … …  
    24452435            pThis->abCurInstr[off++] = REX__R__;
    24462436            off = Bs3Cg1InsertOpcodes(pThis, off);
    2447             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 2+8 /*iReg*/, 0);
     2437            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2+8 /*iReg*/);
    24482438            break;
    24492439        default:
    … …  
    27432733            off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/);
    27442734            off = Bs3Cg1InsertOpcodes(pThis, off);
    2745             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 4 /*iReg*/, 0 /*cbMisalign*/);
     2735            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 4 /*iReg*/);
    27462736            break;
    27472737        case 6:
    27482738            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
    27492739            off = Bs3Cg1InsertOpcodes(pThis, off);
    2750             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 4 /*iReg*/, 0 /*cbMisalign*/);
     2740            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 4 /*iReg*/);
    27512741            break;
    27522742        case 7:
    27532743            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
    27542744            off = Bs3Cg1InsertOpcodes(pThis, off);
    2755             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 4 /*iReg*/, 1 /*cbMisalign*/);
     2745            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 4 /*iReg*/, 1 /*cbMisalign*/);
    27562746            iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 2 : 0;
    27572747            break;
    … …  
    27602750            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 0 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
    27612751            off = Bs3Cg1InsertOpcodes(pThis, off);
    2762             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 4+8 /*iReg*/, 0 /*cbMisalign*/);
     2752            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 4+8 /*iReg*/);
    27632753            break;
    27642754        case 9:
    27652755            off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 0 /*~R*/);
    27662756            off = Bs3Cg1InsertOpcodes(pThis, off);
    2767             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 5+8 /*iReg*/, 0 /*cbMisalign*/);
     2757            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5+8 /*iReg*/);
    27682758            iEncoding += 2;
    27692759            break;
    … …  
    27732763            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W*/);
    27742764            off = Bs3Cg1InsertOpcodes(pThis, off);
    2775             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 4 /*iReg*/, 0 /*cbMisalign*/);
     2765            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 4 /*iReg*/);
    27762766            break;
    27772767
    … …  
    28282818                off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W*/);
    28292819                off = Bs3Cg1InsertOpcodes(pThis, off);
    2830                 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 4 /*iReg*/, 0 /*cbMisalign*/);
     2820                off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 4 /*iReg*/);
    28312821                break;
    28322822            case 5:
    28332823                off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W*/);
    28342824                off = Bs3Cg1InsertOpcodes(pThis, off);
    2835                 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 4 /*iReg*/, 1 /*cbMisalign*/);
     2825                off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 4 /*iReg*/, 1 /*cbMisalign*/);
    28362826                iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 2 : 0;
    28372827                break;
    … …  
    28392829                off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 0 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W*/);
    28402830                off = Bs3Cg1InsertOpcodes(pThis, off);
    2841                 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 4+8 /*iReg*/, 0 /*cbMisalign*/);
     2831                off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 4+8 /*iReg*/);
    28422832                break;
    28432833
    … …  
    30413031            off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, iEncoding >= 20 /*L*/, 1 /*~R*/);
    30423032            off = Bs3Cg1InsertOpcodes(pThis, off);
    3043             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 0, 0);
     3033            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 0);
    30443034            iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
    30453035            break;
    … …  
    30493039            off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, iEncoding >= 20 /*L*/, 0 /*~R*/);
    30503040            off = Bs3Cg1InsertOpcodes(pThis, off);
    3051             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 7 + 8, 0);
     3041            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7 + 8);
    30523042            break;
    30533043#endif
    … …  
    30563046            off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xe /*~V*/, iEncoding >= 20 /*L*/, 1 /*~R*/);
    30573047            off = Bs3Cg1InsertOpcodes(pThis, off);
    3058             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 0, 0);
     3048            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 0);
    30593049            pThis->fInvalidEncoding = true;
    30603050            break;
    … …  
    30633053            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, iEncoding >= 20 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
    30643054            off = Bs3Cg1InsertOpcodes(pThis, off);
    3065             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 1, 0);
     3055            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 1);
    30663056            break;
    30673057        case 4:
    … …  
    30693059            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, iEncoding >= 20 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W-ignored*/);
    30703060            off = Bs3Cg1InsertOpcodes(pThis, off);
    3071             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 5, 0);
     3061            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5);
    30723062            iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 3 : 0;
    30733063            break;
    … …  
    30773067            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, iEncoding >= 20 /*L*/, 0 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
    30783068            off = Bs3Cg1InsertOpcodes(pThis, off);
    3079             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 5+8, 0);
     3069            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5+8);
    30803070            break;
    30813071        case 6:
    … …  
    30833073            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, iEncoding >= 20 /*L*/, 1 /*~R*/, 1 /*~X*/, 0 /*~B-ignored*/, 0 /*W*/);
    30843074            off = Bs3Cg1InsertOpcodes(pThis, off);
    3085             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 1, 0);
     3075            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 1);
    30863076            break;
    30873077        case 7:
    … …  
    30893079            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, iEncoding >= 20 /*L*/, 1 /*~R*/, 0 /*~X-ignored*/, 1 /*~B*/, 0 /*W*/);
    30903080            off = Bs3Cg1InsertOpcodes(pThis, off);
    3091             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 2, 0);
     3081            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2);
    30923082            break;
    30933083#endif
    … …  
    30963086            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0 /*~V*/, iEncoding >= 20 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
    30973087            off = Bs3Cg1InsertOpcodes(pThis, off);
    3098             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 5, 0);
     3088            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5);
    30993089            pThis->fInvalidEncoding = true;
    31003090            break;
    … …  
    31033093            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 7 /*~V*/, iEncoding >= 20 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
    31043094            off = Bs3Cg1InsertOpcodes(pThis, off);
    3105             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 2, 0);
     3095            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2);
    31063096            pThis->fInvalidEncoding = true;
    31073097            iEncoding += 10;
    … …  
    31303120            off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/);
    31313121            off = Bs3Cg1InsertOpcodes(pThis, off);
    3132             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 0, 0);
     3122            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 0);
    31333123            break;
    31343124        case 1:
    31353125            off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L - ignored*/, 1 /*~R*/);
    31363126            off = Bs3Cg1InsertOpcodes(pThis, off);
    3137             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 7, 0);
     3127            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7);
    31383128            iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
    31393129            break;
    … …  
    31423132            off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L - ignored*/, 0 /*~R*/);
    31433133            off = Bs3Cg1InsertOpcodes(pThis, off);
    3144             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 7 + 8, 0);
     3134            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7 + 8);
    31453135            break;
    31463136#endif
    … …  
    31493139            off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xe /*~V*/, 0 /*L*/, 1 /*~R*/);
    31503140            off = Bs3Cg1InsertOpcodes(pThis, off);
    3151             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 0, 0);
     3141            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 0);
    31523142            pThis->fInvalidEncoding = true;
    31533143            break;
    … …  
    31553145            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
    31563146            off = Bs3Cg1InsertOpcodes(pThis, off);
    3157             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 1, 0);
     3147            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 1);
    31583148            break;
    31593149        case 5:
    31603150            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L-ignored*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
    31613151            off = Bs3Cg1InsertOpcodes(pThis, off);
    3162             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 1, 0);
     3152            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 1);
    31633153            break;
    31643154        case 6:
    31653155            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W-ignored*/);
    31663156            off = Bs3Cg1InsertOpcodes(pThis, off);
    3167             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 5, 0);
     3157            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5);
    31683158            iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 3 : 0;
    31693159            break;
    … …  
    31723162            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 0 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
    31733163            off = Bs3Cg1InsertOpcodes(pThis, off);
    3174             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 5+8, 0);
     3164            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5+8);
    31753165            break;
    31763166        case 8:
    31773167            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 0 /*~B-ignored*/, 0 /*W*/);
    31783168            off = Bs3Cg1InsertOpcodes(pThis, off);
    3179             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 1, 0);
     3169            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 1);
    31803170            break;
    31813171        case 9:
    31823172            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 0 /*~X-ignored*/, 1 /*~B*/, 0 /*W*/);
    31833173            off = Bs3Cg1InsertOpcodes(pThis, off);
    3184             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 2, 0);
     3174            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2);
    31853175            break;
    31863176#endif
    … …  
    31883178            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0 /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
    31893179            off = Bs3Cg1InsertOpcodes(pThis, off);
    3190             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 5, 0);
     3180            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5);
    31913181            pThis->fInvalidEncoding = true;
    31923182            break;
    … …  
    31943184            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 7 /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
    31953185            off = Bs3Cg1InsertOpcodes(pThis, off);
    3196             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 2, 0);
     3186            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2);
    31973187            pThis->fInvalidEncoding = true;
    31983188            break;
    … …  
    32183208            off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/);
    32193209            off = Bs3Cg1InsertOpcodes(pThis, off);
    3220             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 0, 0);
     3210            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 0);
    32213211            break;
    32223212        case 1:
    32233213            off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L - invalid*/, 1 /*~R*/);
    32243214            off = Bs3Cg1InsertOpcodes(pThis, off);
    3225             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 7, 0);
     3215            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7);
    32263216            pThis->fInvalidEncoding = true;
    32273217            iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 2 : 0;
    … …  
    32313221            off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 0 /*~R*/);
    32323222            off = Bs3Cg1InsertOpcodes(pThis, off);
    3233             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 7 + 8, 0);
     3223            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7 + 8);
    32343224            break;
    32353225        case 3:
    32363226            off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L - invalid*/, 0 /*~R*/);
    32373227            off = Bs3Cg1InsertOpcodes(pThis, off);
    3238             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 5 + 8, 0);
     3228            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5 + 8);
    32393229            pThis->fInvalidEncoding = true;
    32403230            break;
    … …  
    32433233            off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xe /*~V*/, 0 /*L*/, 1 /*~R*/);
    32443234            off = Bs3Cg1InsertOpcodes(pThis, off);
    3245             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 0, 0);
     3235            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 0);
    32463236            pThis->fInvalidEncoding = true;
    32473237            break;
    … …  
    32493239            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
    32503240            off = Bs3Cg1InsertOpcodes(pThis, off);
    3251             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 1, 0);
     3241            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 1);
    32523242            break;
    32533243        case 6:
    32543244            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L - invalid*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
    32553245            off = Bs3Cg1InsertOpcodes(pThis, off);
    3256             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 1, 0);
     3246            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 1);
    32573247            pThis->fInvalidEncoding = true;
    32583248            break;
    … …  
    32603250            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W-ignored*/);
    32613251            off = Bs3Cg1InsertOpcodes(pThis, off);
    3262             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 5, 0);
     3252            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5);
    32633253            iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 3 : 0;
    32643254            break;
    … …  
    32673257            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 0 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
    32683258            off = Bs3Cg1InsertOpcodes(pThis, off);
    3269             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 5+8, 0);
     3259            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5+8);
    32703260            break;
    32713261        case 9:
    32723262            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 0 /*~B-ignored*/, 0 /*W*/);
    32733263            off = Bs3Cg1InsertOpcodes(pThis, off);
    3274             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 1, 0);
     3264            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 1);
    32753265            break;
    32763266        case 10:
    32773267            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 0 /*~X-ignored*/, 1 /*~B*/, 0 /*W*/);
    32783268            off = Bs3Cg1InsertOpcodes(pThis, off);
    3279             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 2, 0);
     3269            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2);
    32803270            break;
    32813271#endif
    … …  
    32833273            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0 /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
    32843274            off = Bs3Cg1InsertOpcodes(pThis, off);
    3285             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 5, 0);
     3275            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5);
    32863276            pThis->fInvalidEncoding = true;
    32873277            break;
    … …  
    32893279            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 7 /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
    32903280            off = Bs3Cg1InsertOpcodes(pThis, off);
    3291             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 2, 0);
     3281            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2);
    32923282            pThis->fInvalidEncoding = true;
    32933283            break;
    … …  
    33123302            off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, uVexL, 1 /*~R*/);
    33133303            off = Bs3Cg1InsertOpcodes(pThis, off);
    3314             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 0, 0);
     3304            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 0);
    33153305            iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
    33163306            break;
    … …  
    33193309            off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, uVexL, 0 /*~R*/);
    33203310            off = Bs3Cg1InsertOpcodes(pThis, off);
    3321             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 7 + 8, 0);
     3311            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7 + 8);
    33223312            break;
    33233313#endif
    … …  
    33253315            off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xe /*~V*/, uVexL, 1 /*~R*/);
    33263316            off = Bs3Cg1InsertOpcodes(pThis, off);
    3327             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 0, 0);
     3317            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 0);
    33283318            pThis->fInvalidEncoding = true;
    33293319            break;
    … …  
    33313321            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, uVexL, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
    33323322            off = Bs3Cg1InsertOpcodes(pThis, off);
    3333             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 1, 0);
     3323            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 1);
    33343324            break;
    33353325        case 4:
    33363326            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, uVexL, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W-ignored*/);
    33373327            off = Bs3Cg1InsertOpcodes(pThis, off);
    3338             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 5, 0);
     3328            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5);
    33393329            iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 3 : 0;
    33403330            break;
    … …  
    33433333            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, uVexL, 0 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
    33443334            off = Bs3Cg1InsertOpcodes(pThis, off);
    3345             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 5+8, 0);
     3335            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5+8);
    33463336            break;
    33473337        case 6:
    33483338            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, uVexL, 1 /*~R*/, 1 /*~X*/, 0 /*~B-ignored*/, 0 /*W*/);
    33493339            off = Bs3Cg1InsertOpcodes(pThis, off);
    3350             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 1, 0);
     3340            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 1);
    33513341            break;
    33523342        case 7:
    33533343            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, uVexL, 1 /*~R*/, 0 /*~X-ignored*/, 1 /*~B*/, 0 /*W*/);
    33543344            off = Bs3Cg1InsertOpcodes(pThis, off);
    3355             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 2, 0);
     3345            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2);
    33563346            break;
    33573347#endif
    … …  
    33593349            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0 /*~V*/, uVexL, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
    33603350            off = Bs3Cg1InsertOpcodes(pThis, off);
    3361             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 5, 0);
     3351            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5);
    33623352            pThis->fInvalidEncoding = true;
    33633353            break;
    … …  
    33653355            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 7 /*~V*/, uVexL, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
    33663356            off = Bs3Cg1InsertOpcodes(pThis, off);
    3367             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 2, 0);
     3357            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2);
    33683358            pThis->fInvalidEncoding = true;
    33693359            break;
    … …  
    34113401            off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xc /*~V*/, 0 /*L*/, 1 /*~R*/);
    34123402            off = Bs3Cg1InsertOpcodes(pThis, off);
    3413             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 0, 0);
     3403            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 0);
    34143404            pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 3;
    34153405            break;
    … …  
    34173407            off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L*/, 1 /*~R*/);
    34183408            off = Bs3Cg1InsertOpcodes(pThis, off);
    3419             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 7, 0);
     3409            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7);
    34203410            pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 0;
    34213411            pThis->fInvalidEncoding = true;
    … …  
    34263416            off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0x1 /*~V*/, 0 /*L*/, 0 /*~R*/);
    34273417            off = Bs3Cg1InsertOpcodes(pThis, off);
    3428             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 7 + 8, 0);
     3418            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7 + 8);
    34293419            pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 14;
    34303420            break;
    … …  
    34333423            off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xe /*~V*/, 0 /*L*/, 1 /*~R*/);
    34343424            off = Bs3Cg1InsertOpcodes(pThis, off);
    3435             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 0, 0);
     3425            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 0);
    34363426            pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 1;
    34373427            break;
    … …  
    34393429            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
    34403430            off = Bs3Cg1InsertOpcodes(pThis, off);
    3441             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 1, 0);
     3431            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 1);
    34423432            pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 0;
    34433433            break;
    … …  
    34453435            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L-ignored*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
    34463436            off = Bs3Cg1InsertOpcodes(pThis, off);
    3447             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 1, 0);
     3437            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 1);
    34483438            pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 0;
    34493439            pThis->fInvalidEncoding = true;
    … …  
    34523442            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W-ignored*/);
    34533443            off = Bs3Cg1InsertOpcodes(pThis, off);
    3454             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 5, 0);
     3444            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5);
    34553445            pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 0;
    34563446            iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 3 : 0;
    … …  
    34603450            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 0 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
    34613451            off = Bs3Cg1InsertOpcodes(pThis, off);
    3462             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 5+8, 0);
     3452            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5+8);
    34633453            pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 0;
    34643454            break;
    … …  
    34663456            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 0 /*~B-ignored*/, 0 /*W*/);
    34673457            off = Bs3Cg1InsertOpcodes(pThis, off);
    3468             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 1, 0);
     3458            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 1);
    34693459            pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 0;
    34703460            break;
    … …  
    34723462            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 0 /*~X-ignored*/, 1 /*~B*/, 0 /*W*/);
    34733463            off = Bs3Cg1InsertOpcodes(pThis, off);
    3474             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 2, 0);
     3464            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2);
    34753465            pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 0;
    34763466            break;
    … …  
    34793469            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0 /*~V*/, 1 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
    34803470            off = Bs3Cg1InsertOpcodes(pThis, off);
    3481             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 5, 0);
     3471            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5);
    34823472            pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + (BS3CG1_IS_64BIT_TARGET(pThis) ? 15 : 7);
    34833473            pThis->fInvalidEncoding = true;
    … …  
    36013591            off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/);
    36023592            off = Bs3Cg1InsertOpcodes(pThis, off);
    3603             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 2 /*iReg*/, 0);
     3593            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2 /*iReg*/);
    36043594            break;
    36053595        case 4:
    36063596            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
    36073597            off = Bs3Cg1InsertOpcodes(pThis, off);
    3608             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 3 /*iReg*/, 0);
     3598            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 3 /*iReg*/);
    36093599            break;
    36103600        case 5:
    36113601            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W - ignored */);
    36123602            off = Bs3Cg1InsertOpcodes(pThis, off);
    3613             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 3 /*iReg*/, 0);
     3603            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 3 /*iReg*/);
    36143604            break;
    36153605        case 6:
    36163606            off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/);
    36173607            off = Bs3Cg1InsertOpcodes(pThis, off);
    3618             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 3 /*iReg*/, 1 /*cbMisalign*/);
     3608            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 3 /*iReg*/, 1 /*cbMisalign*/);
    36193609            if (!Bs3Cg1XcptTypeIsVexUnaligned(pThis->enmXcptType))
    36203610                pThis->bAlignmentXcpt = X86_XCPT_GP;
    … …  
    36233613            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
    36243614            off = Bs3Cg1InsertOpcodes(pThis, off);
    3625             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 3 /*iReg*/, 1 /*cbMisalign*/);
     3615            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 3 /*iReg*/, 1 /*cbMisalign*/);
    36263616            if (!Bs3Cg1XcptTypeIsVexUnaligned(pThis->enmXcptType))
    36273617                pThis->bAlignmentXcpt = X86_XCPT_GP;
    … …  
    37023692            off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, iEncoding >= 20 /*L*/, 1 /*~R*/);
    37033693            off = Bs3Cg1InsertOpcodes(pThis, off);
    3704             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 2 /*iReg*/, 0);
     3694            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2 /*iReg*/);
    37053695            break;
    37063696        case 4:
    … …  
    37083698            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, iEncoding >= 20 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
    37093699            off = Bs3Cg1InsertOpcodes(pThis, off);
    3710             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 3 /*iReg*/, 0);
     3700            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 3 /*iReg*/);
    37113701            break;
    37123702        case 5:
    … …  
    37143704            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, iEncoding >= 20 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W - ignored */);
    37153705            off = Bs3Cg1InsertOpcodes(pThis, off);
    3716             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 3 /*iReg*/, 0);
     3706            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 3 /*iReg*/);
    37173707            break;
    37183708        case 6:
    … …  
    37203710            off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, iEncoding >= 20 /*L*/, 1 /*~R*/);
    37213711            off = Bs3Cg1InsertOpcodes(pThis, off);
    3722             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 3 /*iReg*/, 1 /*cbMisalign*/);
     3712            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 3 /*iReg*/, 1 /*cbMisalign*/);
    37233713            if (!Bs3Cg1XcptTypeIsVexUnaligned(pThis->enmXcptType))
    37243714                pThis->bAlignmentXcpt = X86_XCPT_GP;
    … …  
    37283718            off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, iEncoding >= 20 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/);
    37293719            off = Bs3Cg1InsertOpcodes(pThis, off);
    3730             off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 3 /*iReg*/, 1 /*cbMisalign*/);
     3720            off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 3 /*iReg*/, 1 /*cbMisalign*/);
    37313721            if (!Bs3Cg1XcptTypeIsVexUnaligned(pThis->enmXcptType))
    37323722                pThis->bAlignmentXcpt = X86_XCPT_GP;
    … …  
    39983988        case BS3CG1ENC_MODRM_Md_WO:
    39993989            return Bs3Cg1EncodeNext_MODRM_Md_WO(pThis, iEncoding);
    4000         case BS3CG1ENC_MODRM_Mq_WO_Vq:
    4001             return Bs3Cg1EncodeNext_MODRM_Mq_WO_Vq(pThis, iEncoding);
    4002         case BS3CG1ENC_MODRM_Mq_WO_VqHi:
    4003             return Bs3Cg1EncodeNext_MODRM_Mq_WO_VqHi(pThis, iEncoding);
    40043990
    40053991        case BS3CG1ENC_FIXED:
    … …  
    43894375        case BS3CG1ENC_MODRM_Mq_WO_Vq:
    43904376        case BS3CG1ENC_MODRM_Mq_WO_VqHi:
     4377            pThis->pfnEncoder        = Bs3Cg1EncodeNext_MODRM_Msomething_WO_Vsomething;
    43914378            pThis->iRmOp             = 0;
    43924379            pThis->iRegOp            = 1;
    43934380            pThis->aOperands[0].cbOp = 8;
    43944381            pThis->aOperands[1].cbOp = 8;
    4395             pThis->aOperands[0].enmLocation = BS3CG1OPLOC_MEM_WO;
    4396             pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
     4382            pThis->aOperands[0].enmLocation    = BS3CG1OPLOC_MEM_WO;
     4383            pThis->aOperands[0].enmLocationMem = BS3CG1OPLOC_MEM_WO;
     4384            pThis->aOperands[1].enmLocation    = BS3CG1OPLOC_CTX;
     4385            pThis->aOperands[1].idxFieldBase   = pThis->enmEncoding == BS3CG1ENC_MODRM_Mq_WO_Vq
     4386                                               ? BS3CG1DST_XMM0_LO : BS3CG1DST_XMM0_HI;
    43974387            break;
    43984388
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