Changeset 67562 in vbox for trunk/src/VBox/Devices

Timestamp:

Jun 22, 2017 2:10:15 PM (8 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

116314

Message:

DevPciIch9.cpp: improve reset handling to be less broken (making less assumptions about the config space cache being authoritative), and additionally actually recursively reset all devices/bridges connected to a bridge, making the topology updates only once the bridge doesn't need to work any more.

File:

• trunk/src/VBox/Devices/Bus/DevPciIch9.cpp (modified) (10 diffs)

trunk/src/VBox/Devices/Bus/DevPciIch9.cpp

@@ -96 +96 @@
                                   int iIrq, int iLevel, uint32_t uTagSrc);
 #ifdef IN_RING3
-static void ich9pcibridgeReset(PPDMDEVINS pDevIns);
 DECLINLINE(PPDMPCIDEV) ich9pciFindBridge(PDEVPCIBUS pBus, uint8_t uBus);
 static void ich9pciBiosInitAllDevicesOnBus(PDEVPCIROOT pPciRoot, uint8_t uBus);
@@ -135 +134 @@
      * of our parent passing the device which asserted the interrupt instead of the device of the bridge.
      */
-    PDEVPCIBUS    pBus          = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
+    PDEVPCIBUS     pBus          = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
     PPDMPCIDEV     pPciDevBus    = pPciDev;
     int            iIrqPinBridge = iIrq;
@@ -1462 +1461 @@
 {
     PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
-    PDEVPCIBUS     pBus  = &pThis->PciBus;
-    uint32_t        u32;
-    int             rc;
+    PDEVPCIBUS  pBus  = &pThis->PciBus;
+    uint32_t    u32;
+    int         rc;
 
     /* We ignore this version as there's no saved state with it anyway */
@@ -3002 +3001 @@
      */
     PDEVPCIROOT pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
-    PDEVPCIBUS     pBus     = &pPciRoot->PciBus;
+    PDEVPCIBUS  pBus     = &pPciRoot->PciBus;
     /* Zero out everything */
     memset(pPciRoot, 0, sizeof(*pPciRoot));
@@ -3181 +3180 @@
         if (pRegion->size == 0)
             continue;
+        bool const f64Bit =    (pRegion->type & ((uint8_t)(PCI_ADDRESS_SPACE_BAR64 | PCI_ADDRESS_SPACE_IO)))
+                            == PCI_ADDRESS_SPACE_BAR64;
 
         ich9pciUnmapRegion(pDev, iRegion);
+
+        if (f64Bit)
+            iRegion++;
     }
 
@@ -3209 +3213 @@
         if (pciDevIsMsiCapable(pDev))
         {
-            /* Extracted from MsiPciConfigWrite(). */
-            pDev->abConfig[pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL] &= 0x8e;
+            ich9pciSetWord(pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL,
+                           ich9pciGetWord(pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL) & 0xff8e);
         }
 
@@ -3216 +3220 @@
         if (pciDevIsMsixCapable(pDev))
         {
-            /* Extracted from MsixPciConfigWrite(); no side effects. */
-            pDev->abConfig[pDev->Int.s.u8MsixCapOffset + VBOX_MSIX_CAP_MESSAGE_CONTROL + 1] &= 0x3f;
+            ich9pciSetWord(pDev, pDev->Int.s.u8MsixCapOffset + VBOX_MSIX_CAP_MESSAGE_CONTROL,
+                           ich9pciGetWord(pDev, pDev->Int.s.u8MsixCapOffset + VBOX_MSIX_CAP_MESSAGE_CONTROL) & 0x3fff);
         }
     }
@@ -3224 +3228 @@
 
 /**
- * @copydoc FNPDMDEVRESET
- */
-static DECLCALLBACK(void) ich9pciReset(PPDMDEVINS pDevIns)
-{
-    PDEVPCIROOT pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
-    PDEVPCIBUS     pBus     = &pPciRoot->PciBus;
+ * Recursive worker for ich9pciReset.
+ *
+ * @param   pDevIns     ICH9 bridge (root or PCI-to-PCI) instance.
+ */
+static void ich9pciResetBridge(PPDMDEVINS pDevIns)
+{
+    PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
 
     /* PCI-specific reset for each device. */
@@ -3241 +3246 @@
     {
         if (pBus->papBridgesR3[iBridge])
-            ich9pcibridgeReset(pBus->papBridgesR3[iBridge]->Int.s.CTX_SUFF(pDevIns));
-    }
-
+            ich9pciResetBridge(pBus->papBridgesR3[iBridge]->Int.s.CTX_SUFF(pDevIns));
+    }
+
+    /* Reset topology config for non-root bridge. Last thing to do, otherwise
+     * the secondary and subordinate are instantly unreachable. */
+    if (pBus->iBus != 0)
+    {
+        ich9pciSetByte(&pBus->PciDev, VBOX_PCI_PRIMARY_BUS, 0);
+        ich9pciSetByte(&pBus->PciDev, VBOX_PCI_SECONDARY_BUS, 0);
+        ich9pciSetByte(&pBus->PciDev, VBOX_PCI_SUBORDINATE_BUS, 0);
+        /* Not resetting the address decoders of the bridge to 0, since the
+         * PCI-to-PCI Bridge spec says that there is no default value. */
+    }
+}
+
+
+/**
+ * @interface_method_impl{PDMDEVREG,pfnReset}
+ */
+static DECLCALLBACK(void) ich9pciReset(PPDMDEVINS pDevIns)
+{
+    /* Reset everything under the root bridge. */
+    ich9pciResetBridge(pDevIns);
+
+    /* Do a fresh Fake PCI BIOS setup. */
     ich9pciFakePCIBIOS(pDevIns);
 }
@@ -3512 +3539 @@
     }
     return VINF_SUCCESS;
-}
-
-/**
- * @copydoc FNPDMDEVRESET
- */
-static void ich9pcibridgeReset(PPDMDEVINS pDevIns)
-{
-    PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
-
-    /* Reset config space to default values. */
-    ich9pciSetByte(&pBus->PciDev, VBOX_PCI_PRIMARY_BUS, 0);
-    ich9pciSetByte(&pBus->PciDev, VBOX_PCI_SECONDARY_BUS, 0);
-    ich9pciSetByte(&pBus->PciDev, VBOX_PCI_SUBORDINATE_BUS, 0);
-
-    /* PCI-specific reset for each device. */
-    for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
-    {
-        if (pBus->apDevices[i])
-            ich9pciResetDevice(pBus->apDevices[i]);
-    }
 }