Changeset 67660 in vbox

Timestamp:

Jun 28, 2017 10:17:05 AM (7 years ago)

Author:

vboxsync

Message:

VMM/HMSVMR0: Added decode assist for invlpg, mov CRx instruction VM-exits.

Location:

trunk

Files:

• include/VBox/vmm/hm_svm.h (modified) (1 diff)
• src/VBox/VMM/VMMR0/HMSVMR0.cpp (modified) (6 diffs)
• src/VBox/VMM/VMMR3/HM.cpp (modified) (1 diff)

trunk/include/VBox/vmm/hm_svm.h

@@ -297 +297 @@
 /** @} */
 
-/** @name SVMVMCB.u64ExitInfo1 for Mov CRX accesses.
- * @{
- */
-/** The access was via Mov CRx instruction bit number. */
+/** @name SVMVMCB.u64ExitInfo1 for Mov CRx accesses.
+ * @{
+ */
+/** The mask of whether the access was via a Mov CRx instruction. */
 #define SVM_EXIT1_MOV_CRX_MASK                RT_BIT_64(63)
-/** @} */
-
+/** The mask for the GPR number of the Mov CRx instruction.  */
+#define SVM_EXIT1_MOV_CRX_GPR_NUMBER          0xf
+/** @} */
+
+/** @name SVMVMCB.u64ExitInfo1 for Mov DRx accesses.
+ * @{
+ */
+/** The mask for the GPR number of the Mov DRx instruction.  */
+#define SVM_EXIT1_MOV_DRX_GPR_NUMBER          0xf
+/** @} */
 
 /** @name SVMVMCB.ctrl.u64InterceptCtrl

trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp

@@ -4572 +4572 @@
     PVM pVM = pVCpu->CTX_SUFF(pVM);
     Assert(!pVM->hm.s.fNestedPaging);
-
-    /** @todo Decode Assist. */
+    STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpg);
+
+    if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST)
+    {
+        Assert(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
+        PCSVMVMCB pVmcb = (PCSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
+        uint8_t const cbInstr   = pVmcb->ctrl.u64NextRIP - pCtx->rip;
+        RTGCPTR const GCPtrPage = pVmcb->ctrl.u64ExitInfo1;
+        VBOXSTRICTRC rcStrict = IEMExecDecodedInvlpg(pVCpu, cbInstr, GCPtrPage);
+        HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
+        return VBOXSTRICTRC_VAL(rcStrict);
+    }
+
     int rc = hmR0SvmInterpretInvlpg(pVM, pVCpu, pCtx);    /* Updates RIP if successful. */
-    STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpg);
     Assert(rc == VINF_SUCCESS || rc == VERR_EM_INTERPRETER);
     HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
@@ -4672 +4682 @@
 
     Log4(("hmR0SvmExitReadCRx: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
-
-    /** @todo Decode Assist. */
+    STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxRead[pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0]);
+
+    PVM pVM = pVCpu->CTX_SUFF(pVM);
+    if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST)
+    {
+        Assert(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
+        PCSVMVMCB pVmcb = (PCSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
+        bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
+        if (fMovCRx)
+        {
+            uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
+            uint8_t const iCrReg  = pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0;
+            uint8_t const iGReg   = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
+            VBOXSTRICTRC rcStrict = IEMExecDecodedMovCRxRead(pVCpu, cbInstr, iGReg, iCrReg);
+            HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
+            return VBOXSTRICTRC_VAL(rcStrict);
+        }
+        /* else: SMSW instruction, fall back below to IEM for this. */
+    }
+
     VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
     int rc = VBOXSTRICTRC_VAL(rc2);
@@ -4679 +4707 @@
               ("hmR0SvmExitReadCRx: EMInterpretInstruction failed rc=%Rrc\n", rc));
     Assert((pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0) <= 15);
-    STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxRead[pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0]);
     HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
     return rc;
@@ -4692 +4719 @@
     HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
 
-    /** @todo Decode Assist. */
-    VBOXSTRICTRC rcStrict = IEMExecOneBypassEx(pVCpu, CPUMCTX2CORE(pCtx), NULL);
-    if (RT_UNLIKELY(   rcStrict == VERR_IEM_ASPECT_NOT_IMPLEMENTED
-                    || rcStrict == VERR_IEM_INSTR_NOT_IMPLEMENTED))
-        rcStrict = VERR_EM_INTERPRETER;
+    uint8_t const iCrReg = pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0;
+    Assert(iCrReg <= 15);
+
+    VBOXSTRICTRC rcStrict;
+    PVM pVM = pVCpu->CTX_SUFF(pVM);
+    bool fDecodedInstr = false;
+    if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST)
+    {
+        Assert(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
+        PCSVMVMCB pVmcb = (PCSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
+        bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
+        if (fMovCRx)
+        {
+            uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
+            uint8_t const iGReg   = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
+            rcStrict = IEMExecDecodedMovCRxWrite(pVCpu, cbInstr, iCrReg, iGReg);
+            fDecodedInstr = true;
+        }
+        /* else: LMSW or CLTS instruction, fall back below to IEM for this. */
+    }
+
+    if (!fDecodedInstr)
+    {
+        rcStrict = IEMExecOneBypassEx(pVCpu, CPUMCTX2CORE(pCtx), NULL);
+        if (RT_UNLIKELY(   rcStrict == VERR_IEM_ASPECT_NOT_IMPLEMENTED
+                        || rcStrict == VERR_IEM_INSTR_NOT_IMPLEMENTED))
+            rcStrict = VERR_EM_INTERPRETER;
+    }
+
     if (rcStrict == VINF_SUCCESS)
     {
-        /* RIP has been updated by EMInterpretInstruction(). */
-        Assert((pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0) <= 15);
-        switch (pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0)
+        switch (iCrReg)
         {
             case 0:     /* CR0. */
@@ -4708 +4757 @@
 
             case 3:     /* CR3. */
-                Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
+                Assert(!pVM->hm.s.fNestedPaging);
                 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR3);
                 break;
@@ -4722 +4771 @@
             default:
                 AssertMsgFailed(("hmR0SvmExitWriteCRx: Invalid/Unexpected Write-CRx exit. u64ExitCode=%#RX64 %#x\n",
-                                 pSvmTransient->u64ExitCode, pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0));
+                                 pSvmTransient->u64ExitCode, iCrReg));
                 break;
         }

trunk/src/VBox/VMM/VMMR3/HM.cpp

@@ -1648 +1648 @@
 
     /*
+     * SVM R0 code assumes if the decode-assist feature exists, NRIP feature exists too.
+     */
+    AssertLogRelReturn(  !(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST)
+                       || (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
+                       VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO);
+
+    /*
      * Nested paging is determined in HMR3Init, verify the sanity of that.
      */