Changeset 67668 in vbox

Timestamp:

Jun 28, 2017 4:28:34 PM (8 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

116476

Message:

PDM: rip out the entire FakePCIBIOS support, no longer triggered from here
Devices/Bus: register magic port to trigger FakePCIBIOS
BIOS: disable the unneeded function for PCI resource/IRQ initialization (only partially used anyway) and use the magic port to trigger FakePCIBIOS

Location:

trunk

Files:

• include/VBox/vmm/pdmdev.h (modified) (2 diffs)
• src/VBox/Devices/Bus/DevPCI.cpp (modified) (27 diffs)
• src/VBox/Devices/Bus/DevPciIch9.cpp (modified) (35 diffs)
• src/VBox/Devices/PC/BIOS/pcibios.inc (modified) (6 diffs)
• src/VBox/VMM/VMMR3/PDM.cpp (modified) (1 diff)
• src/VBox/VMM/VMMR3/PDMDevHlp.cpp (modified) (3 diffs)
• src/VBox/VMM/VMMR3/PDMDevice.cpp (modified) (1 diff)
• src/VBox/VMM/include/PDMInternal.h (modified) (1 diff)

trunk/include/VBox/vmm/pdmdev.h ¶

@@ -610 +610 @@
     DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
 
-    /**
-     * Called to perform the job of the bios.
-     *
-     * This is only called for the first PCI Bus - it is expected to
-     * service all the PCI buses.
-     *
-     * @returns VBox status.
-     * @param   pDevIns     Device instance of the first bus.
-     * @remarks Caller enters the PDM critical section.
-     */
-    DECLR3CALLBACKMEMBER(int, pfnFakePCIBIOSR3,(PPDMDEVINS pDevIns));
-
     /** The name of the SetIrq RC entry point. */
     const char         *pszSetIrqRC;
@@ -633 +621 @@
 
 /** Current PDMPCIBUSREG version number. */
-#define PDM_PCIBUSREG_VERSION                   PDM_VERSION_MAKE(0xfffe, 6, 0)
+#define PDM_PCIBUSREG_VERSION                   PDM_VERSION_MAKE(0xfffe, 7, 0)
 
 /**

trunk/src/VBox/Devices/Bus/DevPCI.cpp ¶

@@ -116 +116 @@
     uint32_t config_addr;
 
-    Log(("pci_data_write: addr=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
+    LogFunc(("addr=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
 
     if (!(pGlobals->uConfigReg & (1 << 31))) {
@@ -150 +150 @@
         {
 #ifdef IN_RING3
-            Log(("pci_config_write: %s: addr=%02x val=%08x len=%d\n", pci_dev->pszNameR3, config_addr, val, len));
+            LogFunc(("%s: addr=%02x val=%08x len=%d\n", pci_dev->pszNameR3, config_addr, val, len));
             pci_dev->Int.s.pfnConfigWrite(pci_dev->Int.s.CTX_SUFF(pDevIns), pci_dev, config_addr, val, len);
 #else
@@ -198 +198 @@
 #ifdef IN_RING3
             *pu32 = pci_dev->Int.s.pfnConfigRead(pci_dev->Int.s.CTX_SUFF(pDevIns), pci_dev, config_addr, len);
-            Log(("pci_config_read: %s: addr=%02x val=%08x len=%d\n", pci_dev->pszNameR3, config_addr, *pu32, len));
+            LogFunc(("%s: addr=%02x val=%08x len=%d\n", pci_dev->pszNameR3, config_addr, *pu32, len));
 #else
             NOREF(len);
@@ -249 +249 @@
         apic_irq = irq_num + 0x10;
         apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
-        Log3(("apic_set_irq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
+        Log3Func(("%s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
               R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num));
         pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
@@ -257 +257 @@
             pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
             apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
-            Log3(("apic_set_irq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
+            Log3Func(("%s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
                   R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num));
             pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
         }
     } else {
-        Log3(("apic_set_irq: %s: irq_num1=%d level=%d iAcpiIrq=%d\n",
+        Log3Func(("%s: irq_num1=%d level=%d iAcpiIrq=%d\n",
               R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, iAcpiIrq));
         pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), iAcpiIrq, iLevel, uTagSrc);
@@ -288 +288 @@
 static void pciSetIrqInternal(PDEVPCIROOT pGlobals, uint8_t uDevFn, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
 {
-    PDEVPCIBUS     pBus =     &pGlobals->PciBus;
+    PDEVPCIBUS  pBus = &pGlobals->PciBus;
     uint8_t    *pbCfg = pGlobals->Piix3.PIIX3State.dev.abConfig;
     const bool  fIsAcpiDevice = pPciDev->abConfig[2] == 0x13 && pPciDev->abConfig[3] == 0x71;
@@ -364 +364 @@
             pic_level |= pGlobals->Piix3.iAcpiIrqLevel;
 
-        Log3(("pciSetIrq: %s: iLevel=%d iIrq=%d pic_irq=%d pic_level=%d uTagSrc=%#x\n",
+        Log3Func(("%s: iLevel=%d iIrq=%d pic_irq=%d pic_level=%d uTagSrc=%#x\n",
               R3STRING(pPciDev->pszNameR3), iLevel, iIrq, pic_irq, pic_level, uTagSrc));
         pBus->CTX_SUFF(pPciHlp)->pfnIsaSetIrq(pBus->CTX_SUFF(pDevIns), pic_irq, pic_level, uTagSrc);
@@ -617 +617 @@
                 if ((pGlobals->uPciBiosIo % _4K) != 0)
                     pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, _4K);
-                Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosIo));
+                LogFunc(("Aligned I/O start address. New address %#x\n", pGlobals->uPciBiosIo));
                 pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0);
 
@@ -623 +623 @@
                 if ((pGlobals->uPciBiosMmio % _1M) != 0)
                     pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, _1M);
-                Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosMmio));
+                LogFunc(("Aligned MMIO start address. New address %#x\n", pGlobals->uPciBiosMmio));
                 pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0));
 
@@ -705 +705 @@
                         u32Size = (~u32Size) + 1;
 
-                    Log2(("%s: Size of region %u for device %d on bus %d is %u\n", __FUNCTION__, i, uDevFn, uBus, u32Size));
+                    Log2Func(("Size of region %u for device %d on bus %d is %u\n", i, uDevFn, uBus, u32Size));
 
                     if (u32Size)
@@ -727 +727 @@
                         else
                         {
-                            Log(("%s: Start address of %s region %u is %#x\n", __FUNCTION__, (fIsPio ? "I/O" : "MMIO"), i, uNew));
+                            LogFunc(("%s: Start address of %s region %u is %#x\n", (fIsPio ? "I/O" : "MMIO"), i, uNew));
                             pci_set_io_region_addr(pGlobals, uBus, uDevFn, i, uNew);
                             if (fIsPio)
@@ -734 +734 @@
                                 fActiveMemRegion = true;
                             *paddr = uNew + u32Size;
-                            Log2(("%s: New address is %#x\n", __FUNCTION__, *paddr));
+                            Log2Func(("New address is %#x\n", *paddr));
                         }
                     }
@@ -772 +772 @@
 }
 
+/**
+ * Worker for Fake PCI BIOS config, triggered by magic port access by BIOS.
+ *
+ * @returns VBox status code.
+ *
+ * @param   pDevIns     i440FX device instance.
+ */
+static int pciR3FakePCIBIOS(PPDMDEVINS pDevIns)
+{
+    unsigned        i;
+    uint8_t         elcr[2]    = {0, 0};
+    PDEVPCIROOT     pGlobals   = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
+    PVM             pVM        = PDMDevHlpGetVM(pDevIns); Assert(pVM);
+    PVMCPU          pVCpu      = PDMDevHlpGetVMCPU(pDevIns); Assert(pVM);
+    uint32_t const  cbBelow4GB = MMR3PhysGetRamSizeBelow4GB(pVM);
+    uint64_t const  cbAbove4GB = MMR3PhysGetRamSizeAbove4GB(pVM);
+    RT_NOREF(cbBelow4GB, cbAbove4GB);
+
+    LogRel(("PCI: setting up resources and interrupts\n"));
+
+    /*
+     * Set the start addresses.
+     */
+    pGlobals->uPciBiosBus  = 0;
+    pGlobals->uPciBiosIo   = 0xd000;
+    pGlobals->uPciBiosMmio = UINT32_C(0xf0000000);
+
+    /*
+     * Activate IRQ mappings.
+     */
+    for (i = 0; i < 4; i++)
+    {
+        uint8_t irq = pci_irqs[i];
+        /* Set to trigger level. */
+        elcr[irq >> 3] |= (1 << (irq & 7));
+        /* Activate irq remapping in PIIX3. */
+        pci_config_writeb(pGlobals, 0, pGlobals->Piix3.PIIX3State.dev.uDevFn, 0x60 + i, irq);
+    }
+
+    /* Tell to the PIC. */
+    VBOXSTRICTRC rcStrict = IOMIOPortWrite(pVM, pVCpu, 0x4d0, elcr[0], sizeof(uint8_t));
+    if (rcStrict == VINF_SUCCESS)
+        rcStrict = IOMIOPortWrite(pVM, pVCpu, 0x4d1, elcr[1], sizeof(uint8_t));
+    if (rcStrict != VINF_SUCCESS)
+    {
+        AssertMsgFailed(("Writing to PIC failed! rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
+        return RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR : VBOXSTRICTRC_VAL(rcStrict);
+    }
+
+    /*
+     * Init the devices.
+     */
+    for (i = 0; i < 256; i++)
+    {
+        uint8_t aBridgePositions[256];
+
+        memset(aBridgePositions, 0, sizeof(aBridgePositions));
+        Log2(("PCI: Initializing device %d (%#x)\n",
+              i, 0x80000000 | (i << 8)));
+        pci_bios_init_device(pGlobals, 0, i, 0, aBridgePositions);
+    }
+
+    return VINF_SUCCESS;
+}
+
 #endif /* IN_RING3 */
 
@@ -782 +847 @@
 PDMBOTHCBDECL(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
 {
-    Log(("pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
+    LogFunc(("Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
     RT_NOREF2(Port, pvUser);
     if (cb == 4)
@@ -809 +874 @@
         *pu32 = pThis->uConfigReg;
         PCI_UNLOCK(pDevIns);
-        Log(("pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
+        LogFunc(("Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
         return VINF_SUCCESS;
     }
     /* else: 440FX does "pass through to the bus" for other writes, what ever that means.
      * Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
-    Log(("pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
+    LogFunc(("Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
     return VERR_IOM_IOPORT_UNUSED;
 }
@@ -824 +889 @@
 PDMBOTHCBDECL(int) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
 {
-    Log(("pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
+    LogFunc(("Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
     NOREF(pvUser);
     int rc = VINF_SUCCESS;
@@ -850 +915 @@
         int rc = pci_data_read(PDMINS_2_DATA(pDevIns, PDEVPCIROOT), Port, cb, pu32);
         PCI_UNLOCK(pDevIns);
-        Log(("pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
+        LogFunc(("Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
         return rc;
     }
@@ -858 +923 @@
 
 #ifdef IN_RING3
+
+/**
+ * @callback_method_impl{FNIOMIOPORTOUT, PCI data}
+ */
+DECLCALLBACK(int) pciR3IOPortMagicPCIWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
+{
+    RT_NOREF2(pvUser, Port);
+    LogFunc(("Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
+    if (cb == 4)
+    {
+        if (u32 == UINT32_C(19200509)) // Richard Adams
+        {
+            int rc = pciR3FakePCIBIOS(pDevIns);
+            AssertRC(rc);
+        }
+    }
+
+    return VINF_SUCCESS;
+}
+
+/**
+ * @callback_method_impl{FNIOMIOPORTIN, PCI data}
+ */
+DECLCALLBACK(int) pciR3IOPortMagicPCIRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
+{
+    RT_NOREF5(pDevIns, pvUser, Port, pu32, cb);
+    LogFunc(("Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
+    return VERR_IOM_IOPORT_UNUSED;
+}
+
 
 /*
@@ -1077 +1172 @@
 {
     PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
-    PDEVPCIBUS     pBus  = &pThis->PciBus;
+    PDEVPCIBUS  pBus  = &pThis->PciBus;
     uint32_t    u32;
     int         rc;
@@ -1122 +1217 @@
 
 /* -=-=-=-=-=- PCI Bus Interface Methods (PDMPCIBUSREG) -=-=-=-=-=- */
-
-/**
- * @interface_method_impl{PDMPCIBUSREG,pfnFakePCIBIOSR3}
- */
-static DECLCALLBACK(int) pciR3FakePCIBIOS(PPDMDEVINS pDevIns)
-{
-    unsigned        i;
-    uint8_t         elcr[2]    = {0, 0};
-    PDEVPCIROOT     pGlobals   = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
-    PVM             pVM        = PDMDevHlpGetVM(pDevIns); Assert(pVM);
-    PVMCPU          pVCpu      = PDMDevHlpGetVMCPU(pDevIns); Assert(pVM);
-    uint32_t const  cbBelow4GB = MMR3PhysGetRamSizeBelow4GB(pVM);
-    uint64_t const  cbAbove4GB = MMR3PhysGetRamSizeAbove4GB(pVM);
-    RT_NOREF(cbBelow4GB, cbAbove4GB);
-
-    /*
-     * Set the start addresses.
-     */
-    pGlobals->uPciBiosBus  = 0;
-    pGlobals->uPciBiosIo   = 0xd000;
-    pGlobals->uPciBiosMmio = UINT32_C(0xf0000000);
-
-    /*
-     * Activate IRQ mappings.
-     */
-    for (i = 0; i < 4; i++)
-    {
-        uint8_t irq = pci_irqs[i];
-        /* Set to trigger level. */
-        elcr[irq >> 3] |= (1 << (irq & 7));
-        /* Activate irq remapping in PIIX3. */
-        pci_config_writeb(pGlobals, 0, pGlobals->Piix3.PIIX3State.dev.uDevFn, 0x60 + i, irq);
-    }
-
-    /* Tell to the PIC. */
-    VBOXSTRICTRC rcStrict = IOMIOPortWrite(pVM, pVCpu, 0x4d0, elcr[0], sizeof(uint8_t));
-    if (rcStrict == VINF_SUCCESS)
-        rcStrict = IOMIOPortWrite(pVM, pVCpu, 0x4d1, elcr[1], sizeof(uint8_t));
-    if (rcStrict != VINF_SUCCESS)
-    {
-        AssertMsgFailed(("Writing to PIC failed! rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
-        return RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR : VBOXSTRICTRC_VAL(rcStrict);
-    }
-
-    /*
-     * Init the devices.
-     */
-    for (i = 0; i < 256; i++)
-    {
-        uint8_t aBridgePositions[256];
-
-        memset(aBridgePositions, 0, sizeof(aBridgePositions));
-        Log2(("PCI: Initializing device %d (%#x)\n",
-              i, 0x80000000 | (i << 8)));
-        pci_bios_init_device(pGlobals, 0, i, 0, aBridgePositions);
-    }
-
-    return VINF_SUCCESS;
-}
 
 
@@ -1275 +1311 @@
 
     PDMPCIBUSREG PciBusReg;
-    PDEVPCIBUS      pBus = &pGlobals->PciBus;
+    PDEVPCIBUS   pBus = &pGlobals->PciBus;
     PciBusReg.u32Version              = PDM_PCIBUSREG_VERSION;
     PciBusReg.pfnRegisterR3           = pciR3MergedRegister;
@@ -1282 +1318 @@
     PciBusReg.pfnSetConfigCallbacksR3 = devpciR3CommonSetConfigCallbacks;
     PciBusReg.pfnSetIrqR3             = pciSetIrq;
-    PciBusReg.pfnFakePCIBIOSR3        = pciR3FakePCIBIOS;
     PciBusReg.pszSetIrqRC             = fGCEnabled ? "pciSetIrq" : NULL;
     PciBusReg.pszSetIrqR0             = fR0Enabled ? "pciSetIrq" : NULL;
@@ -1361 +1396 @@
             return rc;
     }
+
+    rc = PDMDevHlpIOPortRegister(pDevIns, 0x0410, 1, NULL, pciR3IOPortMagicPCIWrite, pciR3IOPortMagicPCIRead, NULL, NULL, "i440FX (Fake PCI BIOS trigger)")
+;
+    if (RT_FAILURE(rc))
+        return rc;
+
 
     rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(*pBus) + 16*128, "pgm",
@@ -1467 +1508 @@
      * of our parent passing the device which asserted the interrupt instead of the device of the bridge.
      */
-    PDEVPCIBUS    pBus          = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
+    PDEVPCIBUS pBus          = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
     PPDMPCIDEV pPciDevBus    = pPciDev;
     int        iIrqPinBridge = iIrq;
@@ -1514 +1555 @@
         if (pPciDev)
         {
-            Log(("%s: %s: addr=%02x val=%08x len=%d\n", __FUNCTION__, pPciDev->pszNameR3, u32Address, u32Value, cb));
+            LogFunc(("%s: addr=%02x val=%08x len=%d\n", pPciDev->pszNameR3, u32Address, u32Value, cb));
             pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, u32Value, cb);
         }
@@ -1548 +1589 @@
         {
             u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, cb);
-            Log(("%s: %s: u32Address=%02x u32Value=%08x cb=%d\n", __FUNCTION__, pPciDev->pszNameR3, u32Address, u32Value, cb));
+            LogFunc(("%s: u32Address=%02x u32Value=%08x cb=%d\n", pPciDev->pszNameR3, u32Address, u32Value, cb));
         }
     }
@@ -1641 +1682 @@
     PciBusReg.pfnSetConfigCallbacksR3 = devpciR3CommonSetConfigCallbacks;
     PciBusReg.pfnSetIrqR3             = pcibridgeSetIrq;
-    PciBusReg.pfnFakePCIBIOSR3        = NULL; /* Only needed for the first bus. */
     PciBusReg.pszSetIrqRC             = fGCEnabled ? "pcibridgeSetIrq" : NULL;
     PciBusReg.pszSetIrqR0             = fR0Enabled ? "pcibridgeSetIrq" : NULL;

trunk/src/VBox/Devices/Bus/DevPciIch9.cpp ¶

@@ -96 +96 @@
                                   int iIrq, int iLevel, uint32_t uTagSrc);
 #ifdef IN_RING3
+static int ich9pciFakePCIBIOS(PPDMDEVINS pDevIns);
 DECLINLINE(PPDMPCIDEV) ich9pciFindBridge(PDEVPCIBUS pBus, uint8_t uBus);
 static void ich9pciBiosInitAllDevicesOnBus(PDEVPCIROOT pPciRoot, uint8_t uBus);
@@ -155 +156 @@
 
 
+#ifdef IN_RING3
+
 /**
- * Port I/O Handler for PCI address OUT operations.
- *
- * Emulates writes to Configuration Address Port at 0CF8h for
- * Configuration Mechanism #1.
+ * Port I/O Handler for Fake PCI BIOS trigger OUT operations at 0410h
  *
  * @returns VBox status code.
@@ -169 +169 @@
  * @param   cb          The value size in bytes.
  */
+DECLCALLBACK(int) ich9pciR3IOPortMagicPCIWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
+{
+    RT_NOREF2(pvUser, uPort);
+    LogFlowFunc(("Port=%#x u32=%#x cb=%d\n", uPort, u32, cb));
+    if (cb == 4)
+    {
+        if (u32 == UINT32_C(19200509)) // Richard Adams
+        {
+            int rc = ich9pciFakePCIBIOS(pDevIns);
+            AssertRC(rc);
+        }
+    }
+
+    return VINF_SUCCESS;
+}
+
+
+/**
+ * Port I/O Handler for Fake PCI BIOS trigger IN operations at 0410h
+ *
+ * @returns VBox status code.
+ *
+ * @param   pDevIns     ICH9 device instance.
+ * @param   pvUser      User argument - ignored.
+ * @param   uPort       Port number used for the IN operation.
+ * @param   pu32        Where to store the result.
+ * @param   cb          Number of bytes read.
+ */
+DECLCALLBACK(int) ich9pciR3IOPortMagicPCIRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t *pu32, unsigned cb)
+{
+    RT_NOREF5(pDevIns, pvUser, uPort, pu32, cb);
+    LogFunc(("Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", uPort, cb));
+    return VERR_IOM_IOPORT_UNUSED;
+}
+
+#endif /* IN_RING3 */
+
+
+/**
+ * Port I/O Handler for PCI address OUT operations.
+ *
+ * Emulates writes to Configuration Address Port at 0CF8h for
+ * Configuration Mechanism #1.
+ *
+ * @returns VBox status code.
+ *
+ * @param   pDevIns     ICH9 device instance.
+ * @param   pvUser      User argument - ignored.
+ * @param   uPort       Port number used for the OUT operation.
+ * @param   u32         The value to output.
+ * @param   cb          The value size in bytes.
+ */
 PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
 {
-    LogFlow(("ich9pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", uPort, u32, cb));
+    LogFlowFunc(("Port=%#x u32=%#x cb=%d\n", uPort, u32, cb));
     RT_NOREF2(uPort, pvUser);
     if (cb == 4)
@@ -217 +269 @@
         PCI_UNLOCK(pDevIns);
 
-        LogFlow(("ich9pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", uPort, cb, *pu32));
+        LogFlowFunc(("Port=%#x cb=%d -> %#x\n", uPort, cb, *pu32));
         return VINF_SUCCESS;
     }
 
-    Log(("ich9pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", uPort, cb));
+    LogFunc(("Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", uPort, cb));
     return VERR_IOM_IOPORT_UNUSED;
 }
@@ -269 +321 @@
     }
 
-    Log2(("ich9pciDataWriteAddr: %02x:%02x.%d reg %x(%d) %x %Rrc\n",
-          pAddr->iBus, pAddr->iDeviceFunc >> 3, pAddr->iDeviceFunc & 0x7, pAddr->iRegister,
-          cb, val, rc));
+    Log2Func(("%02x:%02x.%d reg %x(%d) %x %Rrc\n",
+              pAddr->iBus, pAddr->iDeviceFunc >> 3, pAddr->iDeviceFunc & 0x7, pAddr->iRegister, cb, val, rc));
     return rc;
 }
@@ -286 +337 @@
 static int ich9pciDataWrite(PDEVPCIROOT pPciRoot, uint32_t addr, uint32_t val, int len)
 {
-    LogFlow(("ich9pciDataWrite: config=%08x val=%08x len=%d\n", pPciRoot->uConfigReg, val, len));
+    LogFlowFunc(("config=%08x val=%08x len=%d\n", pPciRoot->uConfigReg, val, len));
 
     /* Configuration space mapping enabled? */
@@ -317 +368 @@
 PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
 {
-    LogFlow(("ich9pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", uPort, u32, cb));
+    LogFlowFunc(("Port=%#x u32=%#x cb=%d\n", uPort, u32, cb));
     NOREF(pvUser);
     int rc = VINF_SUCCESS;
@@ -388 +439 @@
     }
 
-    Log3(("ich9pciDataReadAddr: %02x:%02x.%d reg %x(%d) gave %x %Rrc\n",
-          pPciAddr->iBus, pPciAddr->iDeviceFunc >> 3, pPciAddr->iDeviceFunc & 0x7, pPciAddr->iRegister,
-          cb, *pu32, rc));
+    Log3Func(("%02x:%02x.%d reg %x(%d) gave %x %Rrc\n",
+              pPciAddr->iBus, pPciAddr->iDeviceFunc >> 3, pPciAddr->iDeviceFunc & 0x7, pPciAddr->iRegister, cb, *pu32, rc));
     return rc;
 }
@@ -405 +455 @@
 static int ich9pciDataRead(PDEVPCIROOT pPciRoot, uint32_t addr, int cb, uint32_t *pu32)
 {
-    LogFlow(("ich9pciDataRead: config=%x cb=%d\n",  pPciRoot->uConfigReg, cb));
+    LogFlowFunc(("config=%x cb=%d\n",  pPciRoot->uConfigReg, cb));
 
     *pu32 = 0xffffffff;
@@ -447 +497 @@
         PCI_UNLOCK(pDevIns);
 
-        LogFlow(("ich9pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", uPort, cb, *pu32, rc));
+        LogFlowFunc(("Port=%#x cb=%#x -> %#x (%Rrc)\n", uPort, cb, *pu32, rc));
         return rc;
     }
@@ -510 +560 @@
         apic_irq = irq_num + 0x10;
         apic_level = pPciRoot->auPciApicIrqLevels[irq_num] != 0;
-        Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d uTagSrc=%#x\n",
-              R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num, uTagSrc));
+        Log3Func(("%s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d uTagSrc=%#x\n",
+                  R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num, uTagSrc));
         pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
 
@@ -523 +573 @@
             pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
             apic_level = pPciRoot->auPciApicIrqLevels[irq_num] != 0;
-            Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d uTagSrc=%#x (flop)\n",
-                  R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num, uTagSrc));
+            Log3Func(("%s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d uTagSrc=%#x (flop)\n",
+                      R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num, uTagSrc));
             pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
         }
     } else {
-        Log3(("ich9pciApicSetIrq: (forced) %s: irq_num1=%d level=%d acpi_irq=%d uTagSrc=%#x\n",
-              R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, iForcedIrq, uTagSrc));
+        Log3Func(("(forced) %s: irq_num1=%d level=%d acpi_irq=%d uTagSrc=%#x\n",
+                  R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, iForcedIrq, uTagSrc));
         pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), iForcedIrq, iLevel, uTagSrc);
     }
@@ -608 +658 @@
     NOREF(pvUser);
 
-    Log2(("ich9pciMcfgMMIOWrite: %RGp(%d) \n", GCPhysAddr, cb));
+    Log2Func(("%RGp(%d) \n", GCPhysAddr, cb));
 
     PCI_LOCK(pDevIns, VINF_IOM_R3_MMIO_WRITE);
@@ -660 +710 @@
     NOREF(pvUser);
 
-    LogFlow(("ich9pciMcfgMMIORead: %RGp(%d) \n", GCPhysAddr, cb));
+    LogFlowFunc(("%RGp(%d) \n", GCPhysAddr, cb));
 
     PCI_LOCK(pDevIns, VINF_IOM_R3_MMIO_READ);
@@ -722 +772 @@
         /* safe, only needs to go to the config space array */
         uint32_t uSubordinate = PDMPciDevGetByte(pBridge, VBOX_PCI_SUBORDINATE_BUS);
-        Log3(("ich9pciFindBridge on bus %p, bridge %d: %d in %d..%d\n", pBus, iBridge, uBus, uSecondary, uSubordinate));
+        Log3Func(("bus %p, bridge %d: %d in %d..%d\n", pBus, iBridge, uBus, uSecondary, uSubordinate));
         if (uBus >= uSecondary && uBus <= uSubordinate)
             return pBridge;
@@ -828 +878 @@
                     VERR_INVALID_PARAMETER);
 
-    Log(("devpciR3CommonIORegionRegister: %s region %d size %RGp type %x\n",
-         pPciDev->pszNameR3, iRegion, cbRegion, enmType));
+    LogFunc(("%s region %d size %RGp type %x\n", pPciDev->pszNameR3, iRegion, cbRegion, enmType));
 
     /* Make sure that we haven't marked this region as continuation of 64-bit region. */
@@ -979 +1028 @@
     PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
 
-    LogFlowFunc((": pDevIns=%p uBus=%d uDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, uBus, uDevice, u32Address, u32Value, cb));
+    LogFlowFunc(("pDevIns=%p uBus=%d uDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, uBus, uDevice, u32Address, u32Value, cb));
 
     /* If the current bus is not the target bus search for the bus which contains the device. */
@@ -999 +1048 @@
         if (pPciDev)
         {
-            Log(("%s: %s: addr=%02x val=%08x len=%d\n", __FUNCTION__, pPciDev->pszNameR3, u32Address, u32Value, cb));
+            LogFunc(("%s: addr=%02x val=%08x len=%d\n", pPciDev->pszNameR3, u32Address, u32Value, cb));
             pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, u32Value, cb);
         }
@@ -1010 +1059 @@
     uint32_t u32Value;
 
-    LogFlowFunc((": pDevIns=%p uBus=%d uDevice=%d u32Address=%u cb=%d\n", pDevIns, uBus, uDevice, u32Address, cb));
+    LogFlowFunc(("pDevIns=%p uBus=%d uDevice=%d u32Address=%u cb=%d\n", pDevIns, uBus, uDevice, u32Address, cb));
 
     /* If the current bus is not the target bus search for the bus which contains the device. */
@@ -1033 +1082 @@
         {
             u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, cb);
-            Log(("%s: %s: u32Address=%02x u32Value=%08x cb=%d\n", __FUNCTION__, pPciDev->pszNameR3, u32Address, u32Value, cb));
+            LogFunc(("%s: u32Address=%02x u32Value=%08x cb=%d\n", pPciDev->pszNameR3, u32Address, u32Value, cb));
         }
         else
@@ -1569 +1618 @@
     {
         pPciRoot->uPciBiosIo = RT_ALIGN_32(pPciRoot->uPciBiosIo, _4K);
-        Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pPciRoot->uPciBiosIo));
+        LogFunc(("Aligned I/O start address. New address %#x\n", pPciRoot->uPciBiosIo));
     }
     ich9pciBiosInitWriteConfig(pPciRoot, uBus, uDevFn, VBOX_PCI_IO_BASE, (pPciRoot->uPciBiosIo >> 8) & 0xf0, 1);
@@ -1577 +1626 @@
     {
         pPciRoot->uPciBiosMmio = RT_ALIGN_32(pPciRoot->uPciBiosMmio, _1M);
-        Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pPciRoot->uPciBiosMmio));
+        LogFunc(("Aligned MMIO start address. New address %#x\n", pPciRoot->uPciBiosMmio));
     }
     ich9pciBiosInitWriteConfig(pPciRoot, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pPciRoot->uPciBiosMmio >> 16) & UINT32_C(0xffff0), 2);
@@ -1717 +1766 @@
             cbRegSize64 = cbRegSize32;
         }
-        Log2(("%s: Size of region %u for device %d on bus %d is %lld\n", __FUNCTION__, iRegion, uDevFn, uBus, cbRegSize64));
+        Log2Func(("%s: Size of region %u for device %d on bus %d is %lld\n", iRegion, uDevFn, uBus, cbRegSize64));
 
         if (cbRegSize64)
@@ -1822 +1871 @@
             cbRegSize64 = cbRegSize32;
         }
-        Log2(("%s: Size of region %u for device %d on bus %d is %lld\n", __FUNCTION__, iRegion, uDevFn, uBus, cbRegSize64));
+        Log2Func(("%s: Size of region %u for device %d on bus %d is %lld\n", iRegion, uDevFn, uBus, cbRegSize64));
 
         if (cbRegSize64)
@@ -2185 +2234 @@
 
     /* safe, only needs to go to the config space array */
-    Log2(("ich9pciBiosInitBridgeTopology: for bus %p: primary=%d secondary=%d subordinate=%d\n",
+    Log2Func(("for bus %p: primary=%d secondary=%d subordinate=%d\n",
           pBus,
           PDMPciDevGetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS),
@@ -2197 +2246 @@
 
 /**
- * @interface_method_impl{PDMPCIBUSREG,pfnFakePCIBIOSR3}
- */
-static DECLCALLBACK(int) ich9pciFakePCIBIOS(PPDMDEVINS pDevIns)
+ * Worker for Fake PCI BIOS config
+ *
+ * @returns VBox status code.
+ *
+ * @param   pDevIns     ICH9 device instance.
+ */
+static int ich9pciFakePCIBIOS(PPDMDEVINS pDevIns)
 {
     PDEVPCIROOT     pPciRoot   = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
@@ -2205 +2258 @@
     uint32_t const  cbBelow4GB = MMR3PhysGetRamSizeBelow4GB(pVM);
     uint64_t const  cbAbove4GB = MMR3PhysGetRamSizeAbove4GB(pVM);
+
+    LogRel(("PCI: setting up topology, resources and interrupts\n"));
 
     /** @todo r=klaus this needs to do the same elcr magic as DevPCI.cpp, as the BIOS can't be trusted to do the right thing. Of course it's more difficult than with the old code, as there are bridges to be handled. The interrupt routing needs to be taken into account. Also I highly suspect that the chipset has 8 interrupt lines which we might be able to use for handling things on the root bus better (by treating them as devices on the mainboard). */
@@ -2278 +2333 @@
         if (   pciDevIsMsiCapable(pPciDev)
             && uAddress - (uint32_t)pPciDev->Int.s.u8MsiCapOffset < (uint32_t)pPciDev->Int.s.u8MsiCapSize )
-            Log2(("devpciR3CommonDefaultConfigRead: MSI CAP: %#x LB %u -> %#x\n", uAddress - (uint32_t)pPciDev->Int.s.u8MsiCapOffset, cb, uValue));
+            Log2Func(("MSI CAP: %#x LB %u -> %#x\n", uAddress - (uint32_t)pPciDev->Int.s.u8MsiCapOffset, cb, uValue));
         else if (   pciDevIsMsixCapable(pPciDev)
                  && uAddress - (uint32_t)pPciDev->Int.s.u8MsixCapOffset < (uint32_t)pPciDev->Int.s.u8MsixCapSize)
-            Log2(("devpciR3CommonDefaultConfigRead: MSI-X CAP: %#x LB %u -> %#x\n", uAddress - (uint32_t)pPciDev->Int.s.u8MsiCapOffset, cb, uValue));
+            Log2Func(("MSI-X CAP: %#x LB %u -> %#x\n", uAddress - (uint32_t)pPciDev->Int.s.u8MsiCapOffset, cb, uValue));
 #endif
     }
@@ -2456 +2511 @@
 {
     PCIIORegion *pRegion = &pPciDev->Int.s.aIORegions[iRegion];
-    Log3(("devpciR3WriteBarByte: region=%d off=%d val=%#x size=%#llx\n", iRegion, off, bVal, pRegion->size));
+    Log3Func(("region=%d off=%d val=%#x size=%#llx\n", iRegion, off, bVal, pRegion->size));
     Assert(off <= 3);
 
@@ -2484 +2539 @@
         bVal = (bOld & bMask) | (bVal & ~bMask);
 
-        Log3(("devpciR3WriteBarByte: %x changed to  %x\n", bOld, bVal));
+        Log3Func(("%x changed to  %x\n", bOld, bVal));
 
         /* safe, only needs to go to the config space array */
@@ -3041 +3096 @@
     PciBusReg.pfnSetConfigCallbacksR3 = devpciR3CommonSetConfigCallbacks;
     PciBusReg.pfnSetIrqR3             = ich9pciSetIrq;
-    PciBusReg.pfnFakePCIBIOSR3        = ich9pciFakePCIBIOS;
     PciBusReg.pszSetIrqRC             = fGCEnabled ? "ich9pciSetIrq" : NULL;
     PciBusReg.pszSetIrqR0             = fR0Enabled ? "ich9pciSetIrq" : NULL;
@@ -3114 +3168 @@
     }
 
+    rc = PDMDevHlpIOPortRegister(pDevIns, 0x0410, 1, NULL, ich9pciR3IOPortMagicPCIWrite, ich9pciR3IOPortMagicPCIRead, NULL, NULL, "ICH9 (Fake PCI BIOS trigger)");
+    if (RT_FAILURE(rc))
+        return rc;
+
     if (pPciRoot->u64PciConfigMMioAddress != 0)
     {
@@ -3267 +3325 @@
 static DECLCALLBACK(void) ich9pciReset(PPDMDEVINS pDevIns)
 {
+    PDEVPCIROOT pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
+
     /* Reset everything under the root bridge. */
     ich9pciResetBridge(pDevIns);
@@ -3373 +3433 @@
     pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
     /** @todo r=klaus figure out how to extend this to allow PCIe config space
-     * extension, which increases the config space frorm 256 bytes to 4K. */
+     * extension, which increases the config space from 256 bytes to 4K. */
     pBus->papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) * RT_ELEMENTS(pBus->apDevices));
     AssertLogRelReturn(pBus->papBridgesR3, VERR_NO_MEMORY);
@@ -3384 +3444 @@
     PciBusReg.pfnSetConfigCallbacksR3 = devpciR3CommonSetConfigCallbacks;
     PciBusReg.pfnSetIrqR3             = ich9pcibridgeSetIrq;
-    PciBusReg.pfnFakePCIBIOSR3        = NULL; /* Only needed for the first bus. */
     PciBusReg.pszSetIrqRC             = fGCEnabled ? "ich9pcibridgeSetIrq" : NULL;
     PciBusReg.pszSetIrqR0             = fR0Enabled ? "ich9pcibridgeSetIrq" : NULL;

trunk/src/VBox/Devices/PC/BIOS/pcibios.inc ¶

@@ -96 +96 @@
                 push    bp
                 mov     bp, sp
+ifdef VBOX
+                mov     eax,19200509 
+                mov     dx,410h
+                out     dx,  eax
+else
+; This incomplete PCI resource setup code is less functional than the PCI
+; resource assignment created by the fake PCI BIOS and is therefore disabled.
+; Blindly enabling everything on the root bus (including bus mastering!) can
+; only be called buggy. It causes the trouble with AMD PCNet which it then
+; tries to work around, but that still contains a race.
                 mov     eax, 0E0000000h ; base for memory init
                 push    eax
@@ -111 +121 @@
                 jz      next_pci_dev
 
-ifndef VBOX ; This currently breaks restoring a previously saved state. */
+ifndef VBOX ; This currently breaks restoring a previously saved state.
                 mov     dl, 4   ; disable i/o and memory space access
                 call    pcibios_init_sel_reg
@@ -201 +211 @@
                 cmp     bx, 0100h
                 jne     pci_init_io_loop1
+endif ; !VBOX
                 mov     sp, bp
                 pop     bp
@@ -230 +241 @@
                 mov     ax, 0F000h
                 mov     ds, ax
+ifndef VBOX
+; this code works OK, but it's unnecessary effort since the fake PCI BIOS
+; already configured the IRQ lines and the ELCR correctly
                 mov     dx, 04D0h ;; reset ELCR1 + ELCR2
                 mov     al, 0
@@ -282 +296 @@
                 mov     dl, 3Ch
                 call pcibios_init_sel_reg
-                mov     dx, PCI_CFG2 + 1 ; TODO: was #0x0cfd - is that right?
+                mov     dx, PCI_CFG2 + 1 ; access config space at 3Dh
                 in      al, dx
                 and     al, 7
@@ -332 +346 @@
                 pop     bx
 pci_init_end:
+endif
                 pop             bp
                 pop             ds

trunk/src/VBox/VMM/VMMR3/PDM.cpp ¶

@@ -1645 +1645 @@
         }
 
-    /*
-     * Run Fake PCI BIOS after reset.
-     */
-    if (fAtReset && pVM->pdm.s.aPciBuses[0].pDevInsR3)
-    {
-        pdmLock(pVM);
-        int rc = pVM->pdm.s.aPciBuses[0].pfnFakePCIBIOSR3(pVM->pdm.s.aPciBuses[0].pDevInsR3);
-        pdmUnlock(pVM);
-        if (RT_FAILURE(rc))
-            AssertMsgFailed(("PCI BIOS fake failed rc=%Rrc\n", rc));
-    }
-
-
     LogFlow(("PDMR3MemSetup: returns void\n"));
 }

trunk/src/VBox/VMM/VMMR3/PDMDevHlp.cpp ¶

@@ -2613 +2613 @@
 #if PDM_DEVHLPR3_VERSION >= PDM_VERSION_MAKE_PP(0xffe7, 20, 0)
     LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: pPciBusReg=%p:{.u32Version=%#x, .pfnRegisterR3=%p, .pfnIORegionRegisterR3=%p, "
-             ".pfnSetIrqR3=%p, .pfnFakePCIBIOSR3=%p, .pszSetIrqRC=%p:{%s}, .pszSetIrqR0=%p:{%s}} ppPciHlpR3=%p piBus=%p\n",
+             ".pfnSetIrqR3=%p, .pszSetIrqRC=%p:{%s}, .pszSetIrqR0=%p:{%s}} ppPciHlpR3=%p piBus=%p\n",
              pDevIns->pReg->szName, pDevIns->iInstance, pPciBusReg, pPciBusReg->u32Version, pPciBusReg->pfnRegisterR3,
-             pPciBusReg->pfnIORegionRegisterR3, pPciBusReg->pfnSetIrqR3, pPciBusReg->pfnFakePCIBIOSR3,
-             pPciBusReg->pszSetIrqRC, pPciBusReg->pszSetIrqRC, pPciBusReg->pszSetIrqR0, pPciBusReg->pszSetIrqR0,
-             ppPciHlpR3, piBus));
+             pPciBusReg->pfnIORegionRegisterR3, pPciBusReg->pfnSetIrqR3, pPciBusReg->pszSetIrqRC, pPciBusReg->pszSetIrqRC,
+             pPciBusReg->pszSetIrqR0, pPciBusReg->pszSetIrqR0, ppPciHlpR3, piBus));
 #else
     LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: pPciBusReg=%p:{.u32Version=%#x, .pfnRegisterR3=%p, .pfnIORegionRegisterR3=%p, "
-             ".pfnSetIrqR3=%p, .pfnFakePCIBIOSR3=%p, .pszSetIrqRC=%p:{%s}, .pszSetIrqR0=%p:{%s}} ppPciHlpR3=%p\n",
+             ".pfnSetIrqR3=%p, .pszSetIrqRC=%p:{%s}, .pszSetIrqR0=%p:{%s}} ppPciHlpR3=%p\n",
              pDevIns->pReg->szName, pDevIns->iInstance, pPciBusReg, pPciBusReg->u32Version, pPciBusReg->pfnRegisterR3,
-             pPciBusReg->pfnIORegionRegisterR3, pPciBusReg->pfnSetIrqR3, pPciBusReg->pfnFakePCIBIOSR3,
-             pPciBusReg->pszSetIrqRC, pPciBusReg->pszSetIrqRC, pPciBusReg->pszSetIrqR0, pPciBusReg->pszSetIrqR0, ppPciHlpR3));
+             pPciBusReg->pfnIORegionRegisterR3, pPciBusReg->pfnSetIrqR3, pPciBusReg->pszSetIrqRC, pPciBusReg->pszSetIrqRC,
+             pPciBusReg->pszSetIrqR0, pPciBusReg->pszSetIrqR0, ppPciHlpR3));
 #endif
 
@@ -2637 +2636 @@
     if (    !pPciBusReg->pfnRegisterR3
         ||  !pPciBusReg->pfnIORegionRegisterR3
-        ||  !pPciBusReg->pfnSetIrqR3
-        ||  (!pPciBusReg->pfnFakePCIBIOSR3 && !pVM->pdm.s.aPciBuses[0].pDevInsR3)) /* Only the first bus needs to do the BIOS work. */
+        ||  !pPciBusReg->pfnSetIrqR3)
     {
         Assert(pPciBusReg->pfnRegisterR3);
         Assert(pPciBusReg->pfnIORegionRegisterR3);
         Assert(pPciBusReg->pfnSetIrqR3);
-        Assert(pPciBusReg->pfnFakePCIBIOSR3);
         LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc (R3 callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
         return VERR_INVALID_PARAMETER;
@@ -2738 +2735 @@
     pPciBus->pfnSetConfigCallbacksR3 = pPciBusReg->pfnSetConfigCallbacksR3;
     pPciBus->pfnSetIrqR3             = pPciBusReg->pfnSetIrqR3;
-    pPciBus->pfnFakePCIBIOSR3        = pPciBusReg->pfnFakePCIBIOSR3;
 
     Log(("PDM: Registered PCI bus device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));

trunk/src/VBox/VMM/VMMR3/PDMDevice.cpp ¶

@@ -424 +424 @@
 
     /*
-     *
-     * PCI BIOS Fake and Init Complete.
-     *
-     */
-    if (pVM->pdm.s.aPciBuses[0].pDevInsR3)
-    {
-        pdmLock(pVM);
-        rc = pVM->pdm.s.aPciBuses[0].pfnFakePCIBIOSR3(pVM->pdm.s.aPciBuses[0].pDevInsR3);
-        pdmUnlock(pVM);
-        if (RT_FAILURE(rc))
-        {
-            AssertMsgFailed(("PCI BIOS fake failed rc=%Rrc\n", rc));
-            return rc;
-        }
-    }
-
+     * Iterate thru the device instances and work the callback.
+     */
     for (PPDMDEVINS pDevIns = pVM->pdm.s.pDevInstances; pDevIns; pDevIns = pDevIns->Internal.s.pNextR3)
     {

trunk/src/VBox/VMM/include/PDMInternal.h ¶

@@ -641 +641 @@
     DECLR3CALLBACKMEMBER(void,      pfnSetConfigCallbacksR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PFNPCICONFIGREAD pfnRead,
                                                              PPFNPCICONFIGREAD ppfnReadOld, PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld));
-    /** @copydoc PDMPCIBUSREG::pfnFakePCIBIOSR3 */
-    DECLR3CALLBACKMEMBER(int,       pfnFakePCIBIOSR3,(PPDMDEVINS pDevIns));
 
     /** Pointer to the PIC device instance - R0. */