Changeset 67902 in vbox
- Timestamp:
- Jul 11, 2017 11:40:02 AM (8 years ago)
- svn:sync-xref-src-repo-rev:
- 116887
- File:
-
- 1 edited
-
trunk/src/VBox/Devices/Audio/DevHDACommon.h (modified) (16 diffs)
Legend:
- Unmodified
- Added
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trunk/src/VBox/Devices/Audio/DevHDACommon.h
r67901 r67902 78 78 #define HDA_MAX_TAGS 16 79 79 80 /* 81 * ICH6 datasheet defines limits for FIFOS registers (18.2.39) 82 * formula: size - 180 /** 81 * ICH6 datasheet defines limits for FIFOS registers (18.2.39). 82 * Formula: size - 1 83 83 * Other values not listed are not supported. 84 84 */ … … 131 131 132 132 133 #define HDA_REG_GCAP 0 /* range 0x00-0x01*/133 #define HDA_REG_GCAP 0 /* Range 0x00 - 0x01 */ 134 134 #define HDA_RMX_GCAP 0 135 /* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner: 136 * oss (15:12) - number of output streams supported 137 * iss (11:8) - number of input streams supported 138 * bss (7:3) - number of bidirectional streams supported 139 * bds (2:1) - number of serial data out (SDO) signals supported 135 /** 136 * GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner: 137 * 138 * oss (15:12) - Number of output streams supported. 139 * iss (11:8) - Number of input streams supported. 140 * bss (7:3) - Number of bidirectional streams supported. 141 * bds (2:1) - Number of serial data out (SDO) signals supported. 140 142 * b64sup (0) - 64 bit addressing supported. 141 143 */ … … 147 149 | ((b64sup) & 1)) 148 150 149 #define HDA_REG_VMIN 1 /* 0x02 */151 #define HDA_REG_VMIN 1 /* 0x02 */ 150 152 #define HDA_RMX_VMIN 1 151 153 152 #define HDA_REG_VMAJ 2 /* 0x03 */154 #define HDA_REG_VMAJ 2 /* 0x03 */ 153 155 #define HDA_RMX_VMAJ 2 154 156 155 #define HDA_REG_OUTPAY 3 /* 0x04-0x05 */157 #define HDA_REG_OUTPAY 3 /* 0x04-0x05 */ 156 158 #define HDA_RMX_OUTPAY 3 157 159 158 #define HDA_REG_INPAY 4 /* 0x06-0x07 */160 #define HDA_REG_INPAY 4 /* 0x06-0x07 */ 159 161 #define HDA_RMX_INPAY 4 160 162 161 #define HDA_REG_GCTL 5 /* 0x08-0x0B */163 #define HDA_REG_GCTL 5 /* 0x08-0x0B */ 162 164 #define HDA_RMX_GCTL 5 163 165 #define HDA_GCTL_UNSOL RT_BIT(8) /* Accept Unsolicited Response Enable */ … … 165 167 #define HDA_GCTL_CRST RT_BIT(0) /* Controller Reset */ 166 168 167 #define HDA_REG_WAKEEN 6 /* 0x0C */169 #define HDA_REG_WAKEEN 6 /* 0x0C */ 168 170 #define HDA_RMX_WAKEEN 6 169 171 170 #define HDA_REG_STATESTS 7 /* 0x0E */172 #define HDA_REG_STATESTS 7 /* 0x0E */ 171 173 #define HDA_RMX_STATESTS 7 172 #define HDA_STATESTS_SCSF_MASK 0x7 /* State Change Status Flags (6.2.8). */173 174 #define HDA_REG_GSTS 8 /* 0x10-0x11*/174 #define HDA_STATESTS_SCSF_MASK 0x7 /* State Change Status Flags (6.2.8). */ 175 176 #define HDA_REG_GSTS 8 /* 0x10-0x11*/ 175 177 #define HDA_RMX_GSTS 8 176 178 #define HDA_GSTS_FSTS RT_BIT(1) /* Flush Status */ 177 179 178 #define HDA_REG_OUTSTRMPAY 9 /* 0x18 */180 #define HDA_REG_OUTSTRMPAY 9 /* 0x18 */ 179 181 #define HDA_RMX_OUTSTRMPAY 112 180 182 181 #define HDA_REG_INSTRMPAY 10 /* 0x1a */183 #define HDA_REG_INSTRMPAY 10 /* 0x1a */ 182 184 #define HDA_RMX_INSTRMPAY 113 183 185 184 #define HDA_REG_INTCTL 11 /* 0x20 */186 #define HDA_REG_INTCTL 11 /* 0x20 */ 185 187 #define HDA_RMX_INTCTL 9 186 188 #define HDA_INTCTL_GIE RT_BIT(31) /* Global Interrupt Enable */ 187 189 #define HDA_INTCTL_CIE RT_BIT(30) /* Controller Interrupt Enable */ 188 /* Bits 0-29 correspond to streams 0-29. */190 /** Bits 0-29 correspond to streams 0-29. */ 189 191 #define HDA_STRMINT_MASK 0xFF /* Streams 0-7 implemented. Applies to INTCTL and INTSTS. */ 190 192 191 #define HDA_REG_INTSTS 12 /* 0x24 */193 #define HDA_REG_INTSTS 12 /* 0x24 */ 192 194 #define HDA_RMX_INTSTS 10 193 195 #define HDA_INTSTS_GIS RT_BIT(31) /* Global Interrupt Status */ 194 196 #define HDA_INTSTS_CIS RT_BIT(30) /* Controller Interrupt Status */ 195 /* Bits 0-29 correspond to streams 0-29. */ 196 197 #define HDA_REG_WALCLK 13 /* 0x30*/198 /* NB: HDA_RMX_WALCLK is not defined because the register is not stored in memory. */ 199 200 /* Note: The HDA specification defines a SSYNC register at offset 0x38. The197 198 #define HDA_REG_WALCLK 13 /* 0x30 */ 199 /**NB: HDA_RMX_WALCLK is not defined because the register is not stored in memory. */ 200 201 /** 202 * Note: The HDA specification defines a SSYNC register at offset 0x38. The 201 203 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches 202 204 * the datasheet. 203 205 */ 204 #define HDA_REG_SSYNC 14 /* 0x34 */206 #define HDA_REG_SSYNC 14 /* 0x34 */ 205 207 #define HDA_RMX_SSYNC 12 206 208 207 #define HDA_REG_CORBLBASE 15 /* 0x40 */209 #define HDA_REG_CORBLBASE 15 /* 0x40 */ 208 210 #define HDA_RMX_CORBLBASE 13 209 211 210 #define HDA_REG_CORBUBASE 16 /* 0x44 */212 #define HDA_REG_CORBUBASE 16 /* 0x44 */ 211 213 #define HDA_RMX_CORBUBASE 14 212 214 213 #define HDA_REG_CORBWP 17 /* 0x48 */215 #define HDA_REG_CORBWP 17 /* 0x48 */ 214 216 #define HDA_RMX_CORBWP 15 215 217 216 #define HDA_REG_CORBRP 18 /* 0x4A */218 #define HDA_REG_CORBRP 18 /* 0x4A */ 217 219 #define HDA_RMX_CORBRP 16 218 220 #define HDA_CORBRP_RST RT_BIT(15) /* CORB Read Pointer Reset */ 219 221 220 #define HDA_REG_CORBCTL 19 /* 0x4C */222 #define HDA_REG_CORBCTL 19 /* 0x4C */ 221 223 #define HDA_RMX_CORBCTL 17 222 224 #define HDA_CORBCTL_DMA RT_BIT(1) /* Enable CORB DMA Engine */ 223 225 #define HDA_CORBCTL_CMEIE RT_BIT(0) /* CORB Memory Error Interrupt Enable */ 224 226 225 #define HDA_REG_CORBSTS 20 /* 0x4D */227 #define HDA_REG_CORBSTS 20 /* 0x4D */ 226 228 #define HDA_RMX_CORBSTS 18 227 229 228 #define HDA_REG_CORBSIZE 21 /* 0x4E */230 #define HDA_REG_CORBSIZE 21 /* 0x4E */ 229 231 #define HDA_RMX_CORBSIZE 19 230 /* NB: Up to and including ICH 10, sizes of CORB and RIRB are fixed at 256 entries. */231 232 #define HDA_REG_RIRBLBASE 22 /* 0x50 */232 /** NB: Up to and including ICH 10, sizes of CORB and RIRB are fixed at 256 entries. */ 233 234 #define HDA_REG_RIRBLBASE 22 /* 0x50 */ 233 235 #define HDA_RMX_RIRBLBASE 20 234 236 235 #define HDA_REG_RIRBUBASE 23 /* 0x54 */237 #define HDA_REG_RIRBUBASE 23 /* 0x54 */ 236 238 #define HDA_RMX_RIRBUBASE 21 237 239 238 #define HDA_REG_RIRBWP 24 /* 0x58 */240 #define HDA_REG_RIRBWP 24 /* 0x58 */ 239 241 #define HDA_RMX_RIRBWP 22 240 242 #define HDA_RIRBWP_RST RT_BIT(15) /* RIRB Write Pointer Reset */ 241 243 242 #define HDA_REG_RINTCNT 25 /* 0x5A */244 #define HDA_REG_RINTCNT 25 /* 0x5A */ 243 245 #define HDA_RMX_RINTCNT 23 244 246 #define RINTCNT_N(pThis) (HDA_REG(pThis, RINTCNT) & 0xff) 245 247 246 #define HDA_REG_RIRBCTL 26 /* 0x5C */248 #define HDA_REG_RIRBCTL 26 /* 0x5C */ 247 249 #define HDA_RMX_RIRBCTL 24 248 250 #define HDA_RIRBCTL_ROIC RT_BIT(2) /* Response Overrun Interrupt Control */ … … 250 252 #define HDA_RIRBCTL_RINTCTL RT_BIT(0) /* Response Interrupt Control */ 251 253 252 #define HDA_REG_RIRBSTS 27 /* 0x5D */254 #define HDA_REG_RIRBSTS 27 /* 0x5D */ 253 255 #define HDA_RMX_RIRBSTS 25 254 256 #define HDA_RIRBSTS_RIRBOIS RT_BIT(2) /* Response Overrun Interrupt Status */ 255 257 #define HDA_RIRBSTS_RINTFL RT_BIT(0) /* Response Interrupt Flag */ 256 258 257 #define HDA_REG_RIRBSIZE 28 /* 0x5E */259 #define HDA_REG_RIRBSIZE 28 /* 0x5E */ 258 260 #define HDA_RMX_RIRBSIZE 26 259 261 260 #define HDA_REG_IC 29 /* 0x60 */262 #define HDA_REG_IC 29 /* 0x60 */ 261 263 #define HDA_RMX_IC 27 262 264 263 #define HDA_REG_IR 30 /* 0x64 */265 #define HDA_REG_IR 30 /* 0x64 */ 264 266 #define HDA_RMX_IR 28 265 267 266 #define HDA_REG_IRS 31 /* 0x68 */268 #define HDA_REG_IRS 31 /* 0x68 */ 267 269 #define HDA_RMX_IRS 29 268 270 #define HDA_IRS_IRV RT_BIT(1) /* Immediate Result Valid */ 269 271 #define HDA_IRS_ICB RT_BIT(0) /* Immediate Command Busy */ 270 272 271 #define HDA_REG_DPLBASE 32 /* 0x70 */273 #define HDA_REG_DPLBASE 32 /* 0x70 */ 272 274 #define HDA_RMX_DPLBASE 30 273 275 274 #define HDA_REG_DPUBASE 33 /* 0x74 */276 #define HDA_REG_DPUBASE 33 /* 0x74 */ 275 277 #define HDA_RMX_DPUBASE 31 276 278 … … 279 281 #define HDA_STREAM_REG_DEF(name, num) (HDA_REG_SD##num##name) 280 282 #define HDA_STREAM_RMX_DEF(name, num) (HDA_RMX_SD##num##name) 281 /* Note: sdnum here _MUST_ be stream reg number [0,7]. */283 /** Note: sdnum here _MUST_ be stream reg number [0,7]. */ 282 284 #define HDA_STREAM_REG(pThis, name, sdnum) (HDA_REG_IND((pThis), HDA_REG_SD0##name + (sdnum) * 10)) 283 285 … … 308 310 #define HDA_SDCTL_SRST RT_BIT(0) /* Stream Reset */ 309 311 310 #define HDA_REG_SD0STS 35 /* 0x83; other streams offset by 0x20 */312 #define HDA_REG_SD0STS 35 /* 0x83; other streams offset by 0x20 */ 311 313 #define HDA_RMX_SD0STS 33 312 314 #define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10) … … 323 325 #define HDA_SDSTS_BCIS RT_BIT(2) /* Buffer Completion Interrupt Status */ 324 326 325 #define HDA_REG_SD0LPIB 36 /* 0x84; other streams offset by 0x20 */327 #define HDA_REG_SD0LPIB 36 /* 0x84; other streams offset by 0x20 */ 326 328 #define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */ 327 329 #define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */ … … 340 342 #define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70) 341 343 342 #define HDA_REG_SD0CBL 37 /* 0x88; other streams offset by 0x20 */344 #define HDA_REG_SD0CBL 37 /* 0x88; other streams offset by 0x20 */ 343 345 #define HDA_RMX_SD0CBL 35 344 346 #define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10) … … 350 352 #define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70) 351 353 352 #define HDA_REG_SD0LVI 38 /* 0x8C; other streams offset by 0x20 */354 #define HDA_REG_SD0LVI 38 /* 0x8C; other streams offset by 0x20 */ 353 355 #define HDA_RMX_SD0LVI 36 354 356 #define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10) … … 360 362 #define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70) 361 363 362 #define HDA_REG_SD0FIFOW 39 /* 0x8E; other streams offset by 0x20 */364 #define HDA_REG_SD0FIFOW 39 /* 0x8E; other streams offset by 0x20 */ 363 365 #define HDA_RMX_SD0FIFOW 37 364 366 #define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10) … … 377 379 #define HDA_SDFIFOW_32B 0x4 378 380 379 #define HDA_REG_SD0FIFOS 40 /* 0x90; other streams offset by 0x20 */381 #define HDA_REG_SD0FIFOS 40 /* 0x90; other streams offset by 0x20 */ 380 382 #define HDA_RMX_SD0FIFOS 38 381 383 #define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10) … … 387 389 #define HDA_RMX_SD7FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 70) 388 390 389 #define HDA_SDIFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */390 #define HDA_SDIFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */391 392 #define HDA_SDOFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */393 #define HDA_SDOFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */394 #define HDA_SDOFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */395 #define HDA_SDOFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */396 #define HDA_SDOFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */397 #define HDA_SDOFIFO_256B 0xFF /* 20-, 24-bit Output Streams */398 399 #define HDA_REG_SD0FMT 41 /* 0x92; other streams offset by 0x20 */391 #define HDA_SDIFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */ 392 #define HDA_SDIFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */ 393 394 #define HDA_SDOFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */ 395 #define HDA_SDOFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */ 396 #define HDA_SDOFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */ 397 #define HDA_SDOFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */ 398 #define HDA_SDOFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */ 399 #define HDA_SDOFIFO_256B 0xFF /* 20-, 24-bit Output Streams */ 400 401 #define HDA_REG_SD0FMT 41 /* 0x92; other streams offset by 0x20 */ 400 402 #define HDA_RMX_SD0FMT 39 401 403 #define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10) … … 407 409 #define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70) 408 410 409 #define HDA_REG_SD0BDPL 42 /* 0x98; other streams offset by 0x20 */411 #define HDA_REG_SD0BDPL 42 /* 0x98; other streams offset by 0x20 */ 410 412 #define HDA_RMX_SD0BDPL 40 411 413 #define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10) … … 417 419 #define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70) 418 420 419 #define HDA_REG_SD0BDPU 43 /* 0x9C; other streams offset by 0x20 */421 #define HDA_REG_SD0BDPU 43 /* 0x9C; other streams offset by 0x20 */ 420 422 #define HDA_RMX_SD0BDPU 41 421 423 #define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10) … … 428 430 429 431 #define HDA_CODEC_CAD_SHIFT 28 430 /* Encodes the (required) LUN into a codec command. */432 /** Encodes the (required) LUN into a codec command. */ 431 433 #define HDA_CODEC_CMD(cmd, lun) ((cmd) | (lun << HDA_CODEC_CAD_SHIFT)) 432 434 433 #define HDA_SDFMT_NON_PCM_SHIFT 434 #define HDA_SDFMT_NON_PCM_MASK 435 #define HDA_SDFMT_BASE_RATE_SHIFT 436 #define HDA_SDFMT_BASE_RATE_MASK 437 #define HDA_SDFMT_MULT_SHIFT 438 #define HDA_SDFMT_MULT_MASK 439 #define HDA_SDFMT_DIV_SHIFT 440 #define HDA_SDFMT_DIV_MASK 441 #define HDA_SDFMT_BITS_SHIFT 442 #define HDA_SDFMT_BITS_MASK 443 #define HDA_SDFMT_CHANNELS_MASK 444 445 #define HDA_SDFMT_TYPE 446 #define HDA_SDFMT_TYPE_PCM 447 #define HDA_SDFMT_TYPE_NON_PCM 448 449 #define HDA_SDFMT_BASE 450 #define HDA_SDFMT_BASE_48KHZ 451 #define HDA_SDFMT_BASE_44KHZ 452 453 #define HDA_SDFMT_MULT_1X 454 #define HDA_SDFMT_MULT_2X 455 #define HDA_SDFMT_MULT_3X 456 #define HDA_SDFMT_MULT_4X 457 458 #define HDA_SDFMT_DIV_1X 459 #define HDA_SDFMT_DIV_2X 460 #define HDA_SDFMT_DIV_3X 461 #define HDA_SDFMT_DIV_4X 462 #define HDA_SDFMT_DIV_5X 463 #define HDA_SDFMT_DIV_6X 464 #define HDA_SDFMT_DIV_7X 465 #define HDA_SDFMT_DIV_8X 466 467 #define HDA_SDFMT_8_BIT 468 #define HDA_SDFMT_16_BIT 469 #define HDA_SDFMT_20_BIT 470 #define HDA_SDFMT_24_BIT 471 #define HDA_SDFMT_32_BIT 472 473 #define HDA_SDFMT_CHAN_MONO 474 #define HDA_SDFMT_CHAN_STEREO 475 476 /* Emits a SDnFMT register format. */477 /* Also being used in the codec's converter format. */435 #define HDA_SDFMT_NON_PCM_SHIFT 15 436 #define HDA_SDFMT_NON_PCM_MASK 0x1 437 #define HDA_SDFMT_BASE_RATE_SHIFT 14 438 #define HDA_SDFMT_BASE_RATE_MASK 0x1 439 #define HDA_SDFMT_MULT_SHIFT 11 440 #define HDA_SDFMT_MULT_MASK 0x7 441 #define HDA_SDFMT_DIV_SHIFT 8 442 #define HDA_SDFMT_DIV_MASK 0x7 443 #define HDA_SDFMT_BITS_SHIFT 4 444 #define HDA_SDFMT_BITS_MASK 0x7 445 #define HDA_SDFMT_CHANNELS_MASK 0xF 446 447 #define HDA_SDFMT_TYPE RT_BIT(15) 448 #define HDA_SDFMT_TYPE_PCM (0) 449 #define HDA_SDFMT_TYPE_NON_PCM (1) 450 451 #define HDA_SDFMT_BASE RT_BIT(14) 452 #define HDA_SDFMT_BASE_48KHZ (0) 453 #define HDA_SDFMT_BASE_44KHZ (1) 454 455 #define HDA_SDFMT_MULT_1X (0) 456 #define HDA_SDFMT_MULT_2X (1) 457 #define HDA_SDFMT_MULT_3X (2) 458 #define HDA_SDFMT_MULT_4X (3) 459 460 #define HDA_SDFMT_DIV_1X (0) 461 #define HDA_SDFMT_DIV_2X (1) 462 #define HDA_SDFMT_DIV_3X (2) 463 #define HDA_SDFMT_DIV_4X (3) 464 #define HDA_SDFMT_DIV_5X (4) 465 #define HDA_SDFMT_DIV_6X (5) 466 #define HDA_SDFMT_DIV_7X (6) 467 #define HDA_SDFMT_DIV_8X (7) 468 469 #define HDA_SDFMT_8_BIT (0) 470 #define HDA_SDFMT_16_BIT (1) 471 #define HDA_SDFMT_20_BIT (2) 472 #define HDA_SDFMT_24_BIT (3) 473 #define HDA_SDFMT_32_BIT (4) 474 475 #define HDA_SDFMT_CHAN_MONO (0) 476 #define HDA_SDFMT_CHAN_STEREO (1) 477 478 /** Emits a SDnFMT register format. 479 * Also being used in the codec's converter format. */ 478 480 #define HDA_SDFMT_MAKE(_afNonPCM, _aBaseRate, _aMult, _aDiv, _aBits, _aChan) \ 479 481 ( (((_afNonPCM) & HDA_SDFMT_NON_PCM_MASK) << HDA_SDFMT_NON_PCM_SHIFT) \
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