Changeset 69068 in vbox for trunk

Timestamp:

Oct 13, 2017 9:14:48 AM (7 years ago)

Author:

vboxsync

Message:

VMM/HMSVMR0: Flush all tagged TLB entries on ASID wrap-around or while enabling SVM on a CPU.

File:

• trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp (modified) (3 diffs)

trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp

@@ -403 +403 @@
      * Theoretically, other hypervisors may have used ASIDs, ideally we should flush all non-zero ASIDs
      * when enabling SVM. AMD doesn't have an SVM instruction to flush all ASIDs (flushing is done
-     * upon VMRUN). Therefore, just set the fFlushAsidBeforeUse flag which instructs hmR0SvmSetupTLB()
-     * to flush the TLB with before using a new ASID.
+     * upon VMRUN). Therefore, flag that we need to flush the TLB entirely with before executing any
+     * guest code.
      */
     pCpu->fFlushAsidBeforeUse = true;
@@ -958 +958 @@
             {
                 ++pCpu->uCurrentAsid;
+
                 bool fHitASIDLimit = false;
                 if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
@@ -964 +965 @@
                     pCpu->cTlbFlushes++;         /* All VCPUs that run on this host CPU must use a new ASID. */
                     fHitASIDLimit      = true;
-
-                    if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
-                    {
-                        pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
-                        pCpu->fFlushAsidBeforeUse = true;
-                    }
-                    else
-                    {
-                        pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
-                        pCpu->fFlushAsidBeforeUse = false;
-                    }
                 }
 
-                if (   !fHitASIDLimit
-                    && pCpu->fFlushAsidBeforeUse)
+                if (   fHitASIDLimit
+                    || pCpu->fFlushAsidBeforeUse)
                 {
-                    if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
-                        pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
-                    else
-                    {
-                        pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
-                        pCpu->fFlushAsidBeforeUse = false;
-                    }
+                    pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
+                    pCpu->fFlushAsidBeforeUse = false;
                 }