Changeset 69764 in vbox for trunk/src/VBox/VMM/VMMR0

Timestamp:

Nov 20, 2017 9:14:10 AM (7 years ago)

Author:

vboxsync

Message:

VMM: Nested Hw.virt: SVM fixes.

File:

• trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp (modified) (13 diffs)

trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp

@@ -2002 +2002 @@
  * hardware-assisted SVM.
  *
+ * @returns true if the VMCB was previously already cached, false otherwise.
  * @param   pCtx            Pointer to the guest-CPU context.
  *
  * @sa      HMSvmNstGstVmExitNotify.
  */
-static void hmR0SvmVmRunCacheVmcb(PVMCPU pVCpu, PCPUMCTX pCtx)
+static bool hmR0SvmVmRunCacheVmcb(PVMCPU pVCpu, PCPUMCTX pCtx)
 {
     PSVMVMCB            pVmcbNstGst      = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
@@ -2020 +2021 @@
      * cache and restore it, see AMD spec. 15.25.4 "Nested Paging and VMRUN/#VMEXIT".
      */
-    if (!pNstGstVmcbCache->fValid)
+    bool const fWasCached = pCtx->hwvirt.svm.fHMCachedVmcb;
+    if (!fWasCached)
     {
         pNstGstVmcbCache->u16InterceptRdCRx = pVmcbNstGstCtrl->u16InterceptRdCRx;
@@ -2037 +2039 @@
         pNstGstVmcbCache->TLBCtrl           = pVmcbNstGstCtrl->TLBCtrl;
         pNstGstVmcbCache->NestedPagingCtrl  = pVmcbNstGstCtrl->NestedPaging;
-        pNstGstVmcbCache->fValid            = true;
+        pCtx->hwvirt.svm.fHMCachedVmcb      = true;
         Log4(("hmR0SvmVmRunCacheVmcb: Cached VMCB fields\n"));
     }
+
+    return fWasCached;
 }
 
@@ -2058 +2062 @@
      * First cache the nested-guest VMCB fields we may potentially modify.
      */
-    hmR0SvmVmRunCacheVmcb(pVCpu, pCtx);
-
-    /*
-     * The IOPM of the nested-guest can be ignored because the the guest always
-     * intercepts all IO port accesses. Thus, we'll swap to the guest IOPM rather
-     * into the nested-guest one and swap it back on the #VMEXIT.
-     */
-    pVmcbNstGstCtrl->u64IOPMPhysAddr = g_HCPhysIOBitmap;
-
-    /*
-     * Load the host-physical address into the MSRPM rather than the nested-guest
-     * physical address (currently we trap all MSRs in the nested-guest).
-     */
-    pVmcbNstGstCtrl->u64MSRPMPhysAddr = g_HCPhysNstGstMsrBitmap;
-
-    /*
-     * Use the same nested-paging as the "outer" guest. We can't dynamically
-     * switch off nested-paging suddenly while executing a VM (see assertion at the
-     * end of Trap0eHandler in PGMAllBth.h).
-     */
-    pVmcbNstGstCtrl->NestedPaging.n.u1NestedPaging = pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging;
+    bool const fVmcbCached = hmR0SvmVmRunCacheVmcb(pVCpu, pCtx);
+    if (!fVmcbCached)
+    {
+        /*
+         * The IOPM of the nested-guest can be ignored because the the guest always
+         * intercepts all IO port accesses. Thus, we'll swap to the guest IOPM rather
+         * into the nested-guest one and swap it back on the #VMEXIT.
+         */
+        pVmcbNstGstCtrl->u64IOPMPhysAddr = g_HCPhysIOBitmap;
+
+        /*
+         * Load the host-physical address into the MSRPM rather than the nested-guest
+         * physical address (currently we trap all MSRs in the nested-guest).
+         */
+        pVmcbNstGstCtrl->u64MSRPMPhysAddr = g_HCPhysNstGstMsrBitmap;
+
+        /*
+         * Use the same nested-paging as the "outer" guest. We can't dynamically
+         * switch off nested-paging suddenly while executing a VM (see assertion at the
+         * end of Trap0eHandler in PGMAllBth.h).
+         */
+        pVmcbNstGstCtrl->NestedPaging.n.u1NestedPaging = pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging;
+    }
+    else
+    {
+        Assert(pVmcbNstGstCtrl->u64IOPMPhysAddr == g_HCPhysIOBitmap);
+        Assert(pVmcbNstGstCtrl->u64MSRPMPhysAddr = g_HCPhysNstGstMsrBitmap);
+        Assert(pVmcbNstGstCtrl->NestedPaging.n.u1NestedPaging == pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
+    }
 }
 
@@ -2097 +2109 @@
     PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
     Assert(pVmcbNstGst);
-
-    hmR0SvmVmRunSetupVmcb(pVCpu, pCtx);
 
     hmR0SvmLoadGuestSegmentRegs(pVCpu, pVmcbNstGst, pCtx);
@@ -2541 +2551 @@
     /* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
     VMMRZCallRing3Disable(pVCpu);
-    Log4(("hmR0SvmExitToRing3: rcExit=%d\n", rcExit));
+    Log4(("hmR0SvmExitToRing3: VCPU[%u]: rcExit=%d LocalFF=%#RX32 GlobalFF=%#RX32\n", pVCpu->idCpu, rcExit,
+          pVCpu->fLocalForcedActions, pVM->fGlobalForcedActions));
 
     /* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
@@ -2570 +2581 @@
     if (rcExit != VINF_EM_RAW_INTERRUPT)
         HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
+
+#ifdef VBOX_WITH_NESTED_HWVIRT
+    /*
+     * We may inspect the nested-guest VMCB state in ring-3 (e.g. for injecting interrupts)
+     * and thus we need to restore any modifications we may have made to it here if we're
+     * still executing the nested-guest.
+     */
+    if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
+        HMSvmNstGstVmExitNotify(pVCpu, pCtx);
+#endif
 
     STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
@@ -3021 +3042 @@
 
 #ifdef VBOX_WITH_NESTED_HWVIRT
+/**
+ * Checks whether the SVM nested-guest is in a state to receive physical (APIC)
+ * interrupts.
+ *
+ * @returns true if it's ready, false otherwise.
+ * @param   pCtx        The guest-CPU context.
+ *
+ * @remarks This function looks at the VMCB cache rather than directly at the
+ *          nested-guest VMCB which may have been suitably modified for executing
+ *          using hardware-assisted SVM.
+ */
+static bool hmR0SvmCanNstGstTakePhysIntr(PVMCPU pVCpu, PCCPUMCTX pCtx)
+{
+    Assert(pCtx->hwvirt.svm.fHMCachedVmcb);
+    PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
+    X86EFLAGS fEFlags;
+    if (pVmcbNstGstCache->fVIntrMasking)
+        fEFlags.u = pCtx->hwvirt.svm.HostState.rflags.u;
+    else
+        fEFlags.u = pCtx->eflags.u;
+
+    return fEFlags.Bits.u1IF;
+}
+
+
 /**
  * Evaluates the event to be delivered to the nested-guest and sets it as the
@@ -3088 +3134 @@
          * see AMD spec. 15.21.4 "Injecting Virtual (INTR) Interrupts".
          */
+        PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
+        Assert(pCtx->hwvirt.svm.fHMCachedVmcb);
         if (   VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC)
             && !fIntShadow
             && !pVCpu->hm.s.fSingleInstruction
-            && CPUMCanSvmNstGstTakePhysIntr(pCtx))
-        {
-            if (CPUMIsGuestSvmCtrlInterceptSet(pCtx, SVM_CTRL_INTERCEPT_INTR))
+            && hmR0SvmCanNstGstTakePhysIntr(pVCpu, pCtx))
+        {
+            if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_INTR)
             {
                 Log4(("Intercepting external interrupt -> #VMEXIT\n"));
@@ -3128 +3176 @@
         /*
          * Check if the nested-guest can receive virtual (injected by VMRUN) interrupts.
-         * We can call CPUMCanSvmNstGstTakeVirtIntr here as we don't cache/modify any
+         * We can safely call CPUMCanSvmNstGstTakeVirtIntr here as we don't cache/modify any
          * nested-guest VMCB interrupt control fields besides V_INTR_MASKING, see hmR0SvmVmRunCacheVmcb.
          */
-        if (   VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST)
-            && CPUMCanSvmNstGstTakeVirtIntr(pCtx)
-            && CPUMIsGuestSvmCtrlInterceptSet(pCtx, SVM_CTRL_INTERCEPT_VINTR))
+        if (   (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR)
+            && VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST)
+            && CPUMCanSvmNstGstTakeVirtIntr(pCtx))
         {
             Log4(("Intercepting virtual interrupt -> #VMEXIT\n"));
@@ -3569 +3617 @@
         return rc;
 
+    hmR0SvmVmRunSetupVmcb(pVCpu, pCtx);
+
     if (TRPMHasTrap(pVCpu))
         hmR0SvmTrpmTrapToPendingEvent(pVCpu);
@@ -3598 +3648 @@
     STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull);
 
-    Assert(pVCpu->hm.s.svm.NstGstVmcbCache.fValid);
+    Assert(pCtx->hwvirt.svm.fHMCachedVmcb);
 
     /*
@@ -4133 +4183 @@
     hmR0SvmSaveGuestState(pVCpu, pMixedCtx, pVmcbNstGst);       /* Save the nested-guest state from the VMCB to the
                                                                    guest-CPU context. */
-
-    /*
-     * Currently, reload the entire nested-guest VMCB due to code that directly inspects
-     * the nested-guest VMCB instead of the cache, e.g. hmR0SvmEvaluatePendingEventNested.
-     */
-    HMSvmNstGstVmExitNotify(pVCpu, pVmcbNstGst);
-    HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
 }
 #endif