Changeset 70177 in vbox for trunk/src/VBox

Timestamp:

Dec 16, 2017 4:07:02 AM (7 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

119742

Message:

VMM/HMSVMR0: Ensure clean bits are updated while loading/merging nested-guest state intercepts.
Clear VINTR intercepts once clgi is emulated (esp. when VGIF isn't supported).
Comments, cleanups.

File:

• trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp (modified) (8 diffs)

trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp

@@ -1854 +1854 @@
         /* First, load the guest intercepts into the guest VMCB. */
         PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
+        Assert(!(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR));
         hmR0SvmLoadGuestXcptIntercepts(pVCpu, pVmcb, pCtx);
 
@@ -1891 +1892 @@
                == HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS);
         pVmcbNstGst->ctrl.u64InterceptCtrl  &= ~SVM_CTRL_INTERCEPT_VMMCALL;
+
+        /* Finally, update the VMCB clean bits. */
+        pVmcbNstGst->ctrl.u64VmcbCleanBits  &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
 
         Assert(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS));
@@ -2261 +2265 @@
                ("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
 
-    Log4(("hmR0SvmLoadGuestStateNested: CS:RIP=%04x:%RX64 EFL=%#x CR0=%#RX32 CR3=%#RX32 (HyperCR3=%#RX64) CR4=%#RX32 rc=%d\n",
-          pCtx->cs.Sel, pCtx->rip, pCtx->eflags.u, pCtx->cr0, pCtx->cr3, pVmcbNstGst->guest.u64CR3, pCtx->cr4, rc));
+    Log4(("hmR0SvmLoadGuestStateNested: CS:RIP=%04x:%RX64 EFL=%#x CR0=%#RX32 CR3=%#RX32 (HyperCR3=%#RX64) CR4=%#RX32 "
+          "ESP=%#RX32 EBP=%#RX32 rc=%d\n", pCtx->cs.Sel, pCtx->rip, pCtx->eflags.u, pCtx->cr0, pCtx->cr3,
+          pVmcbNstGst->guest.u64CR3, pCtx->cr4, pCtx->esp, pCtx->ebp, rc));
     STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
+
     return rc;
 }
@@ -3117 +3123 @@
 
 /**
- * Sets the virtual interrupt intercept control in the VMCB which
- * instructs AMD-V to cause a \#VMEXIT as soon as the guest is in a state to
- * receive interrupts.
+ * Sets the virtual interrupt intercept control in the VMCB.
  *
  * @param   pVmcb       Pointer to the VM control block.
@@ -3125 +3129 @@
 DECLINLINE(void) hmR0SvmSetVirtIntrIntercept(PSVMVMCB pVmcb)
 {
+    /*
+     * When AVIC isn't supported, indicate that a virtual interrupt is pending and to
+     * cause a #VMEXIT when the guest is ready to accept interrupts. At #VMEXIT, we
+     * then get the interrupt from the APIC (updating ISR at the right time) and
+     * inject the interrupt.
+     *
+     * With AVIC is supported, we could make use of the asynchronously delivery without
+     * #VMEXIT and we would be passing the AVIC page to SVM.
+     */
     if (!(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR))
     {
-        pVmcb->ctrl.IntCtrl.n.u1VIrqPending = 1;     /* A virtual interrupt is pending. */
-        pVmcb->ctrl.IntCtrl.n.u8VIntrVector = 0;     /* Vector not necessary as we #VMEXIT for delivering the interrupt. */
+        Assert(pVmcb->ctrl.IntCtrl.n.u1VIrqPending == 0);
+        pVmcb->ctrl.IntCtrl.n.u1VIrqPending = 1;
         pVmcb->ctrl.u64InterceptCtrl |= SVM_CTRL_INTERCEPT_VINTR;
         pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS | HMSVM_VMCB_CLEAN_TPR);
-
-        Log4(("Setting VINTR intercept\n"));
-    }
-}
-
-
-#if 0
+        Log4(("Set VINTR intercept\n"));
+    }
+}
+
+
 /**
  * Clears the virtual interrupt intercept control in the VMCB as
@@ -3149 +3160 @@
     if (pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR)
     {
+        Assert(pVmcb->ctrl.IntCtrl.n.u1VIrqPending == 1);
+        pVmcb->ctrl.IntCtrl.n.u1VIrqPending = 0;
         pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_VINTR;
-        pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS);
-        Log4(("Clearing VINTR intercept\n"));
-    }
-}
-#endif
+        pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS | HMSVM_VMCB_CLEAN_TPR);
+        Log4(("Cleared VINTR intercept\n"));
+    }
+}
 
 
@@ -6911 +6923 @@
 
     PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
-    pVmcb->ctrl.IntCtrl.n.u1VIrqPending = 0;  /* No virtual interrupts pending, we'll inject the current one/NMI before reentry. */
-    pVmcb->ctrl.IntCtrl.n.u8VIntrVector = 0;
-
-    /* Indicate that we no longer need to #VMEXIT when the guest is ready to receive interrupts/NMIs, it is now ready. */
-    pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_VINTR;
-    pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS | HMSVM_VMCB_CLEAN_TPR);
+    hmR0SvmClearVirtIntrIntercept(pVmcb);
 
     /* Deliver the pending interrupt/NMI via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
@@ -7459 +7466 @@
     uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
     VBOXSTRICTRC rcStrict = IEMExecDecodedClgi(pVCpu, cbInstr);
+
+    /*
+     * The guest should no longer receive interrupts. Until VGIF is supported,
+     * clear virtual interrupt intercepts here.
+     */
+    PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
+    hmR0SvmClearVirtIntrIntercept(pVmcb);
+
     return VBOXSTRICTRC_VAL(rcStrict);
 }