Changeset 70232 in vbox for trunk/src/VBox/VMM/VMMR0
- Timestamp:
- Dec 20, 2017 11:20:39 AM (7 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp
r70177 r70232 3304 3304 /* 3305 3305 * AMD-V has no TPR thresholding feature. We just avoid posting the interrupt. 3306 * We just avoid delivering the TPR-masked interrupt here. TPR will be updated3307 * always via hmR0SvmLoadGuestState() -> hmR0SvmLoadGuestApicState().3306 * We just avoid delivering the TPR-masked interrupt here. TPR and the force-flag 3307 * will be updated eventually when the TPR is written by the guest. 3308 3308 */ 3309 3309 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq); … … 3314 3314 3315 3315 /* 3316 * Check if the nested-guest can receive virtual (injected by VMRUN) interrupts.3317 * We can safely call CPUMCanSvmNstGstTakeVirtIntr here as we don't cache/modify any3318 * nested-guest VMCB interrupt control fields besides V_INTR_MASKING, see hmR0SvmVmRunCacheVmcb.3316 * Check if the nested-guest is intercepting virtual (using V_IRQ and related fields) 3317 * interrupt injection. The virtual interrupt injection itself, if any, will be done 3318 * by the physical CPU. 3319 3319 */ 3320 3320 if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST) … … 3419 3419 /* 3420 3420 * AMD-V has no TPR thresholding feature. We just avoid posting the interrupt. 3421 * We just avoid delivering the TPR-masked interrupt here. TPR will be updated3422 * always via hmR0SvmLoadGuestState() -> hmR0SvmLoadGuestApicState().3421 * We just avoid delivering the TPR-masked interrupt here. TPR and the force-flag 3422 * will be updated eventually when the TPR is written by the guest. 3423 3423 */ 3424 3424 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
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