Index: trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp	(revision 70254)
+++ trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp	(revision 70258)
@@ -777,5 +777,5 @@
         ASMBitClear(pbMsrBitmap, uMsrpmBit + 1);
 
-    pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
+    pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
 }
 
@@ -862,5 +862,5 @@
 
         /* Initially set all VMCB clean bits to 0 indicating that everything should be loaded from the VMCB in memory. */
-        pVmcb->ctrl.u64VmcbCleanBits = 0;
+        pVmcb->ctrl.u32VmcbCleanBits = 0;
 
         /* The host ASID MBZ, for the guest start with 1. */
@@ -1049,5 +1049,5 @@
 
         /* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
-        pVmcb->ctrl.u64VmcbCleanBits    &= ~HMSVM_VMCB_CLEAN_NP;
+        pVmcb->ctrl.u32VmcbCleanBits    &= ~HMSVM_VMCB_CLEAN_NP;
 
         /* Keep track of last CPU ID even when flushing all the time. */
@@ -1061,5 +1061,5 @@
         {
             /* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
-            pVmcb->ctrl.u64VmcbCleanBits    &= ~HMSVM_VMCB_CLEAN_NP;
+            pVmcb->ctrl.u32VmcbCleanBits    &= ~HMSVM_VMCB_CLEAN_NP;
 
             if (fNewAsid)
@@ -1102,5 +1102,5 @@
     {
         pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hm.s.uCurrentAsid;
-        pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_ASID;
+        pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_ASID;
     }
 
@@ -1223,5 +1223,5 @@
     {
         pVmcb->ctrl.u32InterceptXcpt |= RT_BIT(u32Xcpt);
-        pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
+        pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
     }
 }
@@ -1263,5 +1263,5 @@
         {
             pVmcb->ctrl.u32InterceptXcpt &= ~RT_BIT(u32Xcpt);
-            pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
+            pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
         }
     }
@@ -1338,5 +1338,5 @@
 
     pVmcb->guest.u64CR0 = u64GuestCR0;
-    pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
+    pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
 }
 
@@ -1362,5 +1362,5 @@
     {
         pVmcb->guest.u64CR2 = pCtx->cr2;
-        pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CR2;
+        pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CR2;
         HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR2);
     }
@@ -1382,5 +1382,5 @@
 
             pVmcb->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
-            pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
+            pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
             Assert(pVmcb->ctrl.u64NestedPagingCR3);
             pVmcb->guest.u64CR3 = pCtx->cr3;
@@ -1392,5 +1392,5 @@
         }
 
-        pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
+        pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
         HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR3);
     }
@@ -1439,5 +1439,5 @@
 
         pVmcb->guest.u64CR4 = u64GuestCR4;
-        pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
+        pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
 
         /* Whether to save/load/restore XCR0 during world switch depends on CR4.OSXSAVE and host+guest XCR0. */
@@ -1474,5 +1474,5 @@
 
         pVmcb->guest.u8CPL = pCtx->ss.Attr.n.u2Dpl;
-        pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
+        pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
         HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS);
     }
@@ -1497,5 +1497,5 @@
         pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
         pVmcb->guest.GDTR.u64Base  = pCtx->gdtr.pGdt;
-        pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
+        pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
         HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_GDTR);
     }
@@ -1506,5 +1506,5 @@
         pVmcb->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
         pVmcb->guest.IDTR.u64Base  = pCtx->idtr.pIdt;
-        pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
+        pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
         HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_IDTR);
     }
@@ -1536,5 +1536,5 @@
     {
         pVmcb->guest.u64EFER = pCtx->msrEFER | MSR_K6_EFER_SVME;
-        pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
+        pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
         HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_EFER_MSR);
     }
@@ -1552,5 +1552,5 @@
         {
             pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
-            pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
+            pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
         }
     }
@@ -1629,5 +1629,5 @@
             pVmcb->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
             pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
-            pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
+            pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
             pVCpu->hm.s.fUsingHyperDR7 = true;
         }
@@ -1648,5 +1648,5 @@
             pVmcb->guest.u64DR7 = pCtx->dr[7];
             pVmcb->guest.u64DR6 = pCtx->dr[6];
-            pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
+            pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
             pVCpu->hm.s.fUsingHyperDR7 = false;
         }
@@ -1705,5 +1705,5 @@
             pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
             pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
-            pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
+            pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
         }
     }
@@ -1715,5 +1715,5 @@
             pVmcb->ctrl.u16InterceptRdDRx = 0;
             pVmcb->ctrl.u16InterceptWrDRx = 0;
-            pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
+            pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
         }
     }
@@ -1736,5 +1736,5 @@
         pVmcbNstGst->ctrl.IntCtrl.n.u1VIntrMasking = 1;
         pVCpu->hm.s.svm.fSyncVTpr = false;
-        pVmcbNstGst->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_TPR;
+        pVmcbNstGst->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_TPR;
 
         HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
@@ -1800,5 +1800,5 @@
             }
 
-            pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS | HMSVM_VMCB_CLEAN_TPR);
+            pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS | HMSVM_VMCB_CLEAN_TPR);
         }
     }
@@ -1897,5 +1897,5 @@
 
         /* Finally, update the VMCB clean bits. */
-        pVmcbNstGst->ctrl.u64VmcbCleanBits  &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
+        pVmcbNstGst->ctrl.u32VmcbCleanBits  &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
 
         Assert(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS));
@@ -2157,5 +2157,5 @@
         pNstGstVmcbCache->u64MSRPMPhysAddr  = pVmcbNstGstCtrl->u64MSRPMPhysAddr;
         pNstGstVmcbCache->u64TSCOffset      = pVmcbNstGstCtrl->u64TSCOffset;
-        pNstGstVmcbCache->u64VmcbCleanBits  = pVmcbNstGstCtrl->u64VmcbCleanBits;
+        pNstGstVmcbCache->u32VmcbCleanBits  = pVmcbNstGstCtrl->u32VmcbCleanBits;
         pNstGstVmcbCache->fVIntrMasking     = pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking;
         pNstGstVmcbCache->TLBCtrl           = pVmcbNstGstCtrl->TLBCtrl;
@@ -2760,5 +2760,5 @@
 
     /* Finally update the VMCB clean bits since we touched the intercepts as well as the TSC offset. */
-    pVmcbNstGstCtrl->u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
+    pVmcbNstGstCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
 
     if (fParavirtTsc)
@@ -2798,5 +2798,5 @@
         STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
     }
-    pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
+    pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
 
     /** @todo later optimize this to be done elsewhere and not before every
@@ -3146,5 +3146,5 @@
         pVmcb->ctrl.IntCtrl.n.u1VIrqPending = 1;
         pVmcb->ctrl.u64InterceptCtrl |= SVM_CTRL_INTERCEPT_VINTR;
-        pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS | HMSVM_VMCB_CLEAN_TPR);
+        pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS | HMSVM_VMCB_CLEAN_TPR);
         Log4(("Set VINTR intercept\n"));
     }
@@ -3166,5 +3166,5 @@
         pVmcb->ctrl.IntCtrl.n.u1VIrqPending = 0;
         pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_VINTR;
-        pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS | HMSVM_VMCB_CLEAN_TPR);
+        pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS | HMSVM_VMCB_CLEAN_TPR);
         Log4(("Cleared VINTR intercept\n"));
     }
@@ -3184,5 +3184,5 @@
     {
         pVmcb->ctrl.u64InterceptCtrl |= SVM_CTRL_INTERCEPT_IRET;
-        pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
+        pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
 
         Log4(("Setting IRET intercept\n"));
@@ -3201,5 +3201,5 @@
     {
         pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_IRET;
-        pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS);
+        pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS);
 
         Log4(("Clearing IRET intercept\n"));
@@ -3520,5 +3520,5 @@
         hmR0DumpRegs(pVM, pVCpu, pCtx); NOREF(pVM);
 #ifdef VBOX_STRICT
-        Log4(("ctrl.u64VmcbCleanBits             %#RX64\n",   pVmcb->ctrl.u64VmcbCleanBits));
+        Log4(("ctrl.u32VmcbCleanBits             %#RX32\n",   pVmcb->ctrl.u32VmcbCleanBits));
         Log4(("ctrl.u16InterceptRdCRx            %#x\n",      pVmcb->ctrl.u16InterceptRdCRx));
         Log4(("ctrl.u16InterceptWrCRx            %#x\n",      pVmcb->ctrl.u16InterceptWrCRx));
@@ -4033,5 +4033,5 @@
     /* If we've migrating CPUs, mark the VMCB Clean bits as dirty. */
     if (idCurrentCpu != pVCpu->hm.s.idLastCpu)
-        pVmcbNstGst->ctrl.u64VmcbCleanBits = 0;
+        pVmcbNstGst->ctrl.u32VmcbCleanBits = 0;
 
     /* Store status of the shared guest-host state at the time of VMRUN. */
@@ -4089,5 +4089,5 @@
     bool const fSupportsVmcbCleanBits = hmR0SvmSupportsVmcbCleanBits(pVCpu, pCtx);
     if (!fSupportsVmcbCleanBits)
-        pVmcbNstGst->ctrl.u64VmcbCleanBits = 0;
+        pVmcbNstGst->ctrl.u32VmcbCleanBits = 0;
 }
 #endif
@@ -4145,5 +4145,5 @@
     /* If we've migrating CPUs, mark the VMCB Clean bits as dirty. */
     if (idCurrentCpu != pVCpu->hm.s.idLastCpu)
-        pVmcb->ctrl.u64VmcbCleanBits = 0;
+        pVmcb->ctrl.u32VmcbCleanBits = 0;
 
     /* Store status of the shared guest-host state at the time of VMRUN. */
@@ -4198,5 +4198,5 @@
     bool const fSupportsVmcbCleanBits = hmR0SvmSupportsVmcbCleanBits(pVCpu, pCtx);
     if (!fSupportsVmcbCleanBits)
-        pVmcb->ctrl.u64VmcbCleanBits = 0;
+        pVmcb->ctrl.u32VmcbCleanBits = 0;
 }
 
@@ -4310,5 +4310,5 @@
 
     /* Mark the VMCB-state cache as unmodified by VMM. */
-    pVmcbNstGstCtrl->u64VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL;
+    pVmcbNstGstCtrl->u32VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL;
 
     /* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
@@ -4354,5 +4354,5 @@
 
     PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
-    pVmcb->ctrl.u64VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL;        /* Mark the VMCB-state cache as unmodified by VMM. */
+    pVmcb->ctrl.u32VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL;        /* Mark the VMCB-state cache as unmodified by VMM. */
 
     /* TSC read must be done early for maximum accuracy. */
@@ -6512,5 +6512,5 @@
             pVmcb->ctrl.u16InterceptRdDRx = 0;
             pVmcb->ctrl.u16InterceptWrDRx = 0;
-            pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
+            pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
 
             /* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
@@ -6763,5 +6763,5 @@
                 pVmcb->guest.u64DR6 = pCtx->dr[6];
                 pVmcb->guest.u64DR7 = pCtx->dr[7];
-                pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
+                pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
                 hmR0SvmSetPendingXcptDB(pVCpu);
             }
@@ -7323,5 +7323,5 @@
         Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> %Rrc\n", pVmcb->guest.u64DR6, rc));
         pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
-        pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
+        pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
     }
     else
