VirtualBox

Changeset 70606 in vbox for trunk/include


Ignore:
Timestamp:
Jan 16, 2018 7:05:36 PM (7 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
120319
Message:

updates (bugref:9087)

Location:
trunk
Files:
7 edited

Legend:

Unmodified
Added
Removed

  • trunk

    • Property svn:mergeinfo

      •  

        old new  
        88/branches/VBox-5.0:104445,104938,104943,104950,104952-104953,104987-104988,104990,106453
        99/branches/VBox-5.1:112367,115992,116543,116550,116568,116573
         10/branches/VBox-5.2:120083,120099,120213,120221,120239
        1011/branches/andy/draganddrop:90781-91268
        1112/branches/andy/guestctrl20:78916,78930

  • trunk/include/VBox/settings.h

    r69107 r70606  
    905905                        fAPIC,                  // requires settings version 1.16 (VirtualBox 5.1)
    906906                        fX2APIC;                // requires settings version 1.16 (VirtualBox 5.1)
     907    bool                fIBPBOnVMExit;          //< added out of cycle, after 1.16 was out.
     908    bool                fIBPBOnVMEntry;         //< added out of cycle, after 1.16 was out.
    907909    typedef enum LongModeType { LongMode_Enabled, LongMode_Disabled, LongMode_Legacy } LongModeType;
    908910    LongModeType        enmLongMode;

  • trunk/include/VBox/vmm/cpum.h

    r70555 r70606  
    10261026    /** Supports CLFLUSHOPT. */
    10271027    uint32_t        fClFlushOpt : 1;
     1028    /** Supports IA32_PRED_CMD.IBPB. */
     1029    uint32_t        fIbpb : 1;
     1030    /** Supports IA32_SPEC_CTRL.IBRS. */
     1031    uint32_t        fIbrs : 1;
     1032    /** Supports IA32_SPEC_CTRL.STIBP. */
     1033    uint32_t        fStibp : 1;
     1034    /** Supports IA32_ARCH_CAP. */
     1035    uint32_t        fArchCap : 1;
    10281036
    10291037    /** Supports AMD 3DNow instructions. */
    … …  
    10591067
    10601068    /** Alignment padding / reserved for future use. */
    1061     uint32_t        fPadding : 23;
     1069    uint32_t        fPadding : 19;
    10621070
    10631071    /** SVM: Supports Nested-paging. */

  • trunk/include/VBox/vmm/cpum.mac

    r69764 r70606  
    147147%define XSTATE_SIZE             8192
    148148
     149;; Note! Updates here must be reflected in CPUMInternal.mac too!
    149150struc CPUMCTX
    150151    .eax                resq    1
    … …  
    250251    .fXStateMask        resq    1
    251252    .pXStateR0      RTR0PTR_RES 1
     253    alignb 8
    252254    .pXStateR3      RTR3PTR_RES 1
     255    alignb 8
    253256    .pXStateRC      RTRCPTR_RES 1
    254257    .aoffXState         resw    64
    255 %if HC_ARCH_BITS == 64
    256     .abPadding          resb    4
    257 %else
    258     .abPadding          resb    12
    259 %endif
     258    .fWorldSwitcher     resd    1
     259    alignb 8
    260260    .hwvirt.svm.uMsrHSavePa            resq          1
    261261    .hwvirt.svm.GCPhysVmcb             resq          1
    … …  
    284284endstruc
    285285
     286%define CPUMCTX_WSF_IBPB_EXIT           RT_BIT_32(0)
     287%define CPUMCTX_WSF_IBPB_ENTRY          RT_BIT_32(1)
    286288
    287289%define CPUMSELREG_FLAGS_VALID      0x0001

  • trunk/include/VBox/vmm/cpumctx.h

    r69764 r70606  
    458458    /** Pointer to the FPU/SSE/AVX/XXXX state ring-0 mapping. */
    459459    R0PTRTYPE(PX86XSAVEAREA)    pXStateR0;
     460#if HC_ARCH_BITS == 32
     461    uint32_t                    uXStateR0Padding;
     462#endif
    460463    /** Pointer to the FPU/SSE/AVX/XXXX state ring-3 mapping. */
    461464    R3PTRTYPE(PX86XSAVEAREA)    pXStateR3;
     465#if HC_ARCH_BITS == 32
     466    uint32_t                    uXStateR3Padding;
     467#endif
    462468    /** Pointer to the FPU/SSE/AVX/XXXX state raw-mode mapping. */
    463469    RCPTRTYPE(PX86XSAVEAREA)    pXStateRC;
    … …  
    465471    uint16_t                    aoffXState[64];
    466472
    467     /** 724 - Size padding. */
    468     uint8_t                     abPadding[HC_ARCH_BITS == 64 ? 4 : 12];
     473    /** 0x2d4 - World switcher flags, CPUMCTX_WSF_XXX. */
     474    uint32_t                    fWorldSwitcher;
    469475
    470476    /** 728 - Hardware virtualization state.   */
    … …  
    579585AssertCompileMemberOffset(CPUMCTX,                fXStateMask, 568);
    580586AssertCompileMemberOffset(CPUMCTX,                  pXStateR0, 576);
    581 AssertCompileMemberOffset(CPUMCTX,                  pXStateR3, HC_ARCH_BITS == 64 ? 584 : 580);
    582 AssertCompileMemberOffset(CPUMCTX,                  pXStateRC, HC_ARCH_BITS == 64 ? 592 : 584);
    583 AssertCompileMemberOffset(CPUMCTX,                 aoffXState, HC_ARCH_BITS == 64 ? 596 : 588);
     587AssertCompileMemberOffset(CPUMCTX,                  pXStateR3, 584);
     588AssertCompileMemberOffset(CPUMCTX,                  pXStateRC, 592);
     589AssertCompileMemberOffset(CPUMCTX,                 aoffXState, 596);
    584590AssertCompileMemberOffset(CPUMCTX, hwvirt, 728);
    585591AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.uMsrHSavePa,            728);
    … …  
    737743#endif /* !VBOX_FOR_DTRACE_LIB */
    738744
     745
     746/** @name CPUMCTX_WSF_XXX
     747 * @{ */
     748/** Touch IA32_PRED_CMD.IBPB on VM exit. */
     749#define CPUMCTX_WSF_IBPB_EXIT           RT_BIT_32(0)
     750/** Touch IA32_PRED_CMD.IBPB on VM entry. */
     751#define CPUMCTX_WSF_IBPB_ENTRY          RT_BIT_32(1)
     752/** @} */
     753
     754
    739755/**
    740756 * Additional guest MSRs (i.e. not part of the CPU context structure).

  • trunk/include/iprt/x86.h

    r70265 r70606  
    598598/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
    599599#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1       RT_BIT_32(0)
     600/** ECX Bit 2 - UIMP - Supports user mode instruction prevention. */
     601#define X86_CPUID_STEXT_FEATURE_ECX_UMIP              RT_BIT_32(2)
     602/** ECX Bit 3 - PKU - Supports protection keys for user-mode pages. */
     603#define X86_CPUID_STEXT_FEATURE_ECX_PKU               RT_BIT_32(3)
     604/** ECX Bit 4 - OSPKE - Protection keys for user mode pages enabled. */
     605#define X86_CPUID_STEXT_FEATURE_ECX_OSPKE             RT_BIT_32(4)
     606/** ECX Bits 17-21 - MAWAU - Value used by BNDLDX and BNDSTX. */
     607#define X86_CPUID_STEXT_FEATURE_ECX_MAWAU             UINT32_C(0x003e0000)
     608/** ECX Bit 22 - RDPID - Support pread process ID. */
     609#define X86_CPUID_STEXT_FEATURE_ECX_RDPID             RT_BIT_32(2)
     610/** ECX Bit 30 - SGX_LC - Supports SGX launch configuration. */
     611#define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC            RT_BIT_32(30)
     612
     613/** EDX Bit 26 - IBRS & IBPB - Supports the IBRS flag in IA32_SPEC_CTRL and
     614 *  IBPB command in IA32_PRED_CMD. */
     615#define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB         RT_BIT_32(26)
     616/** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
     617#define X86_CPUID_STEXT_FEATURE_EDX_STIBP             RT_BIT_32(27)
     618
     619/** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAP MSR. */
     620#define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP           RT_BIT_32(29)
     621
    600622/** @} */
    601623
    … …  
    742764
    743765
     766/** @name CPUID AMD extended feature extensions ID (EBX).
     767 * CPUID query with EAX=0x80000008.
     768 * @{
     769 */
     770/** Bit 0 - CLZERO - Clear zero instruction. */
     771#define X86_CPUID_AMD_EFEID_EBX_CLZERO       RT_BIT_32(0)
     772/** Bit 1 - IRPerf - Instructions retired count support. */
     773#define X86_CPUID_AMD_EFEID_EBX_IRPERF       RT_BIT_32(1)
     774/** Bit 2 - XSaveErPtr - Always XSAVE* and XRSTR* error pointers. */
     775#define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
     776/* AMD pipeline length: 9 feature bits ;-) */
     777/** Bit 12 - IBPB - Supports the IBPB command in IA32_PRED_CMD. */
     778#define X86_CPUID_AMD_EFEID_EBX_IBPB         RT_BIT_32(12)
     779/** @} */
     780
     781
    744782/** @name CPUID AMD SVM Feature information.
    745783 * CPUID query with EAX=0x8000000a.
    … …  
    11141152#define MSR_IA32_TSC_ADJUST                 0x3B
    11151153
     1154/** Spectre control register.
     1155 * Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */
     1156#define MSR_IA32_SPEC_CTRL                  0x48
     1157/** IBRS - Indirect branch restricted speculation. */
     1158#define MSR_IA32_SPEC_CTRL_F_IBRS           RT_BIT_32(0)
     1159/** STIBP - Single thread indirect branch predictors. */
     1160#define MSR_IA32_SPEC_CTRL_F_STIBP          RT_BIT_32(1)
     1161
     1162/** Prediction command register.
     1163 * Write only, logical processor scope, no state since write only. */
     1164#define MSR_IA32_PRED_CMD                   0x49
     1165/** IBPB - Indirect branch prediction barrie when written as 1. */
     1166#define MSR_IA32_PRED_CMD_F_IBPB            RT_BIT_32(0)
     1167
    11161168/** BIOS update trigger (microcode update). */
    11171169#define MSR_IA32_BIOS_UPDT_TRIG             0x79
    … …  
    11481200/** MTRR Capabilities. */
    11491201#define MSR_IA32_MTRR_CAP                   0xFE
     1202
     1203/** Architecture capabilities (bugfixes).
     1204 * @note May move  */
     1205#define MSR_IA32_ARCH_CAP                   UINT32_C(0x10a)
     1206/** CPU is no subject to spectre problems. */
     1207#define MSR_IA32_ARCH_CAP_F_SPECTRE_FIX     RT_BIT_32(0)
     1208/** CPU has better IBRS and you can leave it on all the time. */
     1209#define MSR_IA32_ARCH_CAP_F_BETTER_IBRS     RT_BIT_32(1)
    11501210
    11511211/** Cache control/info. */

  • trunk/include/iprt/x86.mac

    r70459 r70606  
    177177%define X86_CPUID_STEXT_FEATURE_EBX_SHA               RT_BIT_32(29)
    178178%define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1       RT_BIT_32(0)
     179%define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB         RT_BIT_32(26)
     180%define X86_CPUID_STEXT_FEATURE_EDX_STIBP             RT_BIT_32(27)
     181%define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP           RT_BIT_32(29)
    179182%define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF     RT_BIT_32(0)
    180183%define X86_CPUID_EXT_FEATURE_EDX_SYSCALL       RT_BIT_32(11)
    … …  
    380383%define MSR_IA32_FEATURE_CONTROL_VMXON      RT_BIT_32(2)
    381384%define MSR_IA32_TSC_ADJUST                 0x3B
     385%define MSR_IA32_SPEC_CTRL                  0x48
     386%define MSR_IA32_SPEC_CTRL_F_IBRS           RT_BIT_32(0)
     387%define MSR_IA32_SPEC_CTRL_F_STIBP          RT_BIT_32(1)
     388%define MSR_IA32_PRED_CMD                   0x49
     389%define MSR_IA32_PRED_CMD_F_IBPB            RT_BIT_32(0)
    382390%define MSR_IA32_BIOS_UPDT_TRIG             0x79
    383391%define MSR_IA32_BIOS_SIGN_ID               0x8B
    … …  
    393401%define MSR_IA32_APERF                      0xE8
    394402%define MSR_IA32_MTRR_CAP                   0xFE
     403%define MSR_IA32_ARCH_CAP                   0x10a
     404%define MSR_IA32_ARCH_CAP_F_SPECTRE_FIX     RT_BIT_32(0)
     405%define MSR_IA32_ARCH_CAP_F_BETTER_IBRS     RT_BIT_32(1)
    395406%define MSR_BBL_CR_CTL3                     0x11e
    396407%ifndef MSR_IA32_SYSENTER_CS
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