Changeset 7065 in vbox
- Timestamp:
- Feb 20, 2008 9:50:40 PM (17 years ago)
- File:
-
- 1 edited
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- Unmodified
- Added
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trunk/src/VBox/Devices/Network/DevPCNet.cpp
r7044 r7065 97 97 #define PCNET_PNPMMIO_SIZE 0x20 98 98 99 #define PCNET_SAVEDSTATE_VERSION 799 #define PCNET_SAVEDSTATE_VERSION 8 100 100 101 101 #define BCR_MAX_RAP 50 … … 131 131 GCPTRTYPE(PTMTIMER) pTimerPollGC; 132 132 #endif 133 /** Software Interrupt timer (address for host context) */ 134 R3R0PTRTYPE(PTMTIMER) pTimerSoftIntHC; 135 /** Software Interrupt timer (address for guest context) */ 136 GCPTRTYPE(PTMTIMER) pTimerSoftIntGC; 133 137 /** Register Address Pointer */ 134 138 uint32_t u32RAP; … … 348 352 #define CSR_STRT(S) !!((S)->aCSR[0] & 0x0002) /**< Start assertion */ 349 353 #define CSR_STOP(S) !!((S)->aCSR[0] & 0x0004) /**< Stop assertion */ 350 #define CSR_TDMD(S) !!((S)->aCSR[0] & 0x0008) /**< Transmit demand. (perform xmit poll now 351 (readable, settable, not clearable) */ 354 #define CSR_TDMD(S) !!((S)->aCSR[0] & 0x0008) /**< Transmit demand. (perform xmit poll now (readable, settable, not clearable) */ 352 355 #define CSR_TXON(S) !!((S)->aCSR[0] & 0x0010) /**< Transmit on (readonly) */ 353 356 #define CSR_RXON(S) !!((S)->aCSR[0] & 0x0020) /**< Receive On */ 354 357 #define CSR_INEA(S) !!((S)->aCSR[0] & 0x0040) /**< Interrupt Enable */ 355 358 #define CSR_LAPPEN(S) !!((S)->aCSR[3] & 0x0020) /**< Look Ahead Packet Processing Enable */ 356 #define CSR_DXSUFLO(S) !!((S)->aCSR[3] & 0x0040) /**< Disable Transmit Stop on 357 Underflow error */ 359 #define CSR_DXSUFLO(S) !!((S)->aCSR[3] & 0x0040) /**< Disable Transmit Stop on Underflow error */ 358 360 #define CSR_ASTRP_RCV(S) !!((S)->aCSR[4] & 0x0400) /**< Auto Strip Receive */ 359 361 #define CSR_DPOLL(S) !!((S)->aCSR[4] & 0x1000) /**< Disable Transmit Polling */ … … 361 363 #define CSR_LTINTEN(S) !!((S)->aCSR[5] & 0x4000) /**< Last Transmit Interrupt Enable */ 362 364 #define CSR_TOKINTD(S) !!((S)->aCSR[5] & 0x8000) /**< Transmit OK Interrupt Disable */ 365 366 #define CSR_STINT !!((S)->aCSR[7] & 0x0800) /**< Software Timer Interrupt */ 367 #define CSR_STINTE !!((S)->aCSR[7] & 0x0400) /**< Software Timer Interrupt Enable */ 368 363 369 #define CSR_DRX(S) !!((S)->aCSR[15] & 0x0001) /**< Disable Receiver */ 364 370 #define CSR_DTX(S) !!((S)->aCSR[15] & 0x0002) /**< Disable Transmit */ … … 1238 1244 } 1239 1245 1246 if ((pData->aCSR[7] & 0x0C00) == 0x0C00) 1247 iISR = 1; 1248 1240 1249 pData->aCSR[0] = csr0; 1241 1250 … … 2425 2434 pcnetTransmit(pData); 2426 2435 2436 return rc; 2437 } 2438 case 7: 2439 { 2440 uint16_t csr7 = pData->aCSR[7]; 2441 csr7 &= ~0x0400 ; 2442 csr7 &= ~(val & 0x0800); 2443 csr7 |= (val & 0x0400); 2444 pData->aCSR[7] = csr7; 2427 2445 return rc; 2428 2446 } … … 2626 2644 } 2627 2645 #ifdef PCNET_DEBUG_CSR 2628 Log(("#%d pcnetCSRReadU16: u32RAP=%d val=%#06x\n", PCNETSTATE_2_DEVINS(pData)->iInstance,2646 Log(("#%d pcnetCSRReadU16: rap=%d val=%#06x\n", PCNETSTATE_2_DEVINS(pData)->iInstance, 2629 2647 u32RAP, val)); 2630 2648 #endif … … 2637 2655 u32RAP &= 0x7f; 2638 2656 #ifdef PCNET_DEBUG_BCR 2639 Log2(("#%d pcnetBCRWriteU16: u32RAP=%d val=%#06x\n", PCNETSTATE_2_DEVINS(pData)->iInstance,2657 Log2(("#%d pcnetBCRWriteU16: rap=%d val=%#06x\n", PCNETSTATE_2_DEVINS(pData)->iInstance, 2640 2658 u32RAP, val)); 2641 2659 #endif … … 2689 2707 break; 2690 2708 2709 case BCR_STVAL: 2710 val &= 0xffff; 2711 pData->aBCR[BCR_STVAL] = val; 2712 if (pData->fAm79C973) 2713 TMTimerSet(pData->CTXSUFF(pTimerSoftInt), (uint64_t)12800 * val); 2714 break; 2715 2691 2716 case BCR_MIIMDR: 2692 2717 LOG_REGISTER(("PCNet#%d: WRITE MII%d, %#06x\n", 2693 2718 PCNETSTATE_2_DEVINS(pData)->iInstance, u32RAP, val)); 2694 2719 pData->aMII[pData->aBCR[BCR_MIIADDR] & 0x1f] = val; 2720 #ifdef PCNET_DEBUG_MII 2721 Log(("#%d pcnet: mii write %d <- %#x\n", PCNETSTATE_2_DEVINS(pData)->iInstance, 2722 pData->aBCR[BCR_MIIADDR] & 0x1f, val)); 2723 #endif 2695 2724 break; 2696 2725 … … 2707 2736 STAM_COUNTER_INC(&pData->StatMIIReads); 2708 2737 2709 autoneg = (pData->aBCR[BCR_MIICAS] & 0x20) != 0 ;2738 autoneg = (pData->aBCR[BCR_MIICAS] & 0x20) != 0 /*|| (pData->aMII[0] & 0x1000)*/; 2710 2739 duplex = (pData->aBCR[BCR_MIICAS] & 0x10) != 0; 2711 2740 fast = (pData->aBCR[BCR_MIICAS] & 0x08) != 0; … … 2721 2750 val |= 0x2000; /* 100 Mbps */ 2722 2751 if (duplex) /* Full duplex forced */ 2723 val |= 0x0 010; /* Full duplex */2752 val |= 0x0100; /* Full duplex */ 2724 2753 break; 2725 2754 … … 2852 2881 } 2853 2882 #ifdef PCNET_DEBUG_BCR 2854 Log2(("#%d pcnetBCRReadU16: u32RAP=%d val=%#06x\n", PCNETSTATE_2_DEVINS(pData)->iInstance,2883 Log2(("#%d pcnetBCRReadU16: rap=%d val=%#06x\n", PCNETSTATE_2_DEVINS(pData)->iInstance, 2855 2884 u32RAP, val)); 2856 2885 #endif … … 2886 2915 pData->aBCR[BCR_BSBC ] = 0x9001; 2887 2916 pData->aBCR[BCR_EECAS] = 0x0002; 2917 pData->aBCR[BCR_STVAL] = 0xffff; 2888 2918 pData->aCSR[58 ] = /* CSR58 is an alias for BCR20 */ 2889 2919 pData->aBCR[BCR_SWS ] = 0x0200; … … 3457 3487 PDMCritSectLeave(&pData->CritSect); 3458 3488 STAM_PROFILE_ADV_STOP(&pData->StatTimer, a); 3489 } 3490 3491 /** 3492 * Software interrupt timer callback function. 3493 * 3494 * @param pDevIns Device instance of the device which registered the timer. 3495 * @param pTimer The timer handle. 3496 * @thread EMT 3497 */ 3498 static DECLCALLBACK(void) pcnetTimerSoftInt(PPDMDEVINS pDevIns, PTMTIMER pTimer) 3499 { 3500 PCNetState *pData = PDMINS2DATA(pDevIns, PCNetState *); 3501 3502 pData->aCSR[7] |= 0x0800; 3503 pcnetUpdateIrq(pData); 3504 TMTimerSet(pData->CTXSUFF(pTimerSoftInt), (uint64_t)12800 * (pData->aBCR[BCR_STVAL] & 0xffff)); 3459 3505 } 3460 3506 … … 3851 3897 { 3852 3898 PCNetState *pData = PDMINS2DATA(pDevIns, PCNetState *); 3899 int rc = VINF_SUCCESS; 3853 3900 3854 3901 SSMR3PutBool(pSSMHandle, pData->fLinkUp); … … 3870 3917 return VINF_SUCCESS; 3871 3918 #else 3872 return TMR3TimerSave(pData->CTXSUFF(pTimerPoll), pSSMHandle); 3873 #endif 3919 rc = TMR3TimerSave(pData->CTXSUFF(pTimerPoll), pSSMHandle); 3920 if (VBOX_FAILURE(rc)) 3921 return rc; 3922 #endif 3923 if (pData->fAm79C973) 3924 rc = TMR3TimerSave(pData->CTXSUFF(pTimerSoftInt), pSSMHandle); 3925 return rc; 3874 3926 } 3875 3927 … … 3905 3957 PCNetState *pData = PDMINS2DATA(pDevIns, PCNetState *); 3906 3958 PDMMAC Mac; 3907 if ( u32Version != PCNET_SAVEDSTATE_VERSION)3959 if (SSM_VERSION_MAJOR_CHANGED(u32Version, PCNET_SAVEDSTATE_VERSION)) 3908 3960 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION; 3909 3961 … … 3929 3981 TMR3TimerLoad(pData->CTXSUFF(pTimerPoll), pSSMHandle); 3930 3982 #endif 3983 if (pData->fAm79C973) 3984 { 3985 if ( SSM_VERSION_MAJOR(u32Version) > 0 3986 || SSM_VERSION_MINOR(u32Version) >= 8) 3987 TMR3TimerLoad(pData->CTXSUFF(pTimerSoftInt), pSSMHandle); 3988 } 3931 3989 3932 3990 pData->iLog2DescSize = BCR_SWSTYLE(pData) … … 4184 4242 pData->pTimerPollGC = TMTimerGCPtr(pData->pTimerPollHC); 4185 4243 #endif 4244 pData->pTimerSoftIntGC = TMTimerGCPtr(pData->pTimerSoftIntHC); 4186 4245 } 4187 4246 … … 4382 4441 if (VBOX_FAILURE(rc)) 4383 4442 { 4384 AssertMsgFailed(("pfnTMTimerCreate -> %Vrc\n", rc));4443 AssertMsgFailed(("pfnTMTimerCreate pcnetTimer -> %Vrc\n", rc)); 4385 4444 return rc; 4386 4445 } 4387 4446 #endif 4447 if (pData->fAm79C973) 4448 { 4449 /* Software Interrupt timer */ 4450 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, pcnetTimerSoftInt, 4451 "PCNet SoftInt Timer", &pData->pTimerSoftIntHC); 4452 if (VBOX_FAILURE(rc)) 4453 { 4454 AssertMsgFailed(("pfnTMTimerCreate pcnetTimerSoftInt -> %Vrc\n", rc)); 4455 return rc; 4456 } 4457 } 4388 4458 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, pcnetTimerRestore, 4389 4459 "PCNet Restore Timer", &pData->pTimerRestore); 4390 4460 if (VBOX_FAILURE(rc)) 4391 4461 { 4392 AssertMsgFailed(("pfnTMTimerCreate -> %Vrc\n", rc));4462 AssertMsgFailed(("pfnTMTimerCreate pcnetTimerRestore -> %Vrc\n", rc)); 4393 4463 return rc; 4394 4464 }
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