Changeset 70735 in vbox for trunk/src/VBox/VMM

Timestamp:

Jan 25, 2018 10:04:26 AM (7 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

120494

Message:

VMM/IEM: SVM fixes.

File:

• trunk/src/VBox/VMM/VMMAll/IEMAllCImplSvmInstr.cpp.h (modified) (2 diffs)

trunk/src/VBox/VMM/VMMAll/IEMAllCImplSvmInstr.cpp.h

@@ -675 +675 @@
             pVmcbCtrl->ExitIntInfo.n.u1Valid = 0;
 
+            /*
+             * Clear the event injection valid bit here. While the AMD spec. mentions that the CPU
+             * clears this bit from the VMCB unconditionally on #VMEXIT, internally the CPU could be
+             * clearing it at any time, most likely before/after injecting the event. Since VirtualBox
+             * doesn't have any virtual-CPU internal representation of this bit, we clear/update the
+             * VMCB here. This also has the added benefit that we avoid the risk of injecting the event
+             * twice if we fallback to executing the nesteed-guest using hardware-assisted SVM after
+             * injecting the event through IEM here.
+             */
+            pVmcbCtrl->EventInject.n.u1Valid = 0;
+
             /** @todo NRIP: Software interrupts can only be pushed properly if we support
              *        NRIP for the nested-guest to calculate the instruction length
@@ -680 +691 @@
             LogFlow(("iemSvmVmrun: Injecting event: %04x:%08RX64 vec=%#x type=%d uErr=%u cr2=%#RX64 cr3=%#RX64 efer=%#RX64\n",
                      pCtx->cs.Sel, pCtx->rip, uVector, enmType, uErrorCode, pCtx->cr2, pCtx->cr3, pCtx->msrEFER));
+#if 0
             rcStrict = IEMInjectTrap(pVCpu, uVector, enmType, uErrorCode, pCtx->cr2, 0 /* cbInstr */);
+#else
+            TRPMAssertTrap(pVCpu, uVector, enmType);
+            if (pEventInject->n.u1ErrorCodeValid)
+                TRPMSetErrorCode(pVCpu, uErrorCode);
+            if (   enmType == TRPM_TRAP
+                && uVector == X86_XCPT_PF)
+                TRPMSetFaultAddress(pVCpu, pCtx->cr2);
+#endif
         }
         else