Changeset 71108 in vbox for trunk/src/VBox/VMM/VMMR0
- Timestamp:
- Feb 22, 2018 3:38:35 PM (7 years ago)
- svn:sync-xref-src-repo-rev:
- 120973
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
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trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp
r70612 r71108 2491 2491 } 2492 2492 #endif 2493 /* 2494 * The IA32_PRED_CMD MSR is write-only and has no state associated with it. We never need to intercept 2495 * access (writes need to be executed without exiting, reds will #GP-fault anyway). 2496 */ 2497 if (pVM->cpum.ro.GuestFeatures.fIbpb) 2498 hmR0VmxSetMsrPermission(pVCpu, MSR_IA32_PRED_CMD, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE); 2499 2493 2500 /* Though MSR_IA32_PERF_GLOBAL_CTRL is saved/restored lazily, we want intercept reads/write to it for now. */ 2494 2501 } … … 6630 6637 case MSR_K8_SF_MASK: pMixedCtx->msrSFMASK = pMsr->u64Value; break; 6631 6638 case MSR_K8_KERNEL_GS_BASE: pMixedCtx->msrKERNELGSBASE = pMsr->u64Value; break; 6639 case MSR_IA32_SPEC_CTRL: CPUMR0SetGuestSpecCtrl(pVCpu, pMsr->u64Value); break; 6632 6640 case MSR_K6_EFER: /* Nothing to do here since we intercept writes, see hmR0VmxLoadGuestMsrs(). */ 6633 6641 break; … … 9172 9180 Assert(!pVCpu->hm.s.vmx.cMsrs || pVCpu->hm.s.vmx.fUpdatedHostMsrs); 9173 9181 } 9182 } 9183 9184 if (pVM->cpum.ro.GuestFeatures.fIbrs) 9185 { 9186 bool fMsrUpdated; 9187 int rc2 = hmR0VmxSaveGuestAutoLoadStoreMsrs(pVCpu, pMixedCtx); 9188 AssertRC(rc2); 9189 Assert(HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_AUTO_LOAD_STORE_MSRS)); 9190 9191 rc2 = hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_IA32_SPEC_CTRL, CPUMR0GetGuestSpecCtrl(pVCpu), true /* fUpdateHostMsr */, 9192 &fMsrUpdated); 9193 AssertRC(rc2); 9194 Assert(fMsrUpdated || pVCpu->hm.s.vmx.fUpdatedHostMsrs); 9195 /* Finally, mark that all host MSR values are updated so we don't redo it without leaving VT-x. See @bugref{6956}. */ 9196 pVCpu->hm.s.vmx.fUpdatedHostMsrs = true; 9174 9197 } 9175 9198
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